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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , xfr@outlook.com, Furong Xu <0x1207@gmail.com> Subject: [PATCH net-next v2 7/8] net: stmmac: xgmac: Complete FPE support Date: Fri, 18 Oct 2024 14:39:13 +0800 Message-Id: <1776606b2eda8430077551ca117b035f987b5b70.1729233020.git.0x1207@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Implement the necessary stmmac_fpe_ops function callbacks for xgmac. Signed-off-by: Furong Xu <0x1207@gmail.com> --- .../net/ethernet/stmicro/stmmac/stmmac_fpe.c | 77 +++++++++++++++++++ 1 file changed, 77 insertions(+) diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_fpe.c b/drivers/net= /ethernet/stmicro/stmmac/stmmac_fpe.c index dfe911b3f486..c90ed7c1279d 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_fpe.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_fpe.c @@ -373,6 +373,78 @@ static void dwxgmac3_fpe_configure(void __iomem *ioadd= r, &dwxgmac3_fpe_info); } =20 +static int dwxgmac3_fpe_irq_status(void __iomem *ioaddr, struct net_device= *dev) +{ + return common_fpe_irq_status(ioaddr + XGMAC_MAC_FPE_CTRL_STS, dev); +} + +static void dwxgmac3_fpe_send_mpacket(void __iomem *ioaddr, + struct stmmac_fpe_cfg *cfg, + enum stmmac_mpacket_type type) +{ + common_fpe_send_mpacket(ioaddr + XGMAC_MAC_FPE_CTRL_STS, cfg, type); +} + +static int dwxgmac3_fpe_get_add_frag_size(const void __iomem *ioaddr) +{ + return FIELD_GET(FPE_MTL_ADD_FRAG_SZ, + readl(ioaddr + XGMAC_MTL_FPE_CTRL_STS)); +} + +static void dwxgmac3_fpe_set_add_frag_size(void __iomem *ioaddr, + u32 add_frag_size) +{ + u32 value; + + value =3D readl(ioaddr + XGMAC_MTL_FPE_CTRL_STS); + writel(u32_replace_bits(value, add_frag_size, FPE_MTL_ADD_FRAG_SZ), + ioaddr + XGMAC_MTL_FPE_CTRL_STS); +} + +static int dwxgmac3_fpe_map_preemption_class(struct net_device *ndev, + struct netlink_ext_ack *extack, + u32 pclass) +{ + u32 val, offset, count, preemptible_txqs =3D 0; + struct stmmac_priv *priv =3D netdev_priv(ndev); + u32 num_tc =3D ndev->num_tc; + + if (!num_tc) { + /* Restore default TC:Queue mapping */ + for (u32 i =3D 0; i < priv->plat->tx_queues_to_use; i++) { + val =3D readl(priv->ioaddr + XGMAC_MTL_TXQ_OPMODE(i)); + writel(u32_replace_bits(val, i, XGMAC_Q2TCMAP), + priv->ioaddr + XGMAC_MTL_TXQ_OPMODE(i)); + } + } + + /* Synopsys Databook: + * "All Queues within a traffic class are selected in a round robin + * fashion (when packets are available) when the traffic class is + * selected by the scheduler for packet transmission. This is true for + * any of the scheduling algorithms." + */ + for (u32 tc =3D 0; tc < num_tc; tc++) { + count =3D ndev->tc_to_txq[tc].count; + offset =3D ndev->tc_to_txq[tc].offset; + + if (pclass & BIT(tc)) + preemptible_txqs |=3D GENMASK(offset + count - 1, offset); + + for (u32 i =3D 0; i < count; i++) { + val =3D readl(priv->ioaddr + XGMAC_MTL_TXQ_OPMODE(offset + i)); + writel(u32_replace_bits(val, tc, XGMAC_Q2TCMAP), + priv->ioaddr + XGMAC_MTL_TXQ_OPMODE(offset + i)); + } + } + + val =3D readl(priv->ioaddr + XGMAC_MTL_FPE_CTRL_STS); + writel(u32_replace_bits(val, preemptible_txqs, FPE_MTL_PREEMPTION_CLASS), + priv->ioaddr + XGMAC_MTL_FPE_CTRL_STS); + + return 0; +} + const struct stmmac_fpe_ops dwmac5_fpe_ops =3D { .fpe_configure =3D dwmac5_fpe_configure, .fpe_send_mpacket =3D dwmac5_fpe_send_mpacket, @@ -384,4 +456,9 @@ const struct stmmac_fpe_ops dwmac5_fpe_ops =3D { =20 const struct stmmac_fpe_ops dwxgmac_fpe_ops =3D { .fpe_configure =3D dwxgmac3_fpe_configure, + .fpe_send_mpacket =3D dwxgmac3_fpe_send_mpacket, + .fpe_irq_status =3D dwxgmac3_fpe_irq_status, + .fpe_get_add_frag_size =3D dwxgmac3_fpe_get_add_frag_size, + .fpe_set_add_frag_size =3D dwxgmac3_fpe_set_add_frag_size, + .fpe_map_preemption_class =3D dwxgmac3_fpe_map_preemption_class, }; --=20 2.34.1