From nobody Sat Jun 20 17:37:09 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 00ECC19AD5C for ; Sun, 12 Apr 2026 17:46:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776015971; cv=none; b=hKOHoEBF3leCsh/DLVTlYfcNoqSPS3BWv95RXC9YGu1PQv95jI0GX/oLVnpJOKCEYLfaoSykAu9HQshvywVh4FGc/Bw6ZeY0SWiQJ5s1YDbnyBJhTGRFygI04C6tGvqlcwnaTu01VdK+d89HI3+t7bOR3Ma9JWLNEVeWtC9DMJQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776015971; c=relaxed/simple; bh=EfcqOq3rg7iXPn1hdDKSuYC9VZIRk2XTbyOdRIh9W7k=; h=Date:From:To:Cc:Subject:References:Message-ID:Content-Type: MIME-Version; b=bABP4GenWL6AlE2wZAcmQDt7T4NTs+udT/AuYxeV5yYq1ZwHKG83z9lnzwgjKeGloVDTkjQxNPYWFDMhyHqmoevnZJvZj8KPVT3QhLM0o80fKZ7D4PkvqzuySwxArbdYltRi98RF9Z1YFgW9qECwj7wGMl2ozdc9/1pEwvQDv50= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=B+PCq8cK; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="B+PCq8cK" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1B7A1C19424; Sun, 12 Apr 2026 17:46:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1776015968; bh=EfcqOq3rg7iXPn1hdDKSuYC9VZIRk2XTbyOdRIh9W7k=; h=Date:From:To:Cc:Subject:References:From; b=B+PCq8cKSFBTqzGI56dGS1Wc+J3xCUlTSBikb3ta3G8r8taZ4OTbH+wNAgOClWs1s ZaFVLfg4K0tmcsB0cVHbkWwsDHq+oxzGw/EftVAVWEb/USE3wEgm1xWtEXRAiCGy6h Xb446GA49BdbYpCm4TWpQ4vAFeamIg/9unNItdkqPMQOGM8OcZ6A3xwVD3CrK8lhps Zi/54bolUo4dU3CrIrG0J6tbjrHQiGm3HwFeM9zv9R75yQrQGz5/lWUfk7GBsAnsAc Q4XhBzn8dKUcV0flW7Myvq2GiVQrj7SRLnqxPh8Rky7qLn+gu8J/mpXrrgblx2MIpG f4o/H8r3E5qNQ== Date: Sun, 12 Apr 2026 19:46:05 +0200 From: Thomas Gleixner To: Linus Torvalds Cc: linux-kernel@vger.kernel.org, x86@kernel.org Subject: [GIT pull] irq/core for v7.1-rc1 References: <177601563477.7932.4081917600853246368.tglx@xen13> Message-ID: <177601563724.7932.18343829723840652258.tglx@xen13> Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Linus, please pull the latest irq/core branch from: git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git irq-core-2026-= 04-12 up to: e8be82c2d77e: Drivers: hv: Move add_interrupt_randomness() to hyper= visor callback sysvec Update for the core interrupt subsystem: - Invoke add_interrupt_randomness() in handle_percpu_devid_irq() and cleanup the workaround in the Hyper-V driver, which would now invoke it twice on ARM64. Removing it from the driver requires to add it to the x86 system vector entry point. - Remove the pointles cpu_read_lock() around reading CPU possible mask, which is read only after init. - Add documentation for the interaction between device tree bindings and the interrupt type defines in irq.h. - Delete stale defines in the matrix allocator and the equivalent in loongarch. Thanks, tglx ------------------> Geert Uytterhoeven (1): genirq: Document interaction between and DT binding def= ines Michael Kelley (2): genirq/chip: Invoke add_interrupt_randomness() in handle_percpu_devid= _irq() Drivers: hv: Move add_interrupt_randomness() to hypervisor callback s= ysvec Nam Cao (1): genirq/matrix, LoongArch: Delete IRQ_MATRIX_BITS leftovers Sebastian Andrzej Siewior (1): genirq/affinity: Remove cpus_read_lock() while reading cpu_possible_m= ask arch/loongarch/include/asm/irq.h | 1 - arch/x86/kernel/cpu/mshyperv.c | 2 ++ drivers/hv/mshv_synic.c | 3 --- drivers/hv/vmbus_drv.c | 3 --- include/linux/irq.h | 4 ++++ kernel/irq/affinity.c | 7 ++----- kernel/irq/chip.c | 3 +++ kernel/irq/matrix.c | 2 +- 8 files changed, 12 insertions(+), 13 deletions(-) diff --git a/arch/loongarch/include/asm/irq.h b/arch/loongarch/include/asm/= irq.h index 3943647503a9..537add26daf4 100644 --- a/arch/loongarch/include/asm/irq.h +++ b/arch/loongarch/include/asm/irq.h @@ -48,7 +48,6 @@ void spurious_interrupt(void); */ #define NR_VECTORS 256 #define NR_LEGACY_VECTORS 16 -#define IRQ_MATRIX_BITS NR_VECTORS =20 #define AVEC_IRQ_SHIFT 4 #define AVEC_IRQ_BIT 8 diff --git a/arch/x86/kernel/cpu/mshyperv.c b/arch/x86/kernel/cpu/mshyperv.c index 9befdc557d9e..a7dfc29d3470 100644 --- a/arch/x86/kernel/cpu/mshyperv.c +++ b/arch/x86/kernel/cpu/mshyperv.c @@ -161,6 +161,8 @@ DEFINE_IDTENTRY_SYSVEC(sysvec_hyperv_callback) if (vmbus_handler) vmbus_handler(); =20 + add_interrupt_randomness(HYPERVISOR_CALLBACK_VECTOR); + if (ms_hyperv.hints & HV_DEPRECATING_AEOI_RECOMMENDED) apic_eoi(); =20 diff --git a/drivers/hv/mshv_synic.c b/drivers/hv/mshv_synic.c index 43f1bcbbf2d3..e2288a726fec 100644 --- a/drivers/hv/mshv_synic.c +++ b/drivers/hv/mshv_synic.c @@ -12,7 +12,6 @@ #include #include #include -#include #include #include #include @@ -445,8 +444,6 @@ void mshv_isr(void) mb(); if (msg->header.message_flags.msg_pending) hv_set_non_nested_msr(HV_MSR_EOM, 0); - - add_interrupt_randomness(mshv_sint_vector); } else { pr_warn_once("%s: unknown message type 0x%x\n", __func__, msg->header.message_type); diff --git a/drivers/hv/vmbus_drv.c b/drivers/hv/vmbus_drv.c index bc4fc1951ae1..e7ac79e2fb49 100644 --- a/drivers/hv/vmbus_drv.c +++ b/drivers/hv/vmbus_drv.c @@ -32,7 +32,6 @@ #include #include #include -#include #include #include #include @@ -1361,8 +1360,6 @@ static void __vmbus_isr(void) =20 vmbus_message_sched(hv_cpu, hv_cpu->hyp_synic_message_page); vmbus_message_sched(hv_cpu, hv_cpu->para_synic_message_page); - - add_interrupt_randomness(vmbus_interrupt); } =20 static DEFINE_PER_CPU(bool, vmbus_irq_pending); diff --git a/include/linux/irq.h b/include/linux/irq.h index 951acbdb9f84..efa514ee562f 100644 --- a/include/linux/irq.h +++ b/include/linux/irq.h @@ -35,6 +35,10 @@ enum irqchip_irq_state; * * Bits 0-7 are the same as the IRQF_* bits in linux/interrupt.h * + * Note that the first 6 definitions are shadowed by C preprocessor defini= tions + * in include/dt-bindings/interrupt-controller/irq.h. This is not an issu= e, as + * the actual values must be the same, due to being part of the stable DT = ABI. + * * IRQ_TYPE_NONE - default, unspecified type * IRQ_TYPE_EDGE_RISING - rising edge triggered * IRQ_TYPE_EDGE_FALLING - falling edge triggered diff --git a/kernel/irq/affinity.c b/kernel/irq/affinity.c index 85c45cfe7223..78f2418a8925 100644 --- a/kernel/irq/affinity.c +++ b/kernel/irq/affinity.c @@ -115,13 +115,10 @@ unsigned int irq_calc_affinity_vectors(unsigned int m= invec, unsigned int maxvec, if (resv > minvec) return 0; =20 - if (affd->calc_sets) { + if (affd->calc_sets) set_vecs =3D maxvec - resv; - } else { - cpus_read_lock(); + else set_vecs =3D cpumask_weight(cpu_possible_mask); - cpus_read_unlock(); - } =20 return resv + min(set_vecs, maxvec - resv); } diff --git a/kernel/irq/chip.c b/kernel/irq/chip.c index 6147a07d0127..6c9b1dc4e7d4 100644 --- a/kernel/irq/chip.c +++ b/kernel/irq/chip.c @@ -14,6 +14,7 @@ #include #include #include +#include =20 #include =20 @@ -929,6 +930,8 @@ void handle_percpu_devid_irq(struct irq_desc *desc) enabled ? " and unmasked" : "", irq, cpu); } =20 + add_interrupt_randomness(irq); + if (chip->irq_eoi) chip->irq_eoi(&desc->irq_data); } diff --git a/kernel/irq/matrix.c b/kernel/irq/matrix.c index 0f79a4abea05..faafb43a4e61 100644 --- a/kernel/irq/matrix.c +++ b/kernel/irq/matrix.c @@ -39,7 +39,7 @@ struct irq_matrix { =20 /** * irq_alloc_matrix - Allocate a irq_matrix structure and initialize it - * @matrix_bits: Number of matrix bits must be <=3D IRQ_MATRIX_BITS + * @matrix_bits: Number of matrix bits * @alloc_start: From which bit the allocation search starts * @alloc_end: At which bit the allocation search ends, i.e first * invalid bit