From nobody Sun Jun 14 17:36:39 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E349E333440; Fri, 3 Apr 2026 23:06:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775257601; cv=none; b=C4oPCtNza9a3+Q20DNKddMgyGxFIyhdwBUJOtNXnPZkGRfslkbypmdzCQI4I5+UWl5oov/I3RzIEeTG1Hhd/kU5CfQBtOp3Cb2eNd1QtpgowHVRg8TijRllJvAm4+k1v1Ly5u1TIkJBCHNJHm1uKBZn4SxuwIt6ylny5gSeuukw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775257601; c=relaxed/simple; bh=+22qV18HFSkZ+1eoKjoorO0fEIJGZP+ot4yXjxXxPdE=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=Y+VNAat6Kl/7Osf1Zn1j+3NApTe5oMuYDQWypzko9NBMwo/TGtbltBUTH8tu2aueh+HgNCCtLbOfTUG8P2LtzL/tc+7YFy7XrKhC7JFoRoC7ep/inVN8KNFJRnTceN0d2YGavhB+pfiNwzzevyEIdC8bMCQkFiQnRvPW815jFTI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=SNn2HBnS; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=Bgv/Tajd; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="SNn2HBnS"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="Bgv/Tajd" Date: Fri, 03 Apr 2026 23:06:34 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1775257597; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=KDvtsm3blUQ4KMr8R+POJUSjjO7MS+9GZZ61vFCbLmA=; b=SNn2HBnSYqf7gTMGZSy0huYcycBoDheeB4uP+yUUKVio0qmM3Vbk71pjBTCkLCtfUmUELw q+0731vZ4pzkyfjXHRRUzPfRvf3TmxJErJ/O1Hyv2hDB5QTVzkLuftfnZRcL20m4pZe6ap lQDK+1R1wO2GQmtHUXtkpPz6D3zcYCZYMLw58lLFIIBKoPxyJ0QJEaefdO/R/4CbSeUBb5 xTtIq+gyEd+6NaYBkqCy/5fAkBFP8CJt69w+kKIiVzq873tsoS1UkFmjqMziWZeArEVE7K XR/TES1l0fsOsmTFvaCURwKcNojP2Rp3BhONCfRrA/AmYocKd521WRTWzEnOag== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1775257597; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=KDvtsm3blUQ4KMr8R+POJUSjjO7MS+9GZZ61vFCbLmA=; b=Bgv/Tajd3njBZeXEkMiK5HhEoc1ntI9qJZ2vGrUWPG2ai/5CxuxJA/cA1zpgPXRN4P3nIG EWDvTNaEAvKvq3AQ== From: "tip-bot2 for Naveen N Rao (AMD)" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: x86/cleanups] x86/apic: Drop AMD Extended Interrupt LVT macros Cc: "Naveen N Rao (AMD)" , "Borislav Petkov (AMD)" , Manali Shukla , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <177525759426.1647592.12519757725623190401.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the x86/cleanups branch of tip: Commit-ID: 5635c8bfd3ab0757c5461d2165f6b284862826bf Gitweb: https://git.kernel.org/tip/5635c8bfd3ab0757c5461d2165f6b2848= 62826bf Author: Naveen N Rao (AMD) AuthorDate: Wed, 01 Apr 2026 10:26:32 +05:30 Committer: Borislav Petkov (AMD) CommitterDate: Sat, 04 Apr 2026 00:56:40 +02:00 x86/apic: Drop AMD Extended Interrupt LVT macros AMD defines Extended Interrupt Local Vector Table (EILVT) registers to allow for additional interrupt sources. While the APIC registers for those are unique to AMD, the format of those registers follows the standard LVT registers. Drop EILVT-specific macros in favor of the standard APIC LVT macros. Drop unused APIC_EILVT_NR_AMD_K8 and APIC_EILVT_LVTOFF while at it. No functional change. [ bp: Merge the two cleanup patches into one. ] Signed-off-by: Naveen N Rao (AMD) Signed-off-by: Borislav Petkov (AMD) Tested-by: Manali Shukla Link: https://patch.msgid.link/b98d69037c0102d2ccd082a941888a689cd214c9.177= 5019269.git.naveen@kernel.org --- arch/x86/events/amd/ibs.c | 6 +++--- arch/x86/include/asm/apicdef.h | 7 ------- arch/x86/kernel/apic/apic.c | 12 ++++++------ arch/x86/kernel/cpu/mce/amd.c | 6 +++--- 4 files changed, 12 insertions(+), 19 deletions(-) diff --git a/arch/x86/events/amd/ibs.c b/arch/x86/events/amd/ibs.c index aca89f2..f3a16eb 100644 --- a/arch/x86/events/amd/ibs.c +++ b/arch/x86/events/amd/ibs.c @@ -1545,7 +1545,7 @@ EXPORT_SYMBOL(get_ibs_caps); =20 static inline int get_eilvt(int offset) { - return !setup_APIC_eilvt(offset, 0, APIC_EILVT_MSG_NMI, 1); + return !setup_APIC_eilvt(offset, 0, APIC_DELIVERY_MODE_NMI, 1); } =20 static inline int put_eilvt(int offset) @@ -1694,7 +1694,7 @@ static void setup_APIC_ibs(void) if (offset < 0) goto failed; =20 - if (!setup_APIC_eilvt(offset, 0, APIC_EILVT_MSG_NMI, 0)) + if (!setup_APIC_eilvt(offset, 0, APIC_DELIVERY_MODE_NMI, 0)) return; failed: pr_warn("perf: IBS APIC setup failed on cpu #%d\n", @@ -1707,7 +1707,7 @@ static void clear_APIC_ibs(void) =20 offset =3D get_ibs_lvt_offset(); if (offset >=3D 0) - setup_APIC_eilvt(offset, 0, APIC_EILVT_MSG_FIX, 1); + setup_APIC_eilvt(offset, 0, APIC_DELIVERY_MODE_FIXED, 1); } =20 static int x86_pmu_amd_ibs_starting_cpu(unsigned int cpu) diff --git a/arch/x86/include/asm/apicdef.h b/arch/x86/include/asm/apicdef.h index be39a54..bc125c4 100644 --- a/arch/x86/include/asm/apicdef.h +++ b/arch/x86/include/asm/apicdef.h @@ -138,15 +138,8 @@ #define APIC_SEOI 0x420 #define APIC_IER 0x480 #define APIC_EILVTn(n) (0x500 + 0x10 * n) -#define APIC_EILVT_NR_AMD_K8 1 /* # of extended interrupts */ #define APIC_EILVT_NR_AMD_10H 4 #define APIC_EILVT_NR_MAX APIC_EILVT_NR_AMD_10H -#define APIC_EILVT_LVTOFF(x) (((x) >> 4) & 0xF) -#define APIC_EILVT_MSG_FIX 0x0 -#define APIC_EILVT_MSG_SMI 0x2 -#define APIC_EILVT_MSG_NMI 0x4 -#define APIC_EILVT_MSG_EXT 0x7 -#define APIC_EILVT_MASKED (1 << 16) =20 #define APIC_BASE (fix_to_virt(FIX_APIC_BASE)) #define APIC_BASE_MSR 0x800 diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c index d93f87f..eb2d825 100644 --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -332,7 +332,7 @@ static void __setup_APIC_LVTT(unsigned int clocks, int = oneshot, int irqen) * Since the offsets must be consistent for all cores, we keep track * of the LVT offsets in software and reserve the offset for the same * vector also to be used on other cores. An offset is freed by - * setting the entry to APIC_EILVT_MASKED. + * setting the entry to APIC_LVT_MASKED. * * If the BIOS is right, there should be no conflicts. Otherwise a * "[Firmware Bug]: ..." error message is generated. However, if @@ -344,9 +344,9 @@ static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX]; =20 static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int= new) { - return (old & APIC_EILVT_MASKED) - || (new =3D=3D APIC_EILVT_MASKED) - || ((new & ~APIC_EILVT_MASKED) =3D=3D old); + return (old & APIC_LVT_MASKED) + || (new =3D=3D APIC_LVT_MASKED) + || ((new & ~APIC_LVT_MASKED) =3D=3D old); } =20 static unsigned int reserve_eilvt_offset(int offset, unsigned int new) @@ -358,13 +358,13 @@ static unsigned int reserve_eilvt_offset(int offset, = unsigned int new) =20 rsvd =3D atomic_read(&eilvt_offsets[offset]); do { - vector =3D rsvd & ~APIC_EILVT_MASKED; /* 0: unassigned */ + vector =3D rsvd & ~APIC_LVT_MASKED; /* 0: unassigned */ if (vector && !eilvt_entry_is_changeable(vector, new)) /* may not change if vectors are different */ return rsvd; } while (!atomic_try_cmpxchg(&eilvt_offsets[offset], &rsvd, new)); =20 - rsvd =3D new & ~APIC_EILVT_MASKED; + rsvd =3D new & ~APIC_LVT_MASKED; if (rsvd && rsvd !=3D vector) pr_info("LVT offset %d assigned for vector 0x%02x\n", offset, rsvd); diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c index da13c1e..3a689d3 100644 --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -521,7 +521,7 @@ static void mce_threshold_block_init(struct threshold_b= lock *b, int offset) static int setup_APIC_mce_threshold(int reserved, int new) { if (reserved < 0 && !setup_APIC_eilvt(new, THRESHOLD_APIC_VECTOR, - APIC_EILVT_MSG_FIX, 0)) + APIC_DELIVERY_MODE_FIXED, 0)) return new; =20 return reserved; @@ -704,11 +704,11 @@ static void smca_enable_interrupt_vectors(void) return; =20 offset =3D (mca_intr_cfg & SMCA_THR_LVT_OFF) >> 12; - if (!setup_APIC_eilvt(offset, THRESHOLD_APIC_VECTOR, APIC_EILVT_MSG_FIX, = 0)) + if (!setup_APIC_eilvt(offset, THRESHOLD_APIC_VECTOR, APIC_DELIVERY_MODE_F= IXED, 0)) data->thr_intr_en =3D 1; =20 offset =3D (mca_intr_cfg & MASK_DEF_LVTOFF) >> 4; - if (!setup_APIC_eilvt(offset, DEFERRED_ERROR_VECTOR, APIC_EILVT_MSG_FIX, = 0)) + if (!setup_APIC_eilvt(offset, DEFERRED_ERROR_VECTOR, APIC_DELIVERY_MODE_F= IXED, 0)) data->dfr_intr_en =3D 1; } =20