From nobody Wed Apr 1 20:39:03 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5CFF93859D4; Wed, 1 Apr 2026 16:44:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775061844; cv=none; b=gneUtB4by3ghZjZPuPzk5QSsUbChbjfOK+qA7Nc5yh2LGd4P9v1ptQO9MjLNv7DGCk2HZBLuhi8qforwGBjhMI77xTMP+qdmPoPo6F6zvYj6sAWS1cLRRZ4U2yaZHBJ/5RxpVqOlxKoYAQP7/TDOxofMfBZ79yYQJxNCzL70SvI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775061844; c=relaxed/simple; bh=bktzV6w22KIginPHeLoGvWTi/VF2qR7ZdoAtaMxKPas=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=BZ01LdLnONrmSZYTCL2R6ynf6VO5YAnXTbKPSVH3ZZTvTSPjkHw20X3O2Pr3/4r/CeMrVAu/Xs0CvjBwJFaEn1OzFogxMLVhr2iKIZvuTgW7o1C7FQ7CDvfbtuMp5zrzlfx3IPUeUCqc6uajcoaVzuzg6OmeQd0mFoNshvOfy/Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=gLUTcs4q; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=dXN7zy2B; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="gLUTcs4q"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="dXN7zy2B" Date: Wed, 01 Apr 2026 16:43:59 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1775061841; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ptvynAWqHfohuSXvQu58pwYCx3IweTdBBwPtwAPaZvM=; b=gLUTcs4qz8gUj7WaIz6wwMczBzU7cOGHW2sGMC/cSTeV+Yw+9m/7jBDXCFVn9+GSAAa7wk QxYM9XT1DKdiBOXqJnIut1iXZy6mBPuuT0TzkCvTMfitU8X9sjhvACGokcGHb8ByVOSUQ9 TnxU4xNZ0YcmgfEgyl5Y6urU4QLkW7iZ3ld5psyi+FlOwMNviQfgk1Jvk9D6d2g7SguhQ2 uG2mtKrI6TI56TEP8wI6HFpjHquC4qLDKqLRlAELP4ANaH2NnJ0mp8ZYUyNvzvsnaS2oLP /F+tv5dGkb6t0xOOkYFM5dwire/fa4GdGLPIfD395LMqO1h4KnMiOw+T2U/utA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1775061841; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ptvynAWqHfohuSXvQu58pwYCx3IweTdBBwPtwAPaZvM=; b=dXN7zy2BTWLZcI7HT8XQFpj2OKFavhZNnZP+F8RYGKQYU6K3JGgVMUutnfUxzOKjB2JMbQ 4MDEnDNAIkWEIpAw== From: "tip-bot2 for Biju Das" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: irq/drivers] irqchip/renesas-rzg2l: Add NMI support Cc: Biju Das , Thomas Gleixner , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20260401114504.332825-1-biju.das.jz@bp.renesas.com> References: <20260401114504.332825-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <177506183957.1647592.8774676402488497090.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the irq/drivers branch of tip: Commit-ID: 0e5988549dc73d985cc12c4cb438771ced74f522 Gitweb: https://git.kernel.org/tip/0e5988549dc73d985cc12c4cb438771ce= d74f522 Author: Biju Das AuthorDate: Wed, 01 Apr 2026 12:45:00 +01:00 Committer: Thomas Gleixner CommitterDate: Wed, 01 Apr 2026 18:41:58 +02:00 irqchip/renesas-rzg2l: Add NMI support The RZ/G2L SoC has an NMI interrupt. Add support for the NMI interrupt. Signed-off-by: Biju Das Signed-off-by: Thomas Gleixner Link: https://patch.msgid.link/20260401114504.332825-1-biju.das.jz@bp.renes= as.com --- drivers/irqchip/irq-renesas-rzg2l.c | 99 +++++++++++++++++++++++++-- 1 file changed, 95 insertions(+), 4 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-rene= sas-rzg2l.c index 199b3c6..f6b2e69 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -20,11 +20,14 @@ #include #include =20 +#define IRQC_NMI 0 #define IRQC_IRQ_START 1 #define IRQC_TINT_COUNT 32 #define IRQC_SHARED_IRQ_COUNT 8 #define IRQC_IRQ_SHARED_START (IRQC_IRQ_START + IRQC_SHARED_IRQ_COUNT) =20 +#define NSCR 0x0 +#define NITSR 0x4 #define ISCR 0x10 #define IITSR 0x14 #define TSCR 0x20 @@ -43,6 +46,10 @@ #define TSSR_OFFSET(n) ((n) % 4) #define TSSR_INDEX(n) ((n) / 4) =20 +#define NSCR_NSTAT 0 +#define NITSR_NTSEL_EDGE_FALLING 0 +#define NITSR_NTSEL_EDGE_RISING 1 + #define TITSR_TITSEL_EDGE_RISING 0 #define TITSR_TITSEL_EDGE_FALLING 1 #define TITSR_TITSEL_LEVEL_HIGH 2 @@ -63,11 +70,13 @@ =20 /** * struct rzg2l_irqc_reg_cache - registers cache (necessary for suspend/re= sume) - * @iitsr: IITSR register - * @inttsel: INTTSEL register - * @titsr: TITSR registers + * @nitsr: NITSR register + * @iitsr: IITSR register + * @inttsel: INTTSEL register + * @titsr: TITSR registers */ struct rzg2l_irqc_reg_cache { + u32 nitsr; u32 iitsr; u32 inttsel; u32 titsr[2]; @@ -116,6 +125,28 @@ static struct rzg2l_irqc_priv *irq_data_to_priv(struct= irq_data *data) return data->domain->host_data; } =20 +static void rzg2l_clear_nmi_int(struct rzg2l_irqc_priv *priv) +{ + u32 bit =3D BIT(NSCR_NSTAT); + u32 reg; + + /* + * No locking required as the register is not shared + * with other interrupts. + * + * Writing is allowed only when NSTAT is 1 + */ + reg =3D readl_relaxed(priv->base + NSCR); + if (reg & bit) { + writel_relaxed(reg & ~bit, priv->base + NSCR); + /* + * Enforce that the posted write is flushed to prevent that the + * just handled interrupt is raised again. + */ + readl_relaxed(priv->base + NSCR); + } +} + static void rzg2l_clear_irq_int(struct rzg2l_irqc_priv *priv, unsigned int= hwirq) { unsigned int hw_irq =3D hwirq - IRQC_IRQ_START; @@ -155,6 +186,14 @@ static void rzg2l_clear_tint_int(struct rzg2l_irqc_pri= v *priv, unsigned int hwir } } =20 +static void rzg2l_irqc_nmi_eoi(struct irq_data *d) +{ + struct rzg2l_irqc_priv *priv =3D irq_data_to_priv(d); + + rzg2l_clear_nmi_int(priv); + irq_chip_eoi_parent(d); +} + static void rzg2l_irqc_irq_eoi(struct irq_data *d) { struct rzg2l_irqc_priv *priv =3D irq_data_to_priv(d); @@ -341,6 +380,26 @@ static void rzg2l_irqc_tint_enable(struct irq_data *d) irq_chip_enable_parent(d); } =20 +static int rzg2l_nmi_set_type(struct irq_data *d, unsigned int type) +{ + struct rzg2l_irqc_priv *priv =3D irq_data_to_priv(d); + u32 sense; + + switch (type & IRQ_TYPE_SENSE_MASK) { + case IRQ_TYPE_EDGE_FALLING: + sense =3D NITSR_NTSEL_EDGE_FALLING; + break; + case IRQ_TYPE_EDGE_RISING: + sense =3D NITSR_NTSEL_EDGE_RISING; + break; + default: + return -EINVAL; + } + + writel_relaxed(sense, priv->base + NITSR); + return 0; +} + static int rzg2l_irq_set_type(struct irq_data *d, unsigned int type) { struct rzg2l_irqc_priv *priv =3D irq_data_to_priv(d); @@ -467,11 +526,23 @@ static int rzg2l_irqc_tint_set_type(struct irq_data *= d, unsigned int type) return irq_chip_set_type_parent(d, IRQ_TYPE_LEVEL_HIGH); } =20 +static int rzg2l_irqc_nmi_set_type(struct irq_data *d, unsigned int type) +{ + int ret; + + ret =3D rzg2l_nmi_set_type(d, type); + if (ret) + return ret; + + return irq_chip_set_type_parent(d, IRQ_TYPE_LEVEL_HIGH); +} + static int rzg2l_irqc_irq_suspend(void *data) { struct rzg2l_irqc_reg_cache *cache =3D &rzg2l_irqc_data->cache; void __iomem *base =3D rzg2l_irqc_data->base; =20 + cache->nitsr =3D readl_relaxed(base + NITSR); cache->iitsr =3D readl_relaxed(base + IITSR); if (rzg2l_irqc_data->info.shared_irq_cnt) cache->inttsel =3D readl_relaxed(base + INTTSEL); @@ -496,6 +567,7 @@ static void rzg2l_irqc_irq_resume(void *data) if (rzg2l_irqc_data->info.shared_irq_cnt) writel_relaxed(cache->inttsel, base + INTTSEL); writel_relaxed(cache->iitsr, base + IITSR); + writel_relaxed(cache->nitsr, base + NITSR); } =20 static const struct syscore_ops rzg2l_irqc_syscore_ops =3D { @@ -507,6 +579,23 @@ static struct syscore rzg2l_irqc_syscore =3D { .ops =3D &rzg2l_irqc_syscore_ops, }; =20 +static const struct irq_chip rzg2l_irqc_nmi_chip =3D { + .name =3D "rzg2l-irqc", + .irq_eoi =3D rzg2l_irqc_nmi_eoi, + .irq_mask =3D irq_chip_mask_parent, + .irq_unmask =3D irq_chip_unmask_parent, + .irq_disable =3D irq_chip_disable_parent, + .irq_enable =3D irq_chip_enable_parent, + .irq_get_irqchip_state =3D irq_chip_get_parent_state, + .irq_set_irqchip_state =3D irq_chip_set_parent_state, + .irq_retrigger =3D irq_chip_retrigger_hierarchy, + .irq_set_type =3D rzg2l_irqc_nmi_set_type, + .irq_set_affinity =3D irq_chip_set_affinity_parent, + .flags =3D IRQCHIP_MASK_ON_SUSPEND | + IRQCHIP_SET_TYPE_MASKED | + IRQCHIP_SKIP_SET_WAKE, +}; + static const struct irq_chip rzg2l_irqc_irq_chip =3D { .name =3D "rzg2l-irqc", .irq_eoi =3D rzg2l_irqc_irq_eoi, @@ -662,7 +751,9 @@ static int rzg2l_irqc_alloc(struct irq_domain *domain, = unsigned int virq, * from 16-31 bits. TINT from the pinctrl driver needs to be programmed * in IRQC registers to enable a given gpio pin as interrupt. */ - if (hwirq > priv->info.irq_count) { + if (hwirq =3D=3D IRQC_NMI) { + chip =3D &rzg2l_irqc_nmi_chip; + } else if (hwirq > priv->info.irq_count) { tint =3D TINT_EXTRACT_GPIOINT(hwirq); hwirq =3D TINT_EXTRACT_HWIRQ(hwirq); chip =3D priv->tint_chip;