From nobody Thu Apr 2 20:41:54 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E430D40F8DB; Thu, 26 Mar 2026 16:00:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774540844; cv=none; b=bztfj7zdJIxWafotiIgYaHzDLQZ2uN8sbc9zqHuf/1WmFbKY88fJkIYv4fSAw4M54nUXB7TwksvfOMcsXJU90ikCtrshTHL+vNsRdYOx1tEMgYo1+B8CruGZBP4LBqTLmATQ6OfTnD40DEEF6qD0KODbGCdrQI5+4+H1tIGnsk4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774540844; c=relaxed/simple; bh=oNZsyNqapyONpw8DKErrRcWDrVfGPg/YjiiXcCia6cw=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=SzM6dTAGRvKM6anvoaOot1Lfv7o/ywUxtAOTIt70f9GVZUk8dSRMcrTFtcmUZCwnvdgRAy0z2OkV/jwWogE2w74F9QtbneM+yrDDfisEXHonFR8gp5YeZOYTopQklZiW6oS7FJGoZXRNL5J4fOrtwHLJP1vyRJukzpM9x18B1uw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=jKwjnmrM; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=/jhO9VXX; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="jKwjnmrM"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="/jhO9VXX" Date: Thu, 26 Mar 2026 16:00:39 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1774540841; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=iO+66U+cFo+RMLsliJxNUpisYJhIns2NFzcSd1vNcqw=; b=jKwjnmrMKGognEpdLt1RX3xoi+os8h0cNgU6CzSH7/t747p5bpTSTUF5TbTz1/Z0q2LN42 CeeOauZ6a6hDBeJThRVKcY+XY5MG7Vr6RxXbN94jipHl+LNUZ4r6BP6WB2pnuspW1kfp4x 16lSRD1hmJC3U1IV3ya+l8MTDkElTOYuRJiM4pfKBwuo+0tPKBVMIXQgVto1xMCb6UUarX 9A8wVeWKBBvN0MDGvkIambrVz0G4meXdK33SdrIx8ArN536soT7HUOgpUEQEnqbgyz0lqI hQkbZQtZLTF7KiPkJFZaBSIZFPiPEWqYA9wXKn9inMuFbrO+tTj3FyBZ3goLGQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1774540841; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=iO+66U+cFo+RMLsliJxNUpisYJhIns2NFzcSd1vNcqw=; b=/jhO9VXX/KjjDTbNhtmhGYt5dJOq3H7f7oYSaOSgY70D35yVVJ97cn2Kc8Thrm9jU++w20 avjUkIMxETvGIXDA== From: "tip-bot2 for Biju Das" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: irq/drivers] irqchip/renesas-rzg2l: Replace single irq_chip with per-region irq_chip instances Cc: Biju Das , Thomas Gleixner , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20260325192451.172562-6-biju.das.jz@bp.renesas.com> References: <20260325192451.172562-6-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <177454083966.1647592.12122600820867716363.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the irq/drivers branch of tip: Commit-ID: 4b11d14cac6ae198ea855b871c73dc208a177a0e Gitweb: https://git.kernel.org/tip/4b11d14cac6ae198ea855b871c73dc208= a177a0e Author: Biju Das AuthorDate: Wed, 25 Mar 2026 19:24:20=20 Committer: Thomas Gleixner CommitterDate: Thu, 26 Mar 2026 16:56:21 +01:00 irqchip/renesas-rzg2l: Replace single irq_chip with per-region irq_chip ins= tances The driver uses a single irq_chip instance shared across all interrupt types, relying on dispatcher callbacks to differentiate between IRQ and TINT regions at runtime. Replace the per-SoC irq_chip and its dispatcher callbacks with dedicated irq_chip instances for each interrupt region: IRQ and TINT. Subsequent patches will add per-region callbacks for IRQ and TINT from the common code. Signed-off-by: Biju Das Signed-off-by: Thomas Gleixner Link: https://patch.msgid.link/20260325192451.172562-6-biju.das.jz@bp.renes= as.com --- drivers/irqchip/irq-renesas-rzg2l.c | 61 +++++++++++++++++++++++----- 1 file changed, 51 insertions(+), 10 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-rene= sas-rzg2l.c index 8587d4c..1d1df49 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -71,14 +71,16 @@ struct rzg2l_irqc_reg_cache { /** * struct rzg2l_irqc_priv - IRQ controller private data structure * @base: Controller's base address - * @irqchip: Pointer to struct irq_chip + * @irq_chip: Pointer to struct irq_chip for irq + * @tint_chip: Pointer to struct irq_chip for tint * @fwspec: IRQ firmware specific data * @lock: Lock to serialize access to hardware registers * @cache: Registers cache for suspend/resume */ static struct rzg2l_irqc_priv { void __iomem *base; - const struct irq_chip *irqchip; + const struct irq_chip *irq_chip; + const struct irq_chip *tint_chip; struct irq_fwspec fwspec[IRQC_NUM_IRQ]; raw_spinlock_t lock; struct rzg2l_irqc_reg_cache cache; @@ -434,7 +436,7 @@ static struct syscore rzg2l_irqc_syscore =3D { .ops =3D &rzg2l_irqc_syscore_ops, }; =20 -static const struct irq_chip rzg2l_irqc_chip =3D { +static const struct irq_chip rzg2l_irqc_irq_chip =3D { .name =3D "rzg2l-irqc", .irq_eoi =3D rzg2l_irqc_eoi, .irq_mask =3D irq_chip_mask_parent, @@ -451,7 +453,41 @@ static const struct irq_chip rzg2l_irqc_chip =3D { IRQCHIP_SKIP_SET_WAKE, }; =20 -static const struct irq_chip rzfive_irqc_chip =3D { +static const struct irq_chip rzg2l_irqc_tint_chip =3D { + .name =3D "rzg2l-irqc", + .irq_eoi =3D rzg2l_irqc_eoi, + .irq_mask =3D irq_chip_mask_parent, + .irq_unmask =3D irq_chip_unmask_parent, + .irq_disable =3D rzg2l_irqc_irq_disable, + .irq_enable =3D rzg2l_irqc_irq_enable, + .irq_get_irqchip_state =3D irq_chip_get_parent_state, + .irq_set_irqchip_state =3D irq_chip_set_parent_state, + .irq_retrigger =3D irq_chip_retrigger_hierarchy, + .irq_set_type =3D rzg2l_irqc_set_type, + .irq_set_affinity =3D irq_chip_set_affinity_parent, + .flags =3D IRQCHIP_MASK_ON_SUSPEND | + IRQCHIP_SET_TYPE_MASKED | + IRQCHIP_SKIP_SET_WAKE, +}; + +static const struct irq_chip rzfive_irqc_irq_chip =3D { + .name =3D "rzfive-irqc", + .irq_eoi =3D rzg2l_irqc_eoi, + .irq_mask =3D rzfive_irqc_mask, + .irq_unmask =3D rzfive_irqc_unmask, + .irq_disable =3D rzfive_irqc_irq_disable, + .irq_enable =3D rzfive_irqc_irq_enable, + .irq_get_irqchip_state =3D irq_chip_get_parent_state, + .irq_set_irqchip_state =3D irq_chip_set_parent_state, + .irq_retrigger =3D irq_chip_retrigger_hierarchy, + .irq_set_type =3D rzg2l_irqc_set_type, + .irq_set_affinity =3D irq_chip_set_affinity_parent, + .flags =3D IRQCHIP_MASK_ON_SUSPEND | + IRQCHIP_SET_TYPE_MASKED | + IRQCHIP_SKIP_SET_WAKE, +}; + +static const struct irq_chip rzfive_irqc_tint_chip =3D { .name =3D "rzfive-irqc", .irq_eoi =3D rzg2l_irqc_eoi, .irq_mask =3D rzfive_irqc_mask, @@ -472,6 +508,7 @@ static int rzg2l_irqc_alloc(struct irq_domain *domain, = unsigned int virq, unsigned int nr_irqs, void *arg) { struct rzg2l_irqc_priv *priv =3D domain->host_data; + const struct irq_chip *chip; unsigned long tint =3D 0; irq_hw_number_t hwirq; unsigned int type; @@ -491,13 +528,15 @@ static int rzg2l_irqc_alloc(struct irq_domain *domain= , unsigned int virq, if (hwirq > IRQC_IRQ_COUNT) { tint =3D TINT_EXTRACT_GPIOINT(hwirq); hwirq =3D TINT_EXTRACT_HWIRQ(hwirq); + chip =3D priv->tint_chip; + } else { + chip =3D priv->irq_chip; } =20 if (hwirq > (IRQC_NUM_IRQ - 1)) return -EINVAL; =20 - ret =3D irq_domain_set_hwirq_and_chip(domain, virq, hwirq, priv->irqchip, - (void *)(uintptr_t)tint); + ret =3D irq_domain_set_hwirq_and_chip(domain, virq, hwirq, chip, (void *)= (uintptr_t)tint); if (ret) return ret; =20 @@ -529,7 +568,8 @@ static int rzg2l_irqc_parse_interrupts(struct rzg2l_irq= c_priv *priv, } =20 static int rzg2l_irqc_common_probe(struct platform_device *pdev, struct de= vice_node *parent, - const struct irq_chip *irq_chip) + const struct irq_chip *irq_chip, + const struct irq_chip *tint_chip) { struct irq_domain *irq_domain, *parent_domain; struct device_node *node =3D pdev->dev.of_node; @@ -545,7 +585,8 @@ static int rzg2l_irqc_common_probe(struct platform_devi= ce *pdev, struct device_n if (!rzg2l_irqc_data) return -ENOMEM; =20 - rzg2l_irqc_data->irqchip =3D irq_chip; + rzg2l_irqc_data->irq_chip =3D irq_chip; + rzg2l_irqc_data->tint_chip =3D tint_chip; =20 rzg2l_irqc_data->base =3D devm_of_iomap(dev, dev->of_node, 0, NULL); if (IS_ERR(rzg2l_irqc_data->base)) @@ -585,12 +626,12 @@ static int rzg2l_irqc_common_probe(struct platform_de= vice *pdev, struct device_n =20 static int rzg2l_irqc_probe(struct platform_device *pdev, struct device_no= de *parent) { - return rzg2l_irqc_common_probe(pdev, parent, &rzg2l_irqc_chip); + return rzg2l_irqc_common_probe(pdev, parent, &rzg2l_irqc_irq_chip, &rzg2l= _irqc_tint_chip); } =20 static int rzfive_irqc_probe(struct platform_device *pdev, struct device_n= ode *parent) { - return rzg2l_irqc_common_probe(pdev, parent, &rzfive_irqc_chip); + return rzg2l_irqc_common_probe(pdev, parent, &rzfive_irqc_irq_chip, &rzfi= ve_irqc_tint_chip); } =20 IRQCHIP_PLATFORM_DRIVER_BEGIN(rzg2l_irqc)