From nobody Thu Apr 2 20:28:23 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4A15640F8C7; Thu, 26 Mar 2026 16:00:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774540842; cv=none; b=b1AruftCrXzdICURiL3uN2H1swEiHAr3/RUshxpIYuT8vVDKXcbqcyXxVhej83fdZtD37eYrXxtrD1PQnubg6sfmHCtlsEOpKupvGVlfOeGi5a29zvIYpOmLV1J68h05xiZZ7B+w28oRKv/SH11mGW8N+RG3sEkCSCiHOXWXXD8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774540842; c=relaxed/simple; bh=5W4MLeRh/tqGvTuQ7g+PVTDZb+QbcL6bz3OxPiamURI=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=tpZhWoCoqPglyzxz2QGjV7jzG0kdhG3fLrliwLYv6fQeUPrbFeLC6jzFce/W71vQgkHRFoK2ylqTnfPPTA3oJWW6tV4QDsnUbwtOjMvrlO6dyUAnodcs7UjwLQ8S+nXovwqpRH9+l7VaGJQ3xG+XTtNWAVUe7rgqBZEQB4Wbuy0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=QAUxdTxW; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=DUFjQOtz; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="QAUxdTxW"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="DUFjQOtz" Date: Thu, 26 Mar 2026 16:00:38 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1774540839; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=BmgFHFjhbezI9AxIwxj8154/Ay9tmDyHE90RLrAl1i4=; b=QAUxdTxWl3U9hj6+RaVBK9UzDbydLbCKpjz/wW1Jsc5542ehZwRSNTRpA+crFkRMAgfybH pucwCU/Mn+Unijf2JxlUB/XMvzwxXxaOJ4M6TEjvAIpiFCFNaG0Wp/moQF5svLkPSPr0iT 44vW0AwjGlxo98StwAahVbIHmXu+6b0EJCUNwzCCziw6fhkkl2/Os5VAoOfgW4YJGgtrvt JQ3I1oJIKzc+Eze+gd7jlLlN1Ye/eNhJRpy1DOKIxEk4MbtdAMnHDx7O+3xc3/z8xLsvfc jSnS1WYK0OlS9HIwykfWkquR53mlYVl1ClaSxnk+Yo3FDzlFhpcFLe9g0ibjHg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1774540839; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=BmgFHFjhbezI9AxIwxj8154/Ay9tmDyHE90RLrAl1i4=; b=DUFjQOtz4dsW66r0Y0PiHQS6LM50bpEHBWTTVYtsiQNpCmltQoFf3yCIsRsEupm1wPMzVP iLfQ8xH9WHTYbqAQ== From: "tip-bot2 for Biju Das" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: irq/drivers] irqchip/renesas-rzg2l: Split EOI handler into separate IRQ and TINT functions Cc: Biju Das , Thomas Gleixner , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20260325192451.172562-7-biju.das.jz@bp.renesas.com> References: <20260325192451.172562-7-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <177454083800.1647592.15143870622331860191.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the irq/drivers branch of tip: Commit-ID: 6e5e0331dea48bbd6955af562aab4972a3950fa2 Gitweb: https://git.kernel.org/tip/6e5e0331dea48bbd6955af562aab4972a= 3950fa2 Author: Biju Das AuthorDate: Wed, 25 Mar 2026 19:24:21=20 Committer: Thomas Gleixner CommitterDate: Thu, 26 Mar 2026 16:56:21 +01:00 irqchip/renesas-rzg2l: Split EOI handler into separate IRQ and TINT functio= ns The common rzg2l_irqc_eoi() handler uses a conditional to determine whether to clear an IRQ or an TINT interrupt. Split this into two dedicated handlers, rzg2l_irqc_irq_eoi() and rzg2l_irqc_tint_eoi(), each handling only their respective interrupt type without the need for range checks. While at it, simplify rzg2l_irqc_{irq,tint}_eoi() by replacing raw_spin_lock locking/unlocking with scoped_guard(). Signed-off-by: Biju Das Signed-off-by: Thomas Gleixner Link: https://patch.msgid.link/20260325192451.172562-7-biju.das.jz@bp.renes= as.com --- drivers/irqchip/irq-renesas-rzg2l.c | 26 +++++++++++++++++--------- 1 file changed, 17 insertions(+), 9 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-rene= sas-rzg2l.c index 1d1df49..664599a 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -130,17 +130,25 @@ static void rzg2l_clear_tint_int(struct rzg2l_irqc_pr= iv *priv, unsigned int hwir } } =20 -static void rzg2l_irqc_eoi(struct irq_data *d) +static void rzg2l_irqc_irq_eoi(struct irq_data *d) { struct rzg2l_irqc_priv *priv =3D irq_data_to_priv(d); unsigned int hw_irq =3D irqd_to_hwirq(d); =20 - raw_spin_lock(&priv->lock); - if (hw_irq >=3D IRQC_IRQ_START && hw_irq <=3D IRQC_IRQ_COUNT) + scoped_guard(raw_spinlock, &priv->lock) rzg2l_clear_irq_int(priv, hw_irq); - else if (hw_irq >=3D IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ) + + irq_chip_eoi_parent(d); +} + +static void rzg2l_irqc_tint_eoi(struct irq_data *d) +{ + struct rzg2l_irqc_priv *priv =3D irq_data_to_priv(d); + unsigned int hw_irq =3D irqd_to_hwirq(d); + + scoped_guard(raw_spinlock, &priv->lock) rzg2l_clear_tint_int(priv, hw_irq); - raw_spin_unlock(&priv->lock); + irq_chip_eoi_parent(d); } =20 @@ -438,7 +446,7 @@ static struct syscore rzg2l_irqc_syscore =3D { =20 static const struct irq_chip rzg2l_irqc_irq_chip =3D { .name =3D "rzg2l-irqc", - .irq_eoi =3D rzg2l_irqc_eoi, + .irq_eoi =3D rzg2l_irqc_irq_eoi, .irq_mask =3D irq_chip_mask_parent, .irq_unmask =3D irq_chip_unmask_parent, .irq_disable =3D rzg2l_irqc_irq_disable, @@ -455,7 +463,7 @@ static const struct irq_chip rzg2l_irqc_irq_chip =3D { =20 static const struct irq_chip rzg2l_irqc_tint_chip =3D { .name =3D "rzg2l-irqc", - .irq_eoi =3D rzg2l_irqc_eoi, + .irq_eoi =3D rzg2l_irqc_tint_eoi, .irq_mask =3D irq_chip_mask_parent, .irq_unmask =3D irq_chip_unmask_parent, .irq_disable =3D rzg2l_irqc_irq_disable, @@ -472,7 +480,7 @@ static const struct irq_chip rzg2l_irqc_tint_chip =3D { =20 static const struct irq_chip rzfive_irqc_irq_chip =3D { .name =3D "rzfive-irqc", - .irq_eoi =3D rzg2l_irqc_eoi, + .irq_eoi =3D rzg2l_irqc_irq_eoi, .irq_mask =3D rzfive_irqc_mask, .irq_unmask =3D rzfive_irqc_unmask, .irq_disable =3D rzfive_irqc_irq_disable, @@ -489,7 +497,7 @@ static const struct irq_chip rzfive_irqc_irq_chip =3D { =20 static const struct irq_chip rzfive_irqc_tint_chip =3D { .name =3D "rzfive-irqc", - .irq_eoi =3D rzg2l_irqc_eoi, + .irq_eoi =3D rzg2l_irqc_tint_eoi, .irq_mask =3D rzfive_irqc_mask, .irq_unmask =3D rzfive_irqc_unmask, .irq_disable =3D rzfive_irqc_irq_disable,