From nobody Thu Apr 2 20:41:07 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 173CD2F5A34; Thu, 26 Mar 2026 16:00:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774540839; cv=none; b=qgCMVgW21ljaA09lMy62jUU6H5cvkdkSZ/ySIn6VlB+H3cos8RA0tWHYT+xhQjzOoGrvZ8AFrx6mBkZsr3nswAXamVilA7YHqkZI43HtBFXR4C2C7GTdk2+7HBOyKw0ijhRBEHBv8el9hcFu2frY/3J7wOYq0nYg6u4rFLxz0zg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774540839; c=relaxed/simple; bh=DCCGTN+DGaZm510lrMfqon2bgx8/QapNZt/LNvKR/tM=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=qmOwRURIwrcq2ywZOVzL77JhlsfbAlPy1c3oNIyS48iADJL0/593HWgQypg/2tEM/UuyOya0rfczj9WFdr1Wri5qczP1bMpRqQwwP54h/Pw9m3PK95f9aSxBqI1h/2DT1qTzWz0xKo3jG0QYJyUTzQGkV8EO5HNLFz+h4O64u7c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=lkyyo1Yn; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=VjDCKUC0; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="lkyyo1Yn"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="VjDCKUC0" Date: Thu, 26 Mar 2026 16:00:35 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1774540836; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=cGC1CQqfRhmFbwYNSrme2h3GU0goVXUjmBgy5SSf5E4=; b=lkyyo1YnpPuwSiAsqOe6u22PlXoIdQ+AwOgYotU9WgyVYe906hc2XSwqRp6iPEpjw0Cbc1 E2wdaNY33+j9QaKYDG4qwi9sdjovkk4Rx13PkWkBq2L4lNNZpH8TsJhqowOgDijg/aFutv 4IBRbmovTTzkUPYhR+pnvetkY/DYBJ8xkCDDTRt8WZttYydJe3zWaWwsRqPJiMGh4ClJuC mAS89iGgU56hEM/bbmDmWBiNsn4m/q34dQZMlndk9K27m117+2gNgeZSBXLxZlQZ6iXVNf +1khBsI28MA+I8C7FjR2QPGmk6X2rFdySxArlSqtf5eRUgXCT+q4Ybd/E4rDKw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1774540836; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=cGC1CQqfRhmFbwYNSrme2h3GU0goVXUjmBgy5SSf5E4=; b=VjDCKUC0lOFWSiu0b745SUp9Ax0Uk+7tMCv7ZUuvH6STwptDALlxVOAyDTEtMKIfegsT2s 1KTkVLJDTVdLC+Dw== From: "tip-bot2 for Biju Das" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: irq/drivers] irqchip/renesas-rzg2l: Replace rzg2l_irqc_irq_{enable,disable} with TINT-specific handlers Cc: Biju Das , Thomas Gleixner , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20260325192451.172562-9-biju.das.jz@bp.renesas.com> References: <20260325192451.172562-9-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <177454083510.1647592.10432373200759913153.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the irq/drivers branch of tip: Commit-ID: 83ed8efca07a076906c4c24749ee2fd5835c0ade Gitweb: https://git.kernel.org/tip/83ed8efca07a076906c4c24749ee2fd58= 35c0ade Author: Biju Das AuthorDate: Wed, 25 Mar 2026 19:24:23=20 Committer: Thomas Gleixner CommitterDate: Thu, 26 Mar 2026 16:56:21 +01:00 irqchip/renesas-rzg2l: Replace rzg2l_irqc_irq_{enable,disable} with TINT-sp= ecific handlers rzg2l_irqc_irq_disable() and rzg2l_irqc_irq_enable() are used by both the IRQ and TINT chips, but only perform TINT-specific work via rzg2l_tint_irq_endisable(), guarded by a hw_irq range check. Since the IRQ chip does not require this extra enable/disable handling, replace its callbacks with the generic irq_chip_disable_parent() and irq_chip_enable_parent() directly. While at it, simplify rzfive_irqc_irq_enable() by replacing raw_spin_lock locking/unlocking with guard() and update the variable types of offset, tssr_offset, and tssr_index to unsigned int, as these variables are used only for calculation. Signed-off-by: Biju Das Signed-off-by: Thomas Gleixner Link: https://patch.msgid.link/20260325192451.172562-9-biju.das.jz@bp.renes= as.com --- drivers/irqchip/irq-renesas-rzg2l.c | 40 ++++++++++++---------------- 1 file changed, 18 insertions(+), 22 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-rene= sas-rzg2l.c index 3d48491..ffb5316 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -259,33 +259,29 @@ static void rzfive_irqc_irq_enable(struct irq_data *d) =20 static void rzg2l_tint_irq_endisable(struct irq_data *d, bool enable) { + struct rzg2l_irqc_priv *priv =3D irq_data_to_priv(d); unsigned int hw_irq =3D irqd_to_hwirq(d); + unsigned int offset =3D hw_irq - IRQC_TINT_START; + unsigned int tssr_offset =3D TSSR_OFFSET(offset); + unsigned int tssr_index =3D TSSR_INDEX(offset); + u32 reg; =20 - if (hw_irq >=3D IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ) { - struct rzg2l_irqc_priv *priv =3D irq_data_to_priv(d); - u32 offset =3D hw_irq - IRQC_TINT_START; - u32 tssr_offset =3D TSSR_OFFSET(offset); - u8 tssr_index =3D TSSR_INDEX(offset); - u32 reg; - - raw_spin_lock(&priv->lock); - reg =3D readl_relaxed(priv->base + TSSR(tssr_index)); - if (enable) - reg |=3D TIEN << TSSEL_SHIFT(tssr_offset); - else - reg &=3D ~(TIEN << TSSEL_SHIFT(tssr_offset)); - writel_relaxed(reg, priv->base + TSSR(tssr_index)); - raw_spin_unlock(&priv->lock); - } + guard(raw_spinlock)(&priv->lock); + reg =3D readl_relaxed(priv->base + TSSR(tssr_index)); + if (enable) + reg |=3D TIEN << TSSEL_SHIFT(tssr_offset); + else + reg &=3D ~(TIEN << TSSEL_SHIFT(tssr_offset)); + writel_relaxed(reg, priv->base + TSSR(tssr_index)); } =20 -static void rzg2l_irqc_irq_disable(struct irq_data *d) +static void rzg2l_irqc_tint_disable(struct irq_data *d) { irq_chip_disable_parent(d); rzg2l_tint_irq_endisable(d, false); } =20 -static void rzg2l_irqc_irq_enable(struct irq_data *d) +static void rzg2l_irqc_tint_enable(struct irq_data *d) { rzg2l_tint_irq_endisable(d, true); irq_chip_enable_parent(d); @@ -454,8 +450,8 @@ static const struct irq_chip rzg2l_irqc_irq_chip =3D { .irq_eoi =3D rzg2l_irqc_irq_eoi, .irq_mask =3D irq_chip_mask_parent, .irq_unmask =3D irq_chip_unmask_parent, - .irq_disable =3D rzg2l_irqc_irq_disable, - .irq_enable =3D rzg2l_irqc_irq_enable, + .irq_disable =3D irq_chip_disable_parent, + .irq_enable =3D irq_chip_enable_parent, .irq_get_irqchip_state =3D irq_chip_get_parent_state, .irq_set_irqchip_state =3D irq_chip_set_parent_state, .irq_retrigger =3D irq_chip_retrigger_hierarchy, @@ -471,8 +467,8 @@ static const struct irq_chip rzg2l_irqc_tint_chip =3D { .irq_eoi =3D rzg2l_irqc_tint_eoi, .irq_mask =3D irq_chip_mask_parent, .irq_unmask =3D irq_chip_unmask_parent, - .irq_disable =3D rzg2l_irqc_irq_disable, - .irq_enable =3D rzg2l_irqc_irq_enable, + .irq_disable =3D rzg2l_irqc_tint_disable, + .irq_enable =3D rzg2l_irqc_tint_enable, .irq_get_irqchip_state =3D irq_chip_get_parent_state, .irq_set_irqchip_state =3D irq_chip_set_parent_state, .irq_retrigger =3D irq_chip_retrigger_hierarchy,