From nobody Thu Apr 2 20:22:05 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9D55640B6D8; Thu, 26 Mar 2026 16:00:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774540838; cv=none; b=BlmJgQsApToG/yJ+5pFmv8rVObLi2kZMpTCNt4yUtvJpdmU+EirIedSNnMbmQ2bLDT3Z2U1ZFwbSMUpp3kflrNKiF9eJtqpcflnpwBWBnXliP8hb2Etsr7CSSvc9OT6cQ+uOG1OEg6TuIjmOTccGaEJZGrRBruMZP8CybcAEv+w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774540838; c=relaxed/simple; bh=YjxBfoUGbnYDsR9WMb+airE5CaLrLw8zIqzyv1fm9oc=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=jNxif6UPuBDilDSEfOloiTA7RmwBNEIOCTSx55uQYXEAs1WaU16KuoJcLdJJIJfRL4v/P5z+ojYWxEFXKSTUeqpHbWo0tkxpQZcwRqUH3YzUD4Iv6LMCasy6AfzhuIjNT3/JY50/nDWTwAdLMxi3m+9qJcKIgD5ua7x/TtfwvOs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=Z9zRudV9; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=nXMJlOCq; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="Z9zRudV9"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="nXMJlOCq" Date: Thu, 26 Mar 2026 16:00:33 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1774540835; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=yA2w95xgxvXZiu0Ibxf6zyUogGx/ddOyeIegq+3TQVI=; b=Z9zRudV9vmR8pzcV4orCaablTJGoIGNgh4eydfgD4/cNcs0V8bTDrOXf1OkZG4Lt0A9lxJ ZDRDO+eIR1THpvHeu+FAauVVW23NDEVQ1ZKwCC7DAdy/LXVZjxmaZg3JLNPQF0b8y3GPTw wDgXrtJc3O8kQlJRf7M7O8qCeC4AqM48PveDISSWYCT9uBQ4fKgzlLTmQPRAdphvwkNvyC c9zwSzdv8SCkDjEawnwZoEQLZ1cJw0GRM1TQy2QRj8YpxgZnDWRGPPvVLYrH7ZwP1IZj8V sopULVBj+5YwjKZbNtT1MDB6jn2o4oxI3RFuFS7uAqxgbyUFNhAVQ3S0Cil2Mw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1774540835; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=yA2w95xgxvXZiu0Ibxf6zyUogGx/ddOyeIegq+3TQVI=; b=nXMJlOCqvYi7/tukn31Nckw+U9bWr+0sHfkY6iqZgUrTfKZ5l1G6t0ust6FVaG8xUcgNci 0UMBJzQvwp0G+uDQ== From: "tip-bot2 for Biju Das" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: irq/drivers] irqchip/renesas-rzg2l: Split rzfive_tint_irq_endisable() into separate IRQ and TINT helpers Cc: Biju Das , Thomas Gleixner , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20260325192451.172562-10-biju.das.jz@bp.renesas.com> References: <20260325192451.172562-10-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <177454083344.1647592.1289790716697502860.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the irq/drivers branch of tip: Commit-ID: 0b2675fadf4fdfdb69c492b38cc0d6f6a3e2f937 Gitweb: https://git.kernel.org/tip/0b2675fadf4fdfdb69c492b38cc0d6f6a= 3e2f937 Author: Biju Das AuthorDate: Wed, 25 Mar 2026 19:24:24=20 Committer: Thomas Gleixner CommitterDate: Thu, 26 Mar 2026 16:56:22 +01:00 irqchip/renesas-rzg2l: Split rzfive_tint_irq_endisable() into separate IRQ = and TINT helpers rzfive_tint_irq_endisable() handles both IRQ and TINT enable/disable paths via a hw_irq range check. Split this into two dedicated helpers, rzfive_irq_endisable() for IRQ interrupts and rzfive_tint_endisable() for TINT interrupts, each operating unconditionally on their respective interrupt type. While at it, simplify rzfive_{irq,tint}_endisable by replacing raw_spin_lock locking/unlocking with guard() and update the variable types of offset, tssr_offset, and tssr_index to unsigned int, as these variables are used only for calculation. Signed-off-by: Biju Das Signed-off-by: Thomas Gleixner Link: https://patch.msgid.link/20260325192451.172562-10-biju.das.jz@bp.rene= sas.com --- drivers/irqchip/irq-renesas-rzg2l.c | 75 ++++++++++++++++------------ 1 file changed, 44 insertions(+), 31 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-rene= sas-rzg2l.c index ffb5316..5417f01 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -212,48 +212,61 @@ static void rzfive_irqc_unmask(struct irq_data *d) irq_chip_unmask_parent(d); } =20 -static void rzfive_tint_irq_endisable(struct irq_data *d, bool enable) +static void rzfive_irq_endisable(struct irq_data *d, bool enable) { struct rzg2l_irqc_priv *priv =3D irq_data_to_priv(d); unsigned int hwirq =3D irqd_to_hwirq(d); =20 - if (hwirq >=3D IRQC_TINT_START && hwirq < IRQC_NUM_IRQ) { - u32 offset =3D hwirq - IRQC_TINT_START; - u32 tssr_offset =3D TSSR_OFFSET(offset); - u8 tssr_index =3D TSSR_INDEX(offset); - u32 reg; - - raw_spin_lock(&priv->lock); - if (enable) - rzfive_irqc_unmask_tint_interrupt(priv, hwirq); - else - rzfive_irqc_mask_tint_interrupt(priv, hwirq); - reg =3D readl_relaxed(priv->base + TSSR(tssr_index)); - if (enable) - reg |=3D TIEN << TSSEL_SHIFT(tssr_offset); - else - reg &=3D ~(TIEN << TSSEL_SHIFT(tssr_offset)); - writel_relaxed(reg, priv->base + TSSR(tssr_index)); - raw_spin_unlock(&priv->lock); - } else { - raw_spin_lock(&priv->lock); - if (enable) - rzfive_irqc_unmask_irq_interrupt(priv, hwirq); - else - rzfive_irqc_mask_irq_interrupt(priv, hwirq); - raw_spin_unlock(&priv->lock); - } + guard(raw_spinlock)(&priv->lock); + if (enable) + rzfive_irqc_unmask_irq_interrupt(priv, hwirq); + else + rzfive_irqc_mask_irq_interrupt(priv, hwirq); +} + +static void rzfive_tint_endisable(struct irq_data *d, bool enable) +{ + struct rzg2l_irqc_priv *priv =3D irq_data_to_priv(d); + unsigned int hwirq =3D irqd_to_hwirq(d); + unsigned int offset =3D hwirq - IRQC_TINT_START; + unsigned int tssr_offset =3D TSSR_OFFSET(offset); + unsigned int tssr_index =3D TSSR_INDEX(offset); + u32 reg; + + guard(raw_spinlock)(&priv->lock); + if (enable) + rzfive_irqc_unmask_tint_interrupt(priv, hwirq); + else + rzfive_irqc_mask_tint_interrupt(priv, hwirq); + reg =3D readl_relaxed(priv->base + TSSR(tssr_index)); + if (enable) + reg |=3D TIEN << TSSEL_SHIFT(tssr_offset); + else + reg &=3D ~(TIEN << TSSEL_SHIFT(tssr_offset)); + writel_relaxed(reg, priv->base + TSSR(tssr_index)); } =20 static void rzfive_irqc_irq_disable(struct irq_data *d) { irq_chip_disable_parent(d); - rzfive_tint_irq_endisable(d, false); + rzfive_irq_endisable(d, false); } =20 static void rzfive_irqc_irq_enable(struct irq_data *d) { - rzfive_tint_irq_endisable(d, true); + rzfive_irq_endisable(d, true); + irq_chip_enable_parent(d); +} + +static void rzfive_irqc_tint_disable(struct irq_data *d) +{ + irq_chip_disable_parent(d); + rzfive_tint_endisable(d, false); +} + +static void rzfive_irqc_tint_enable(struct irq_data *d) +{ + rzfive_tint_endisable(d, true); irq_chip_enable_parent(d); } =20 @@ -501,8 +514,8 @@ static const struct irq_chip rzfive_irqc_tint_chip =3D { .irq_eoi =3D rzg2l_irqc_tint_eoi, .irq_mask =3D rzfive_irqc_mask, .irq_unmask =3D rzfive_irqc_unmask, - .irq_disable =3D rzfive_irqc_irq_disable, - .irq_enable =3D rzfive_irqc_irq_enable, + .irq_disable =3D rzfive_irqc_tint_disable, + .irq_enable =3D rzfive_irqc_tint_enable, .irq_get_irqchip_state =3D irq_chip_get_parent_state, .irq_set_irqchip_state =3D irq_chip_set_parent_state, .irq_retrigger =3D irq_chip_retrigger_hierarchy,