From nobody Thu Apr 2 20:22:01 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F2730405AC9; Thu, 26 Mar 2026 16:00:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774540836; cv=none; b=GgkuVml2H5UYpi9j5BGXZbLFZPw5OLQr3hljvMyKx+JK42th9BNyg/YHY6NlD7ogVVkhbAOpOb5ehbeHp/tGblNfDVn0ZS3zgi8vfgRxk/u8WwBZJXEx3D1gtyBo00zsXvY9A/DbHFR470BmUVTnjqNeLbZk1jmyoeWNoZgYOKs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774540836; c=relaxed/simple; bh=0kv62cXgwD+M0m7CF/p+nftHxONNgf1Hym8x8w4yy/I=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=kK7Bt9rCDjy6mQ13jm/JRta+zSDG/BTPeCNtTsxihiV/z/X/7DOXaW7jjoXxkZcgLjiCCtdGXk+dkR/m0iJAmjx2+6LWUdPQQ7w77HHAykkQ/i5Of92pFwfg2scozGRG2VSLtiQneF0T0eCHx8Q1hvDHTgBUZnDNgKpYLpkK6fU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=NtuwfS7x; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=mOdPAd+D; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="NtuwfS7x"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="mOdPAd+D" Date: Thu, 26 Mar 2026 16:00:32 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1774540833; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=46iB5kZjLoc/7QL0DPSDPN3Wb8mg8/ohhcDSulvkUVs=; b=NtuwfS7xM46CWkYQjXIVdBfkN/DimXByUSa6wgXPCqZZ4CGiAtmQcvipBBihLidPxwBgAp lNowAMiIbYoLh5FOhln3fr0q3jYzxQPtDJJM9R9coP8ILC3XPEO3SbGggPnKP4UoXoXlGu aOuVo3SVIyRAI1ZXswO9+eeChNxIGsahFWxug5rkvTUvpOr9Z9UF0X5SkSesjdX03LkRL3 jDO9dfsLwlTigJnvXbdqo5DT5D0tuOsnznNPSuRxu5qvLw0YH/7On9PnJhUitw9jvFT4XX iW4oRIdwOSkO7Yu2C2Uo2GdM9DeOtuwxH9FYmwJ2ipkRwQ+vM4fq875QeJY10g== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1774540833; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=46iB5kZjLoc/7QL0DPSDPN3Wb8mg8/ohhcDSulvkUVs=; b=mOdPAd+DqGCy54bgO4w1KLHcx07ZIcxb7zS1tLB7ShZoPcrjSLrUMQC+Da9JtFPv4Egw3p YjhyuMnyQLnEMuAg== From: "tip-bot2 for Biju Das" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: irq/drivers] irqchip/renesas-rzg2l: Split rzfive_irqc_{mask,unmask} into separate IRQ and TINT handlers Cc: Biju Das , Thomas Gleixner , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20260325192451.172562-11-biju.das.jz@bp.renesas.com> References: <20260325192451.172562-11-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <177454083202.1647592.16326202967862417033.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the irq/drivers branch of tip: Commit-ID: bcb30669088a69cc8de2a5cf446b8b72f6b6e8eb Gitweb: https://git.kernel.org/tip/bcb30669088a69cc8de2a5cf446b8b72f= 6b6e8eb Author: Biju Das AuthorDate: Wed, 25 Mar 2026 19:24:25=20 Committer: Thomas Gleixner CommitterDate: Thu, 26 Mar 2026 16:56:22 +01:00 irqchip/renesas-rzg2l: Split rzfive_irqc_{mask,unmask} into separate IRQ an= d TINT handlers rzfive_irqc_mask() and rzfive_irqc_unmask() use hw_irq range checks to dispatch between IRQ and TINT masking operations. Split each into two dedicated handlers =E2=80=94 rzfive_irqc_irq_mask(), rzfive_irqc_tint_mask(= ), rzfive_irqc_irq_unmask(), and rzfive_irqc_tint_unmask() =E2=80=94 each oper= ating unconditionally on its respective interrupt type, removing the runtime conditionals. Assign the IRQ-specific handlers to rzfive_irqc_irq_chip and the TINT-specific handlers to rzfive_irqc_tint_chip, consistent with the separation applied to the EOI, set_type, and enable/disable callbacks in previous patches. While at it, simplify rzfive_irqc_{irq,tint}_{mask,unmask}() by replacing raw_spin_lock locking/unlocking with scoped_guard(). Signed-off-by: Biju Das Signed-off-by: Thomas Gleixner Link: https://patch.msgid.link/20260325192451.172562-11-biju.das.jz@bp.rene= sas.com --- drivers/irqchip/irq-renesas-rzg2l.c | 44 +++++++++++++++++++--------- 1 file changed, 30 insertions(+), 14 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-rene= sas-rzg2l.c index 5417f01..bb6400c 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -184,31 +184,47 @@ static void rzfive_irqc_unmask_tint_interrupt(struct = rzg2l_irqc_priv *priv, writel_relaxed(readl_relaxed(priv->base + TMSK) & ~bit, priv->base + TMSK= ); } =20 -static void rzfive_irqc_mask(struct irq_data *d) +static void rzfive_irqc_irq_mask(struct irq_data *d) { struct rzg2l_irqc_priv *priv =3D irq_data_to_priv(d); unsigned int hwirq =3D irqd_to_hwirq(d); =20 - raw_spin_lock(&priv->lock); - if (hwirq >=3D IRQC_IRQ_START && hwirq <=3D IRQC_IRQ_COUNT) + scoped_guard(raw_spinlock, &priv->lock) rzfive_irqc_mask_irq_interrupt(priv, hwirq); - else if (hwirq >=3D IRQC_TINT_START && hwirq < IRQC_NUM_IRQ) + + irq_chip_mask_parent(d); +} + +static void rzfive_irqc_tint_mask(struct irq_data *d) +{ + struct rzg2l_irqc_priv *priv =3D irq_data_to_priv(d); + unsigned int hwirq =3D irqd_to_hwirq(d); + + scoped_guard(raw_spinlock, &priv->lock) rzfive_irqc_mask_tint_interrupt(priv, hwirq); - raw_spin_unlock(&priv->lock); + irq_chip_mask_parent(d); } =20 -static void rzfive_irqc_unmask(struct irq_data *d) +static void rzfive_irqc_irq_unmask(struct irq_data *d) { struct rzg2l_irqc_priv *priv =3D irq_data_to_priv(d); unsigned int hwirq =3D irqd_to_hwirq(d); =20 - raw_spin_lock(&priv->lock); - if (hwirq >=3D IRQC_IRQ_START && hwirq <=3D IRQC_IRQ_COUNT) + scoped_guard(raw_spinlock, &priv->lock) rzfive_irqc_unmask_irq_interrupt(priv, hwirq); - else if (hwirq >=3D IRQC_TINT_START && hwirq < IRQC_NUM_IRQ) + + irq_chip_unmask_parent(d); +} + +static void rzfive_irqc_tint_unmask(struct irq_data *d) +{ + struct rzg2l_irqc_priv *priv =3D irq_data_to_priv(d); + unsigned int hwirq =3D irqd_to_hwirq(d); + + scoped_guard(raw_spinlock, &priv->lock) rzfive_irqc_unmask_tint_interrupt(priv, hwirq); - raw_spin_unlock(&priv->lock); + irq_chip_unmask_parent(d); } =20 @@ -495,8 +511,8 @@ static const struct irq_chip rzg2l_irqc_tint_chip =3D { static const struct irq_chip rzfive_irqc_irq_chip =3D { .name =3D "rzfive-irqc", .irq_eoi =3D rzg2l_irqc_irq_eoi, - .irq_mask =3D rzfive_irqc_mask, - .irq_unmask =3D rzfive_irqc_unmask, + .irq_mask =3D rzfive_irqc_irq_mask, + .irq_unmask =3D rzfive_irqc_irq_unmask, .irq_disable =3D rzfive_irqc_irq_disable, .irq_enable =3D rzfive_irqc_irq_enable, .irq_get_irqchip_state =3D irq_chip_get_parent_state, @@ -512,8 +528,8 @@ static const struct irq_chip rzfive_irqc_irq_chip =3D { static const struct irq_chip rzfive_irqc_tint_chip =3D { .name =3D "rzfive-irqc", .irq_eoi =3D rzg2l_irqc_tint_eoi, - .irq_mask =3D rzfive_irqc_mask, - .irq_unmask =3D rzfive_irqc_unmask, + .irq_mask =3D rzfive_irqc_tint_mask, + .irq_unmask =3D rzfive_irqc_tint_unmask, .irq_disable =3D rzfive_irqc_tint_disable, .irq_enable =3D rzfive_irqc_tint_enable, .irq_get_irqchip_state =3D irq_chip_get_parent_state,