From nobody Thu Apr 2 20:22:04 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 44B2540629F; Thu, 26 Mar 2026 16:00:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774540833; cv=none; b=KDsACgg2ePMHimee6mwvtLpXKSj2JUn3009J5DJjtijo+ItwuFZ+9wYzORmRUI/SNh48yzrUi1tAvAjtlinEks82FsVRkPNxfhfgMYjhUtwoB5kiIu4148HabYmqCcXU5i7VjiO+e1QsUygxa2sYjNXIC+c/4Rh4GOietmtjQEY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774540833; c=relaxed/simple; bh=fpYOsHU6yzxMBOrQFhoxylOjASHxkV81n6vN0Ab5n68=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=Cl4qDMdr/PoC2whwQXBweWuVClcfWiMT42t/erxTwFZhA/57IJQIPb2xyMNpzNNhJRJSKiUXAxuczCOISsKX0+vYBnB/TtzifmRtmqdoKbA4ePxYLqh0x4DsdRo2wlgL5h29+y6GX/45gHU9XWTLOfcfnfEzrxeEVos2SlfHkzw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=rMCG6MLQ; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=Yfc+fCsZ; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="rMCG6MLQ"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="Yfc+fCsZ" Date: Thu, 26 Mar 2026 16:00:29 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1774540830; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=0eyGduTRTmhY8AWQ0TuqhhFDGLq/rAt5ErBuTi17LX8=; b=rMCG6MLQONhqG6d/BStd0y2Q3prRWxMB21cABtRD5bHtC0M2kdKp1ORC4RBkiaLYe5q3zZ nAN4bE29i7XteNsiV+B1FjSeKsahwb+lNzY94RRRcPskFz/rNIn2zwDj9wqoWhSypIlMOy ry3UpRPOAykYh2bzr60r+UdC1EsVoIXoELOce83WH0FQS8heEP9BwRhyufydrIgUE7nipk 7r2uuDrA3uMvojwsO5Vv+M+ypDhd2uURTyPpvROeLz5u8W66W83vAZqV+lmX2tKTSewgzR 41mLJLEhfzfdKyiui0D0bgw1/fy9zhdE1EaSgJzqyoOwpHKVFo3f9akZ3v9ydA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1774540830; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=0eyGduTRTmhY8AWQ0TuqhhFDGLq/rAt5ErBuTi17LX8=; b=Yfc+fCsZUWmS1v1O8FXk8kJH/NfWSXDz5n2W+GUGkQWs2Gh0clL/eWA2PhJX1oosHljhj1 Te8iBQCEHbGrEpDA== From: "tip-bot2 for Biju Das" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: irq/drivers] irqchip/renesas-rzg2l: Drop IRQC_NUM_IRQ macro Cc: Biju Das , Thomas Gleixner , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20260325192451.172562-13-biju.das.jz@bp.renesas.com> References: <20260325192451.172562-13-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <177454082917.1647592.8303597871974865538.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the irq/drivers branch of tip: Commit-ID: 2f814778950ecc99ca5e71472b626dddb2d2b756 Gitweb: https://git.kernel.org/tip/2f814778950ecc99ca5e71472b626dddb= 2d2b756 Author: Biju Das AuthorDate: Wed, 25 Mar 2026 19:24:27=20 Committer: Thomas Gleixner CommitterDate: Thu, 26 Mar 2026 16:56:23 +01:00 irqchip/renesas-rzg2l: Drop IRQC_NUM_IRQ macro The total number of interrupts in RZ/G2L and RZ/G3L SoC are different. Introduce struct rzg2l_hw_info to handle the hardware differences and replace the macro IRQC_NUM_IRQ with num_irq variable in struct rzg2l_hw_info. Signed-off-by: Biju Das Signed-off-by: Thomas Gleixner Link: https://patch.msgid.link/20260325192451.172562-13-biju.das.jz@bp.rene= sas.com --- drivers/irqchip/irq-renesas-rzg2l.c | 34 +++++++++++++++++++++------- 1 file changed, 26 insertions(+), 8 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-rene= sas-rzg2l.c index db5d1a5..2b6dac7 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -24,7 +24,6 @@ #define IRQC_IRQ_COUNT 8 #define IRQC_TINT_START (IRQC_IRQ_START + IRQC_IRQ_COUNT) #define IRQC_TINT_COUNT 32 -#define IRQC_NUM_IRQ (IRQC_TINT_START + IRQC_TINT_COUNT) =20 #define ISCR 0x10 #define IITSR 0x14 @@ -69,12 +68,21 @@ struct rzg2l_irqc_reg_cache { }; =20 /** + * struct rzg2l_hw_info - Interrupt Control Unit controller hardware info = structure. + * @num_irq: Total Number of interrupts + */ +struct rzg2l_hw_info { + unsigned int num_irq; +}; + +/** * struct rzg2l_irqc_priv - IRQ controller private data structure * @base: Controller's base address * @irq_chip: Pointer to struct irq_chip for irq * @tint_chip: Pointer to struct irq_chip for tint * @fwspec: IRQ firmware specific data * @lock: Lock to serialize access to hardware registers + * @info: Hardware specific data * @cache: Registers cache for suspend/resume */ static struct rzg2l_irqc_priv { @@ -83,6 +91,7 @@ static struct rzg2l_irqc_priv { const struct irq_chip *tint_chip; struct irq_fwspec *fwspec; raw_spinlock_t lock; + struct rzg2l_hw_info info; struct rzg2l_irqc_reg_cache cache; } *rzg2l_irqc_data; =20 @@ -571,7 +580,7 @@ static int rzg2l_irqc_alloc(struct irq_domain *domain, = unsigned int virq, chip =3D priv->irq_chip; } =20 - if (hwirq > (IRQC_NUM_IRQ - 1)) + if (hwirq >=3D priv->info.num_irq) return -EINVAL; =20 ret =3D irq_domain_set_hwirq_and_chip(domain, virq, hwirq, chip, (void *)= (uintptr_t)tint); @@ -594,7 +603,7 @@ static int rzg2l_irqc_parse_interrupts(struct rzg2l_irq= c_priv *priv, unsigned int i; int ret; =20 - for (i =3D 0; i < IRQC_NUM_IRQ; i++) { + for (i =3D 0; i < priv->info.num_irq; i++) { ret =3D of_irq_parse_one(np, i, &map); if (ret) return ret; @@ -607,7 +616,8 @@ static int rzg2l_irqc_parse_interrupts(struct rzg2l_irq= c_priv *priv, =20 static int rzg2l_irqc_common_probe(struct platform_device *pdev, struct de= vice_node *parent, const struct irq_chip *irq_chip, - const struct irq_chip *tint_chip) + const struct irq_chip *tint_chip, + const struct rzg2l_hw_info info) { struct irq_domain *irq_domain, *parent_domain; struct device_node *node =3D pdev->dev.of_node; @@ -630,7 +640,9 @@ static int rzg2l_irqc_common_probe(struct platform_devi= ce *pdev, struct device_n if (IS_ERR(rzg2l_irqc_data->base)) return PTR_ERR(rzg2l_irqc_data->base); =20 - rzg2l_irqc_data->fwspec =3D devm_kcalloc(&pdev->dev, IRQC_NUM_IRQ, + rzg2l_irqc_data->info =3D info; + + rzg2l_irqc_data->fwspec =3D devm_kcalloc(&pdev->dev, info.num_irq, sizeof(*rzg2l_irqc_data->fwspec), GFP_KERNEL); if (!rzg2l_irqc_data->fwspec) return -ENOMEM; @@ -655,7 +667,7 @@ static int rzg2l_irqc_common_probe(struct platform_devi= ce *pdev, struct device_n =20 raw_spin_lock_init(&rzg2l_irqc_data->lock); =20 - irq_domain =3D irq_domain_create_hierarchy(parent_domain, 0, IRQC_NUM_IRQ= , dev_fwnode(dev), + irq_domain =3D irq_domain_create_hierarchy(parent_domain, 0, info.num_irq= , dev_fwnode(dev), &rzg2l_irqc_domain_ops, rzg2l_irqc_data); if (!irq_domain) { pm_runtime_put_sync(dev); @@ -667,14 +679,20 @@ static int rzg2l_irqc_common_probe(struct platform_de= vice *pdev, struct device_n return 0; } =20 +static const struct rzg2l_hw_info rzg2l_hw_params =3D { + .num_irq =3D IRQC_IRQ_START + IRQC_IRQ_COUNT + IRQC_TINT_COUNT, +}; + static int rzg2l_irqc_probe(struct platform_device *pdev, struct device_no= de *parent) { - return rzg2l_irqc_common_probe(pdev, parent, &rzg2l_irqc_irq_chip, &rzg2l= _irqc_tint_chip); + return rzg2l_irqc_common_probe(pdev, parent, &rzg2l_irqc_irq_chip, &rzg2l= _irqc_tint_chip, + rzg2l_hw_params); } =20 static int rzfive_irqc_probe(struct platform_device *pdev, struct device_n= ode *parent) { - return rzg2l_irqc_common_probe(pdev, parent, &rzfive_irqc_irq_chip, &rzfi= ve_irqc_tint_chip); + return rzg2l_irqc_common_probe(pdev, parent, &rzfive_irqc_irq_chip, &rzfi= ve_irqc_tint_chip, + rzg2l_hw_params); } =20 IRQCHIP_PLATFORM_DRIVER_BEGIN(rzg2l_irqc)