From nobody Thu Apr 2 20:21:27 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D6B9C405ABB; Thu, 26 Mar 2026 16:00:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774540832; cv=none; b=RPK8qQFdORckrZZK6yI56xUXEq0FHPKA8NtH0NbjwvB6TPlmFUbxApbrPVFsxWc52hYfJtgW7LLC4KTGVvqRWeLdRfOTR9jCD8rVqRAxoqp+Pu4pWnyHja0TlBmVrBWSFT0WjMosfqXh2QzjOlVzrLgu0YX/dbnfpJ0jixQZiGo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774540832; c=relaxed/simple; bh=x1mDv1NBSULCVKmVJcP9eG1A5J6VBL3MGswGIqjyHpA=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=qVGWwN5/P0DytD506+Aw2AX0ANIT+4bqNnMujJ8g8zmDKBMiLadQDdRaxGGGbkYURtnBMVjzEIwlCuWHcYezJdV/8ElsMOsuwA8+sA1e7SDiJ+T5kmLrZNoc+nIu9RsKn4KOup2fJUD2sQ9RTzDqfoJ2vioHyXyJWZTmC8vdyOE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=ZZG10XNx; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=NWOMA93f; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="ZZG10XNx"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="NWOMA93f" Date: Thu, 26 Mar 2026 16:00:27 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1774540829; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=gFLkPIv5DLVApdgDPEe81lIk/G9f8vCEcHbRoYC3bRM=; b=ZZG10XNxz2e2ujlvOCt8uO0PyouJ6IWWtvnb7tKNqkNYw4CqiP8DKi6rG280Y9Umzm0Atn HAASIx+DjIyxXqFmlvJ83Y4pPGYiFax5cOi6SKh0smT/YmivswoBNwcJFVRvmFsihRImrR UDOg5GIlon8wA+BtJ1q02JEfV/rARSuoceId9oe7nFcDJARF/vFoROtkCboeEKRZGQ4c+x gIluF0I9gtmx6/TQohlgScQwZvBuYqRKe9/cmA34X5L2yU5jRZ3n9t0slRPL2FX32msPSX pvQmbMS9BRTPm/b4lF8rf5I36Kg6qRmZ4YNtS1E/2oXaT3ASywmcw0QT56gFxg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1774540829; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=gFLkPIv5DLVApdgDPEe81lIk/G9f8vCEcHbRoYC3bRM=; b=NWOMA93fl1vHcZaeq1H7tSNeLxpSBMKNMksWVH4Ri0oZDFgn7AGrVol7m8Paps6xoq8ZT+ EpiwlhsnYKFxFoDQ== From: "tip-bot2 for Biju Das" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: irq/drivers] irqchip/renesas-rzg2l: Drop IRQC_TINT_START macro Cc: Biju Das , Thomas Gleixner , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20260325192451.172562-14-biju.das.jz@bp.renesas.com> References: <20260325192451.172562-14-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <177454082780.1647592.8202035979457550200.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the irq/drivers branch of tip: Commit-ID: 87404cb8cae43b680caaaa621280e71969a09147 Gitweb: https://git.kernel.org/tip/87404cb8cae43b680caaaa621280e7196= 9a09147 Author: Biju Das AuthorDate: Wed, 25 Mar 2026 19:24:28=20 Committer: Thomas Gleixner CommitterDate: Thu, 26 Mar 2026 16:56:23 +01:00 irqchip/renesas-rzg2l: Drop IRQC_TINT_START macro The IRQC_TINT_START value is different for RZ/G3L and RZ/G2L SoC. Add tint_start variable in struct rzg2l_hw_info to handle this difference and drop the macro IRQC_TINT_START. While at it, update the variable type of titseln, tssr_offset, tssr_index, index, and sense to unsigned int, in rzg2l_tint_set_edge() as these variables are used only for calculation. Signed-off-by: Biju Das Signed-off-by: Thomas Gleixner Link: https://patch.msgid.link/20260325192451.172562-14-biju.das.jz@bp.rene= sas.com --- drivers/irqchip/irq-renesas-rzg2l.c | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-rene= sas-rzg2l.c index 2b6dac7..06caa22 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -22,7 +22,6 @@ =20 #define IRQC_IRQ_START 1 #define IRQC_IRQ_COUNT 8 -#define IRQC_TINT_START (IRQC_IRQ_START + IRQC_IRQ_COUNT) #define IRQC_TINT_COUNT 32 =20 #define ISCR 0x10 @@ -69,9 +68,11 @@ struct rzg2l_irqc_reg_cache { =20 /** * struct rzg2l_hw_info - Interrupt Control Unit controller hardware info = structure. + * @tint_start: Start of TINT interrupts * @num_irq: Total Number of interrupts */ struct rzg2l_hw_info { + unsigned int tint_start; unsigned int num_irq; }; =20 @@ -125,7 +126,7 @@ static void rzg2l_clear_irq_int(struct rzg2l_irqc_priv = *priv, unsigned int hwirq =20 static void rzg2l_clear_tint_int(struct rzg2l_irqc_priv *priv, unsigned in= t hwirq) { - u32 bit =3D BIT(hwirq - IRQC_TINT_START); + u32 bit =3D BIT(hwirq - priv->info.tint_start); u32 reg; =20 reg =3D readl_relaxed(priv->base + TSCR); @@ -180,7 +181,7 @@ static void rzfive_irqc_unmask_irq_interrupt(struct rzg= 2l_irqc_priv *priv, static void rzfive_irqc_mask_tint_interrupt(struct rzg2l_irqc_priv *priv, unsigned int hwirq) { - u32 bit =3D BIT(hwirq - IRQC_TINT_START); + u32 bit =3D BIT(hwirq - priv->info.tint_start); =20 writel_relaxed(readl_relaxed(priv->base + TMSK) | bit, priv->base + TMSK); } @@ -188,7 +189,7 @@ static void rzfive_irqc_mask_tint_interrupt(struct rzg2= l_irqc_priv *priv, static void rzfive_irqc_unmask_tint_interrupt(struct rzg2l_irqc_priv *priv, unsigned int hwirq) { - u32 bit =3D BIT(hwirq - IRQC_TINT_START); + u32 bit =3D BIT(hwirq - priv->info.tint_start); =20 writel_relaxed(readl_relaxed(priv->base + TMSK) & ~bit, priv->base + TMSK= ); } @@ -253,7 +254,7 @@ static void rzfive_tint_endisable(struct irq_data *d, b= ool enable) { struct rzg2l_irqc_priv *priv =3D irq_data_to_priv(d); unsigned int hwirq =3D irqd_to_hwirq(d); - unsigned int offset =3D hwirq - IRQC_TINT_START; + unsigned int offset =3D hwirq - priv->info.tint_start; unsigned int tssr_offset =3D TSSR_OFFSET(offset); unsigned int tssr_index =3D TSSR_INDEX(offset); u32 reg; @@ -299,7 +300,7 @@ static void rzg2l_tint_irq_endisable(struct irq_data *d= , bool enable) { struct rzg2l_irqc_priv *priv =3D irq_data_to_priv(d); unsigned int hw_irq =3D irqd_to_hwirq(d); - unsigned int offset =3D hw_irq - IRQC_TINT_START; + unsigned int offset =3D hw_irq - priv->info.tint_start; unsigned int tssr_offset =3D TSSR_OFFSET(offset); unsigned int tssr_index =3D TSSR_INDEX(offset); u32 reg; @@ -388,10 +389,10 @@ static int rzg2l_tint_set_edge(struct irq_data *d, un= signed int type) { struct rzg2l_irqc_priv *priv =3D irq_data_to_priv(d); unsigned int hwirq =3D irqd_to_hwirq(d); - u32 titseln =3D hwirq - IRQC_TINT_START; - u32 tssr_offset =3D TSSR_OFFSET(titseln); - u8 tssr_index =3D TSSR_INDEX(titseln); - u8 index, sense; + unsigned int titseln =3D hwirq - priv->info.tint_start; + unsigned int tssr_offset =3D TSSR_OFFSET(titseln); + unsigned int tssr_index =3D TSSR_INDEX(titseln); + unsigned int index, sense; u32 reg, tssr; =20 switch (type & IRQ_TYPE_SENSE_MASK) { @@ -680,6 +681,7 @@ static int rzg2l_irqc_common_probe(struct platform_devi= ce *pdev, struct device_n } =20 static const struct rzg2l_hw_info rzg2l_hw_params =3D { + .tint_start =3D IRQC_IRQ_START + IRQC_IRQ_COUNT, .num_irq =3D IRQC_IRQ_START + IRQC_IRQ_COUNT + IRQC_TINT_COUNT, }; =20