From nobody Thu Apr 2 20:41:06 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 021A62F5A34; Thu, 26 Mar 2026 16:00:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774540829; cv=none; b=BCptoKCASbfer3m73E6ODgITEQOAOOuFbGhGchdu1lvrE0Hr2uMoLP6kHbOFjXf+EAC7WW1fq4wZYRlBRCoNjlpXoP39fMWUV/HYDNYtiYKMkrD3bMrnqVJO8K2UbtkRekq/AJGMAfidJ7Ee6apOb8MkzpVRuHOHJVw8erS8A/w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774540829; c=relaxed/simple; bh=Hp9LFWNpEcgA3ArvWEvIBQsBo43Yn+kjw1/OK0LrAYc=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=CgumK81OZxpk/mgVSmIVrRaB9ddFKHJfxZm0E+vck44WLXNfHlNCpiOeNYTPyeGtnLO4mu39HAZ0PFrEo3uYtOfGvdnwAvrwxnSj+2LLj7+W0JLbp3hb4uEpLZcmNVWLYAH4+ou+Dqfpo8YvpmhEkS7LYeD0OvlO3P83jf9vNoQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=bkaJ3WaU; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=7LaBPkjC; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="bkaJ3WaU"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="7LaBPkjC" Date: Thu, 26 Mar 2026 16:00:25 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1774540826; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=eJLaJY5Xg5+IrBl8c0ARR4IVbbjuJgBgYitlX5l+zw4=; b=bkaJ3WaU/1Q76pUhW1ayRkMZDtJqtmUPeNrTmrkMdbgstHTNCPwJgFHZyyM/POwvw9Z+Y+ NvHnyavd2NbzoPolRNkWynVpFD6AHsy7g5hijzHD8URwUrCSgOKytjnsMwOeiE4z/OOEve 2wjvCcOWHHlXdddElqPZBixlokAKjKHg0gZVyyCz43oh+3+knLpvKrG2CYX5se02n5oRx+ 9PyK8Z7h6WACUCOsXTRiA7ICzJx/Gpu67Ib4Ewps7rYUE8bggrEyW2p8wnw+IsWT2okfqo qii/8MUL0mZ1PvAOEX68RHWxA9Q40RVA/m2wBqU+OD/kIFY9fC7pOSY2uCdjqg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1774540826; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=eJLaJY5Xg5+IrBl8c0ARR4IVbbjuJgBgYitlX5l+zw4=; b=7LaBPkjCqkfy+V9xR9Wy5O4QNL72tI4GBGOHxVGPKSjqeMt1FrSUwhl8MNQCu+YKU+Bk3t 51wrc4OBuTWTziDw== From: "tip-bot2 for Biju Das" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: irq/drivers] irqchip/renesas-rzg2l: Add RZ/G3L support Cc: Biju Das , Thomas Gleixner , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20260325192451.172562-16-biju.das.jz@bp.renesas.com> References: <20260325192451.172562-16-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <177454082506.1647592.6222535171470583416.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the irq/drivers branch of tip: Commit-ID: 98b24d39c852d2498aae24c9aa0a3b11edb8cc2c Gitweb: https://git.kernel.org/tip/98b24d39c852d2498aae24c9aa0a3b11e= db8cc2c Author: Biju Das AuthorDate: Wed, 25 Mar 2026 19:24:30=20 Committer: Thomas Gleixner CommitterDate: Thu, 26 Mar 2026 16:56:23 +01:00 irqchip/renesas-rzg2l: Add RZ/G3L support The IRQC block on the RZ/G3L SoC is almost identical to the one found on the RZ/G2L SoC, with the following differences: - The number of GPIO interrupts for TINT selection is 113 instead of 123. - The pin index and TINT selection index are not in the 1:1 map. - The number of external interrupts are 16 instead of 8, out of these 8 external interrupts are shared with TINT. Add support for the RZ/G3L driver by filling the rzg2l_hw_info table and adding LUT for mapping between pin index and TINT selection index. Signed-off-by: Biju Das Signed-off-by: Thomas Gleixner Link: https://patch.msgid.link/20260325192451.172562-16-biju.das.jz@bp.rene= sas.com --- drivers/irqchip/irq-renesas-rzg2l.c | 48 ++++++++++++++++++++++++++-- 1 file changed, 46 insertions(+), 2 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-rene= sas-rzg2l.c index 5387e90..970126b 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -67,11 +67,13 @@ struct rzg2l_irqc_reg_cache { =20 /** * struct rzg2l_hw_info - Interrupt Control Unit controller hardware info = structure. + * @tssel_lut: TINT lookup table * @irq_count: Number of IRQC interrupts * @tint_start: Start of TINT interrupts * @num_irq: Total Number of interrupts */ struct rzg2l_hw_info { + const u8 *tssel_lut; unsigned int irq_count; unsigned int tint_start; unsigned int num_irq; @@ -331,9 +333,9 @@ static int rzg2l_irq_set_type(struct irq_data *d, unsig= ned int type) { struct rzg2l_irqc_priv *priv =3D irq_data_to_priv(d); unsigned int hwirq =3D irqd_to_hwirq(d); - u32 iitseln =3D hwirq - IRQC_IRQ_START; + unsigned int iitseln =3D hwirq - IRQC_IRQ_START; bool clear_irq_int =3D false; - u16 sense, tmp; + unsigned int sense, tmp; =20 switch (type & IRQ_TYPE_SENSE_MASK) { case IRQ_TYPE_LEVEL_LOW: @@ -377,6 +379,11 @@ static u32 rzg2l_disable_tint_and_set_tint_source(stru= ct irq_data *d, struct rzg u32 tint =3D (u32)(uintptr_t)irq_data_get_irq_chip_data(d); u32 tien =3D reg & (TIEN << TSSEL_SHIFT(tssr_offset)); =20 + if (priv->info.tssel_lut) + tint =3D priv->info.tssel_lut[tint]; + else + tint =3D (u32)(uintptr_t)irq_data_get_irq_chip_data(d); + /* Clear the relevant byte in reg */ reg &=3D ~(TSSEL_MASK << TSSEL_SHIFT(tssr_offset)); /* Set TINT and leave TIEN clear */ @@ -681,6 +688,36 @@ static int rzg2l_irqc_common_probe(struct platform_dev= ice *pdev, struct device_n return 0; } =20 +/* Mapping based on port index on Table 4.2-1 and GPIOINT on Table 4.6-7 */ +static const u8 rzg3l_tssel_lut[] =3D { + 83, 84, /* P20-P21 */ + 7, 8, 9, 10, 11, 12, 13, /* P30-P36 */ + 85, 86, 87, 88, 89, 90, 91, /* P50-P56 */ + 92, 93, 94, 95, 96, 97, 98, /* P60-P66 */ + 99, 100, 101, 102, 103, 104, 105, 106, /* P70-P77 */ + 107, 108, 109, 110, 111, 112, /* P80-P85 */ + 45, 46, 47, 48, 49, 50, 51, 52, /* PA0-PA7 */ + 53, 54, 55, 56, 57, 58, 59, 60, /* PB0-PB7 */ + 61, 62, 63, /* PC0-PC2 */ + 64, 65, 66, 67, 68, 69, 70, 71, /* PD0-PD7 */ + 72, 73, 74, 75, 76, 77, 78, 79, /* PE0-PE7 */ + 80, 81, 82, /* PF0-PF2 */ + 27, 28, 29, 30, 31, 32, 33, 34, /* PG0-PG7 */ + 35, 36, 37, 38, 39, 40, /* PH0-PH5 */ + 2, 3, 4, 5, 6, /* PJ0-PJ4 */ + 41, 42, 43, 44, /* PK0-PK3 */ + 14, 15, 16, 17, 26, /* PL0-PL4 */ + 18, 19, 20, 21, 22, 23, 24, 25, /* PM0-PM7 */ + 0, 1 /* PS0-PS1 */ +}; + +static const struct rzg2l_hw_info rzg3l_hw_params =3D { + .tssel_lut =3D rzg3l_tssel_lut, + .irq_count =3D 16, + .tint_start =3D IRQC_IRQ_START + 16, + .num_irq =3D IRQC_IRQ_START + 16 + IRQC_TINT_COUNT, +}; + static const struct rzg2l_hw_info rzg2l_hw_params =3D { .irq_count =3D 8, .tint_start =3D IRQC_IRQ_START + 8, @@ -693,6 +730,12 @@ static int rzg2l_irqc_probe(struct platform_device *pd= ev, struct device_node *pa rzg2l_hw_params); } =20 +static int rzg3l_irqc_probe(struct platform_device *pdev, struct device_no= de *parent) +{ + return rzg2l_irqc_common_probe(pdev, parent, &rzg2l_irqc_irq_chip, &rzg2l= _irqc_tint_chip, + rzg3l_hw_params); +} + static int rzfive_irqc_probe(struct platform_device *pdev, struct device_n= ode *parent) { return rzg2l_irqc_common_probe(pdev, parent, &rzfive_irqc_irq_chip, &rzfi= ve_irqc_tint_chip, @@ -701,6 +744,7 @@ static int rzfive_irqc_probe(struct platform_device *pd= ev, struct device_node *p =20 IRQCHIP_PLATFORM_DRIVER_BEGIN(rzg2l_irqc) IRQCHIP_MATCH("renesas,rzg2l-irqc", rzg2l_irqc_probe) +IRQCHIP_MATCH("renesas,r9a08g046-irqc", rzg3l_irqc_probe) IRQCHIP_MATCH("renesas,r9a07g043f-irqc", rzfive_irqc_probe) IRQCHIP_PLATFORM_DRIVER_END(rzg2l_irqc) MODULE_AUTHOR("Lad Prabhakar ");