From nobody Thu Apr 2 20:38:41 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D1C103914E6; Thu, 26 Mar 2026 16:00:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774540828; cv=none; b=P1PfAtrfgm2jfsD7/qXWid+hmVVfhXPsBJKCmWwp/HogMwGHZghwpnnMKEjTSxgpo8o3BSlQbXnwebqCo9QCirCh01qtze+liK7LQ8WTyLFRHBv9l2vCkojGY2ibrXmIZkmewPsj1K1E/IJIZ1M6evdvHlulxSZNNlIjh5GrLO4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774540828; c=relaxed/simple; bh=1hmdOu4RAzzAb7Mbwor+xqI7fH5i5cMoqtUDsO9JBgc=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=ir9M9WYf7Z2bQ3JRi3+9f8q6Gxie7tsOCTxA9pKK1NZvQbCcpfSPmdYdiR/jupdF+H6G8GDh0OGSW/krdYHJrtQs7WH0An628/bzAqT3biADeYa3YPSk1ORtz1aBMqunntT9cZ8bFr7s2MZejS7knLMsdj+KPmjoAsowBTYfwmY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=zfaj+6qz; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=kiIi6RLa; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="zfaj+6qz"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="kiIi6RLa" Date: Thu, 26 Mar 2026 16:00:23 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1774540825; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=xrmDwZcAymz95b9AllPTj36JrocUpVPF7nhh1qekHRw=; b=zfaj+6qz595S+WZD6ic3lIs5W5UStazcDk+zpAx5a/veayYsw/IA114Ku8/mnqtc8+cHvu 1DVwj81i0MkUgRik0CUPXORtno5z6Q1nE+lSbiKOsybMZ92NpKGUcfKUEBfKvYF68vfxaQ GmsEXQ8v+HRr+vYojZu/JeGgoLsmWA4Nieu8SBnJHQYRlBPcpnLIRLdbBcPKrcAlF5kBEQ CMfB9SUPHOfT2cTweNxEcsJmeHDxcwHzcLIrlSMaiCg/JkF2lmdZQ0+fC/hF9QM5M/kN5V PfKjwr0vUoRpa5zlu0kq8MwfUmQIKxR2pg/pXAnHiK+N63XRUIQFF5ExE/Ewcw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1774540825; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=xrmDwZcAymz95b9AllPTj36JrocUpVPF7nhh1qekHRw=; b=kiIi6RLawaZKE0HzJ+uN/Yc2wPMlxXQ1A3KJdbNUz9L9VPnQeerqKY5BMbUjK6Ydkg17o8 UftfFt65RphMcQCg== From: "tip-bot2 for Biju Das" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: irq/drivers] irqchip/renesas-rzg2l: Add shared interrupt support Cc: Biju Das , Thomas Gleixner , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20260325192451.172562-17-biju.das.jz@bp.renesas.com> References: <20260325192451.172562-17-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <177454082352.1647592.17295413977813209355.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the irq/drivers branch of tip: Commit-ID: e0fcae27ff572212c39b1078e7aa0795ce5970e7 Gitweb: https://git.kernel.org/tip/e0fcae27ff572212c39b1078e7aa0795c= e5970e7 Author: Biju Das AuthorDate: Wed, 25 Mar 2026 19:24:31=20 Committer: Thomas Gleixner CommitterDate: Thu, 26 Mar 2026 16:56:24 +01:00 irqchip/renesas-rzg2l: Add shared interrupt support The RZ/G3L SoC has 16 external interrupts, of which 8 are shared with TINT (GPIO interrupts), whereas RZ/G2L has only 8 external interrupts with no sharing. The shared interrupt line selection between external interrupt and GPIO interrupt is based on the INTTSEL register. Add shared_irq_cnt variable to struct rzg2l_hw_info handle these differences. Add used_irqs bitmap to struct rzg2l_irqc_priv to track allocation state. In the alloc callback, use test_and_set_bit() to enforce mutual exclusion and configure the INTTSEL register to route to either the external interrupt or TINT. In the free callback, use test_and_clear_bit() to release the shared interrupt line and reset the INTTSEL. Also add INTTSEL register save/restore support to the suspend/resume path. Signed-off-by: Biju Das Signed-off-by: Thomas Gleixner Link: https://patch.msgid.link/20260325192451.172562-17-biju.das.jz@bp.rene= sas.com --- drivers/irqchip/irq-renesas-rzg2l.c | 118 ++++++++++++++++++++++++++- 1 file changed, 115 insertions(+), 3 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-rene= sas-rzg2l.c index 970126b..f5c4d7e 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -22,6 +22,8 @@ =20 #define IRQC_IRQ_START 1 #define IRQC_TINT_COUNT 32 +#define IRQC_SHARED_IRQ_COUNT 8 +#define IRQC_IRQ_SHARED_START (IRQC_IRQ_START + IRQC_SHARED_IRQ_COUNT) =20 #define ISCR 0x10 #define IITSR 0x14 @@ -29,6 +31,7 @@ #define TITSR(n) (0x24 + (n) * 4) #define TITSR0_MAX_INT 16 #define TITSEL_WIDTH 0x2 +#define INTTSEL 0x2c #define TSSR(n) (0x30 + ((n) * 4)) #define TIEN BIT(7) #define TSSEL_SHIFT(n) (8 * (n)) @@ -52,16 +55,21 @@ #define IITSR_IITSEL_EDGE_BOTH 3 #define IITSR_IITSEL_MASK(n) IITSR_IITSEL((n), 3) =20 +#define INTTSEL_TINTSEL(n) BIT(n) +#define INTTSEL_TINTSEL_START 24 + #define TINT_EXTRACT_HWIRQ(x) FIELD_GET(GENMASK(15, 0), (x)) #define TINT_EXTRACT_GPIOINT(x) FIELD_GET(GENMASK(31, 16), (x)) =20 /** * struct rzg2l_irqc_reg_cache - registers cache (necessary for suspend/re= sume) * @iitsr: IITSR register + * @inttsel: INTTSEL register * @titsr: TITSR registers */ struct rzg2l_irqc_reg_cache { u32 iitsr; + u32 inttsel; u32 titsr[2]; }; =20 @@ -71,12 +79,14 @@ struct rzg2l_irqc_reg_cache { * @irq_count: Number of IRQC interrupts * @tint_start: Start of TINT interrupts * @num_irq: Total Number of interrupts + * @shared_irq_cnt: Number of shared interrupts */ struct rzg2l_hw_info { const u8 *tssel_lut; unsigned int irq_count; unsigned int tint_start; unsigned int num_irq; + unsigned int shared_irq_cnt; }; =20 /** @@ -88,6 +98,7 @@ struct rzg2l_hw_info { * @lock: Lock to serialize access to hardware registers * @info: Hardware specific data * @cache: Registers cache for suspend/resume + * @used_irqs: Bitmap to manage the shared interrupts */ static struct rzg2l_irqc_priv { void __iomem *base; @@ -97,6 +108,7 @@ static struct rzg2l_irqc_priv { raw_spinlock_t lock; struct rzg2l_hw_info info; struct rzg2l_irqc_reg_cache cache; + DECLARE_BITMAP(used_irqs, IRQC_SHARED_IRQ_COUNT); } *rzg2l_irqc_data; =20 static struct rzg2l_irqc_priv *irq_data_to_priv(struct irq_data *data) @@ -462,6 +474,8 @@ static int rzg2l_irqc_irq_suspend(void *data) void __iomem *base =3D rzg2l_irqc_data->base; =20 cache->iitsr =3D readl_relaxed(base + IITSR); + if (rzg2l_irqc_data->info.shared_irq_cnt) + cache->inttsel =3D readl_relaxed(base + INTTSEL); for (u8 i =3D 0; i < 2; i++) cache->titsr[i] =3D readl_relaxed(base + TITSR(i)); =20 @@ -480,6 +494,8 @@ static void rzg2l_irqc_irq_resume(void *data) */ for (u8 i =3D 0; i < 2; i++) writel_relaxed(cache->titsr[i], base + TITSR(i)); + if (rzg2l_irqc_data->info.shared_irq_cnt) + writel_relaxed(cache->inttsel, base + INTTSEL); writel_relaxed(cache->iitsr, base + IITSR); } =20 @@ -560,6 +576,72 @@ static const struct irq_chip rzfive_irqc_tint_chip =3D= { IRQCHIP_SKIP_SET_WAKE, }; =20 +static bool rzg2l_irqc_is_shared_irqc(const struct rzg2l_hw_info info, uns= igned int hw_irq) +{ + return ((hw_irq >=3D (info.tint_start - info.shared_irq_cnt)) && hw_irq <= info.tint_start); +} + +static bool rzg2l_irqc_is_shared_tint(const struct rzg2l_hw_info info, uns= igned int hw_irq) +{ + return ((hw_irq >=3D (info.num_irq - info.shared_irq_cnt)) && hw_irq < in= fo.num_irq); +} + +static bool rzg2l_irqc_is_shared_and_get_irq_num(struct rzg2l_irqc_priv *p= riv, + irq_hw_number_t hwirq, unsigned int *irq_num) +{ + bool is_shared =3D false; + + if (rzg2l_irqc_is_shared_irqc(priv->info, hwirq)) { + *irq_num =3D hwirq - IRQC_IRQ_SHARED_START; + is_shared =3D true; + } else if (rzg2l_irqc_is_shared_tint(priv->info, hwirq)) { + *irq_num =3D hwirq - IRQC_TINT_COUNT - IRQC_IRQ_SHARED_START; + is_shared =3D true; + } + + return is_shared; +} + +static void rzg2l_irqc_set_inttsel(struct rzg2l_irqc_priv *priv, unsigned = int offset, + unsigned int select_irq) +{ + u32 reg; + + guard(raw_spinlock_irqsave)(&priv->lock); + reg =3D readl_relaxed(priv->base + INTTSEL); + if (select_irq) + reg |=3D INTTSEL_TINTSEL(offset); + else + reg &=3D ~INTTSEL_TINTSEL(offset); + writel_relaxed(reg, priv->base + INTTSEL); +} + +static int rzg2l_irqc_shared_irq_alloc(struct rzg2l_irqc_priv *priv, irq_h= w_number_t hwirq) +{ + unsigned int irq_num; + + if (rzg2l_irqc_is_shared_and_get_irq_num(priv, hwirq, &irq_num)) { + if (test_and_set_bit(irq_num, priv->used_irqs)) + return -EBUSY; + + if (hwirq < priv->info.tint_start) + rzg2l_irqc_set_inttsel(priv, INTTSEL_TINTSEL_START + irq_num, 1); + else + rzg2l_irqc_set_inttsel(priv, INTTSEL_TINTSEL_START + irq_num, 0); + } + + return 0; +} + +static void rzg2l_irqc_shared_irq_free(struct rzg2l_irqc_priv *priv, irq_h= w_number_t hwirq) +{ + unsigned int irq_num; + + if (rzg2l_irqc_is_shared_and_get_irq_num(priv, hwirq, &irq_num) && + test_and_clear_bit(irq_num, priv->used_irqs)) + rzg2l_irqc_set_inttsel(priv, INTTSEL_TINTSEL_START + irq_num, 0); +} + static int rzg2l_irqc_alloc(struct irq_domain *domain, unsigned int virq, unsigned int nr_irqs, void *arg) { @@ -592,16 +674,45 @@ static int rzg2l_irqc_alloc(struct irq_domain *domain= , unsigned int virq, if (hwirq >=3D priv->info.num_irq) return -EINVAL; =20 + if (priv->info.shared_irq_cnt) { + ret =3D rzg2l_irqc_shared_irq_alloc(priv, hwirq); + if (ret) + return ret; + } + ret =3D irq_domain_set_hwirq_and_chip(domain, virq, hwirq, chip, (void *)= (uintptr_t)tint); if (ret) - return ret; + goto shared_irq_free; + + ret =3D irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, &priv->fwspec= [hwirq]); + if (ret) + goto shared_irq_free; + + return 0; + +shared_irq_free: + if (priv->info.shared_irq_cnt) + rzg2l_irqc_shared_irq_free(priv, hwirq); + + return ret; +} =20 - return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, &priv->fwspec[= hwirq]); +static void rzg2l_irqc_free(struct irq_domain *domain, unsigned int virq, = unsigned int nr_irqs) +{ + struct rzg2l_irqc_priv *priv =3D domain->host_data; + + irq_domain_free_irqs_common(domain, virq, nr_irqs); + + if (priv->info.shared_irq_cnt) { + struct irq_data *d =3D irq_domain_get_irq_data(domain, virq); + + rzg2l_irqc_shared_irq_free(priv, irqd_to_hwirq(d)); + } } =20 static const struct irq_domain_ops rzg2l_irqc_domain_ops =3D { .alloc =3D rzg2l_irqc_alloc, - .free =3D irq_domain_free_irqs_common, + .free =3D rzg2l_irqc_free, .translate =3D irq_domain_translate_twocell, }; =20 @@ -716,6 +827,7 @@ static const struct rzg2l_hw_info rzg3l_hw_params =3D { .irq_count =3D 16, .tint_start =3D IRQC_IRQ_START + 16, .num_irq =3D IRQC_IRQ_START + 16 + IRQC_TINT_COUNT, + .shared_irq_cnt =3D IRQC_SHARED_IRQ_COUNT, }; =20 static const struct rzg2l_hw_info rzg2l_hw_params =3D {