From nobody Thu Apr 2 20:22:05 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ACAB1401A26; Thu, 26 Mar 2026 15:22:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774538523; cv=none; b=PpuUDp85ZZw14/3BfKJGiCrmtYJCOUm8EBXfbFcnWtFGB/OB1LNonkGAmuJ2c6SAhgyFjYfY9rH9+Auzn4qWGIB561D+l+d9wZ64WUWZFkaAHH6ehsoXVNhmz+kbpPZuwhJ7Kmy2m/hnJAMOhXiiUVC5gDDsX04YEodj9wF5+Sc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774538523; c=relaxed/simple; bh=uwFNih96nLZU6UH7wY4Y7FEquXCaF1Bb4GPjBrB6ffM=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=BPkuhSS4a3dWmUjplFalkoLU8YsUaD86zHxa27LP8KwYtuw+eDvhKkbLSJuRr4KI/sq/Gm+nxb0T5SJPg3isxbZvCLvcHoEW5GS8MH0Qi4osNO/DE7nlGYryLY8laUWla9RiPZndgj40OK+9t096VhEIHYuOjQk0N+gTbkZwmHs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=1ENNC4ox; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=GimXOn8X; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="1ENNC4ox"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="GimXOn8X" Date: Thu, 26 Mar 2026 15:21:59 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1774538520; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=XMZ0noeXrjWePNbKJx1ks529JnLZof7viQq7nBpclzc=; b=1ENNC4oxEih7HYT6r2EcIk9LQjWWvksT+p4QHpu+NlkHxyxRZRIUwWTdQ1Njkr7oPy55xq agZcNeUb7I8jYocBiPpXm3NxSL89/4lo8UmjNUttSa18v2FxawjJnyPRpQObAc4ckn2078 ZFSGYn2qg6xeeUiFgBYZXPG/ArWLQvrgv/wj3SYWU+u5zYxHfUqCS074EdkgQfLYlvhhHA 5Q7+0C+LsSI4rmil4a9rk1y8izWkl1G22H1pzgC38qmU23M+3sRDOXHWzVWx0Dj+81VTvQ RuAWyRqCMUATC2NltTa97Adc9D/5OtVyh2Z6K4ke61QNdxc5pK4eWQ7EGPhrjw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1774538520; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=XMZ0noeXrjWePNbKJx1ks529JnLZof7viQq7nBpclzc=; b=GimXOn8XVvXP3X30DbdxttSxxdS9F57jH0rW7vhfWX9mQpsToXhZ1jFi1rNaUsxRUWHKa/ 16z1uAxyhx74apAw== From: "tip-bot2 for Icenowy Zheng" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: irq/drivers] LoongArch: Override arch_dynirq_lower_bound to reserve LPC IRQs Cc: Icenowy Zheng , Thomas Gleixner , Huacai Chen , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20260321092032.3502701-3-zhengxingda@iscas.ac.cn> References: <20260321092032.3502701-3-zhengxingda@iscas.ac.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <177453851901.1647592.7699962055637892754.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the irq/drivers branch of tip: Commit-ID: dc30127cd050dbc9d8452846ee7fa6692a1093d2 Gitweb: https://git.kernel.org/tip/dc30127cd050dbc9d8452846ee7fa6692= a1093d2 Author: Icenowy Zheng AuthorDate: Sat, 21 Mar 2026 17:20:28 +08:00 Committer: Thomas Gleixner CommitterDate: Thu, 26 Mar 2026 16:15:03 +01:00 LoongArch: Override arch_dynirq_lower_bound to reserve LPC IRQs Loongson 7A PCH chips all contain a LPC controller, which is used in some devices to connect legacy ISA devices (e.g. 8259 PS/2 controller). The LPC irqchip driver will register LPC interrupts at the fixed range 0~15, and the PCH PIC irqchip driver uses dynamic allocation. However the LPC interrupt numbers are currently not exempted from dynamic allocation. The current setup work by accident because the LPC interrupt controller is the first consumer of PIC interrupt controller, and the PIC interrupt number is allocated after LPC interrupts are registered. Such setup is fragile and will stop to work when the LPC irqchip driver is reworked. Override arch_dynirq_lower_bound() to reserve LPC interrupts from dynamic allocation, to prevent interrupt number collision and allow rework of the LPC irqchip driver. Signed-off-by: Icenowy Zheng Signed-off-by: Thomas Gleixner Reviewed-by: Huacai Chen Link: https://patch.msgid.link/20260321092032.3502701-3-zhengxingda@iscas.a= c.cn --- arch/loongarch/kernel/irq.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/loongarch/kernel/irq.c b/arch/loongarch/kernel/irq.c index 80946ca..7bf68a7 100644 --- a/arch/loongarch/kernel/irq.c +++ b/arch/loongarch/kernel/irq.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -99,6 +100,11 @@ int __init arch_probe_nr_irqs(void) return NR_IRQS_LEGACY; } =20 +unsigned int arch_dynirq_lower_bound(unsigned int from) +{ + return MAX(from, NR_IRQS_LEGACY); +} + void __init init_IRQ(void) { int i;