From nobody Mon Mar 23 19:51:58 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9F6B53AF662; Mon, 23 Mar 2026 13:58:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774274311; cv=none; b=srwZkuWJmeuUNcHC+VwOCcyXhEONj31u9In61vK4retuE3c6COi1J/DD+kNnwlDblWcrtZ0Q+M8Mtziu4cZfp183hUK2eOFfBogZ/uJVRov9nl4BFNqylc/ZoZdNVjtLlyyG8OFz6QkbiwSQ4/vY7s9XpZK2WT0viFpZKGoRhQw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774274311; c=relaxed/simple; bh=4gD6tr9BxlvC2pP4QZZ0OUmuzqKHHlAEpnL9SqGO9UE=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=S1osBcf+29Jw0zx40mJ2QJvBB4jKgFdsst7RVaaknx3gUhAxbvb6e8bXsQhhhSxCpxpMzUbfHfAzW9XMo8HzqIPpeBmKntICEu/K2oQWtlOfnByDiaEPr6+rXMwoqtoR1IsL5e4c98XI74dUdHFmWD0MuHJnRy/qoL/YETMeplM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=hgbntTHq; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=ZphS8Csg; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="hgbntTHq"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="ZphS8Csg" Date: Mon, 23 Mar 2026 13:58:26 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1774274308; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=kZL+B1rUGRLEDRSBOkzE0Pm4C4l6e05WoQJPwVnnfBo=; b=hgbntTHqjjEwt29U8ZDZofw8FjWxrgOwuWpipJ4lm0/glFhx/xtNS+OOg+RuaeIkiUClv6 FbJnKXT822OXaHOI7nISgNLNX9ETmXF+Lh3qgceoYeSoqRMxYotCXO0VgWzMyzeezu3xoK Jhht1nxIj0dqHuc/oNaHzzvWsTI5z1ELTxjkLlERgH8I2w4GY7fRWS7T165aD7pmVkMn3c cA/BMSohgqD/Uuyo9JgBJ3Xs/oRzgDf8W0VjKZRJRjOdMJqc+7z68kuuOmFUrCU56fkoHs pgGV4TXAkXJg7rNDrWvcnr4edweTprdEGAwGnj6L4IveRiX5zXdh/TjKpGoBmQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1774274308; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=kZL+B1rUGRLEDRSBOkzE0Pm4C4l6e05WoQJPwVnnfBo=; b=ZphS8Csg0B+6VyRqy9Lley2pw+Peb9rdUbTaCFtczITgvk/UWH5ldkIT4bht61WLjWk153 6zzAcAovqE0nr0Cg== From: "tip-bot2 for Nikunj A Dadhania" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: x86/urgent] x86/cpu: Enable FSGSBASE early in cpu_init_exception_handling() Cc: Borislav Petkov , Sohil Mehta , Nikunj A Dadhania , , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20260318075654.1792916-2-nikunj@amd.com> References: <20260318075654.1792916-2-nikunj@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <177427430688.1647592.16907640056817575459.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the x86/urgent branch of tip: Commit-ID: 05243d490bb7852a8acca7b5b5658019c7797a52 Gitweb: https://git.kernel.org/tip/05243d490bb7852a8acca7b5b5658019c= 7797a52 Author: Nikunj A Dadhania AuthorDate: Wed, 18 Mar 2026 07:56:52=20 Committer: Borislav Petkov (AMD) CommitterDate: Mon, 23 Mar 2026 13:29:50 +01:00 x86/cpu: Enable FSGSBASE early in cpu_init_exception_handling() Move FSGSBASE enablement from identify_cpu() to cpu_init_exception_handling= () to ensure it is enabled before any exceptions can occur on both boot and secondary CPUs. =3D=3D Background =3D=3D Exception entry code (paranoid_entry()) uses ALTERNATIVE patching based on X86_FEATURE_FSGSBASE to decide whether to use RDGSBASE/WRGSBASE instructions or the slower RDMSR/SWAPGS sequence for saving/restoring GSBASE. On boot CPU, ALTERNATIVE patching happens after enabling FSGSBASE in CR4. When the feature is available, the code is permanently patched to use RDGSBASE/WRGSBASE, which require CR4.FSGSBASE=3D1 to execute without trigge= ring =3D=3D Boot Sequence =3D=3D Boot CPU (with CR pinning enabled): trap_init() cpu_init() <- Uses unpatched code (RDMSR/SWAPGS) x2apic_setup() ... arch_cpu_finalize_init() identify_boot_cpu() identify_cpu() cr4_set_bits(X86_CR4_FSGSBASE) # Enables the feature # This becomes part of cr4_pinned_bits ... alternative_instructions() <- Patches code to use RDGSBASE/WRGSBASE Secondary CPUs (with CR pinning enabled): start_secondary() cr4_init() <- Code already patched, CR4.FSGSBASE=3D1 set implicitly via cr4_pinned_bits cpu_init() <- exceptions work because FSGSBASE is already enabled Secondary CPU (with CR pinning disabled): start_secondary() cr4_init() <- Code already patched, CR4.FSGSBASE=3D0 cpu_init() x2apic_setup() rdmsrq(MSR_IA32_APICBASE) <- Triggers #VC in SNP guests exc_vmm_communication() paranoid_entry() <- Uses RDGSBASE with CR4.FSGSBASE=3D0 (patched code) ... ap_starting() identify_secondary_cpu() identify_cpu() cr4_set_bits(X86_CR4_FSGSBASE) <- Enables the feature, which is too late =3D=3D CR Pinning =3D=3D Currently, for secondary CPUs, CR4.FSGSBASE is set implicitly through CR-pinning: the boot CPU sets it during identify_cpu(), it becomes part of cr4_pinned_bits, and cr4_init() applies those pinned bits to secondary CPUs. This works but creates an undocumented dependency between cr4_init() and the pinning mechanism. =3D=3D Problem =3D=3D Secondary CPUs boot after alternatives have been applied globally. They execute already-patched paranoid_entry() code that uses RDGSBASE/WRGSBASE instructions, which require CR4.FSGSBASE=3D1. Upcoming changes to CR pinning behavior will break the implicit dependency, causing secondary CPUs to generate #UD. This issue manifests itself on AMD SEV-SNP guests, where the rdmsrq() in x2apic_setup() triggers a #VC exception early during cpu_init(). The #VC handler (exc_vmm_communication()) executes the patched paranoid_entry() pat= h. Without CR4.FSGSBASE enabled, RDGSBASE instructions trigger #UD. =3D=3D Fix =3D=3D Enable FSGSBASE explicitly in cpu_init_exception_handling() before loading exception handlers. This makes the dependency explicit and ensures both boot and secondary CPUs have FSGSBASE enabled before paranoid_entry() executes. Fixes: c82965f9e530 ("x86/entry/64: Handle FSGSBASE enabled paranoid entry/= exit") Reported-by: Borislav Petkov Suggested-by: Sohil Mehta Signed-off-by: Nikunj A Dadhania Signed-off-by: Borislav Petkov (AMD) Reviewed-by: Sohil Mehta Cc: Link: https://patch.msgid.link/20260318075654.1792916-2-nikunj@amd.com --- arch/x86/kernel/cpu/common.c | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index a8ff437..7840b22 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -2050,12 +2050,6 @@ static void identify_cpu(struct cpuinfo_x86 *c) setup_umip(c); setup_lass(c); =20 - /* Enable FSGSBASE instructions if available. */ - if (cpu_has(c, X86_FEATURE_FSGSBASE)) { - cr4_set_bits(X86_CR4_FSGSBASE); - elf_hwcap2 |=3D HWCAP2_FSGSBASE; - } - /* * The vendor-specific functions might have changed features. * Now we do "generic changes." @@ -2416,6 +2410,18 @@ void cpu_init_exception_handling(bool boot_cpu) /* GHCB needs to be setup to handle #VC. */ setup_ghcb(); =20 + /* + * On CPUs with FSGSBASE support, paranoid_entry() uses + * ALTERNATIVE-patched RDGSBASE/WRGSBASE instructions. Secondary CPUs + * boot after alternatives are patched globally, so early exceptions + * execute patched code that depends on FSGSBASE. Enable the feature + * before any exceptions occur. + */ + if (cpu_feature_enabled(X86_FEATURE_FSGSBASE)) { + cr4_set_bits(X86_CR4_FSGSBASE); + elf_hwcap2 |=3D HWCAP2_FSGSBASE; + } + if (cpu_feature_enabled(X86_FEATURE_FRED)) { /* The boot CPU has enabled FRED during early boot */ if (!boot_cpu)