From nobody Mon Mar 23 19:52:28 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7C7CF3AEF58; Mon, 23 Mar 2026 13:58:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774274310; cv=none; b=sz+3Zy4KLR9zUEplEKPKMo80fNnNpNVla9Lh02m/rNvp1+7vwMbLJZ6eXjxypoImxs5spJ5NXbK3UQlzK+9lrpjr50th35U4KP+HQ6QFYttmvVmEm6ccnQOatkYLOxivTe+iIfsKzk41i7JjHuCZG6MRVyPk86C9FK+Kb9Zsa40= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774274310; c=relaxed/simple; bh=4BxDlolKvPEa/RTWxjYJM+/87NocGhXPkqqYUdADRRE=; h=Date:From:To:Subject:Cc:MIME-Version:Message-ID:Content-Type; b=cs8LxCsTK2k0s2uDLDfp6FByWwMc4Xtrj+xDjqnXgEgurEAbzYja/iPLGAYI+Ph9lBhrQEkIip6xTzsDLDkGAesqwDTog1XX5mJJGX5LyGRuvud3w2QN4Spwydqd8KhDcS0l8uoiA5Ao01+ep+kV6RFfHZYRvuxkm6h39UanVcY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=Awk7K9AH; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=UfevMMz3; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="Awk7K9AH"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="UfevMMz3" Date: Mon, 23 Mar 2026 13:58:25 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1774274307; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=P3eBuERsyckpo1Vdo3TYEBf2FvzIRx/OtEhQmcbQbMI=; b=Awk7K9AH5zGrjVJVGIkCU8lvxwAByear+/G5GeicsCyfB7IL52HouaIxQG9E6o1rjBStNf I5BB9AbEcY4g8LxmlwdKxfmuDVAzpi+phv1eXYfoAm25vIFl9z+TRdye6NjZi8UighPpJI 21H69AkDYg/15mF80E+a+AKQOQIBVH6nXPsb15aiuXxmJblgTgJgKQFIRkX6+CFfugOnY8 1OQSKX/SAwKGN7JvtRQ6+OhlbxLOr6QKTk+FAF2N7dy18yqW/ZZ3aXANk3amn3QfDNUK4m nocWGbCAnqGW9yPdex0GH42P0LzmR1IeYqrBYDI1ofeHKF1UEeRbbydPNnj/Hw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1774274307; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=P3eBuERsyckpo1Vdo3TYEBf2FvzIRx/OtEhQmcbQbMI=; b=UfevMMz3TOt+chqCL7Z+GCtmh74UAccWO8pS/j9DDX6YYdG/1DZCb8ZLDPfeGB/jbwJ0pd sjLqneR+bQeIm6AA== From: "tip-bot2 for Borislav Petkov (AMD)" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: x86/urgent] x86/cpu: Remove X86_CR4_FRED from the CR4 pinned bits mask Cc: Dave Hansen , Peter Zijlstra , "Borislav Petkov (AMD)" , , x86@kernel.org, linux-kernel@vger.kernel.org Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <177427430580.1647592.1807131043053392753.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the x86/urgent branch of tip: Commit-ID: 411df123c017169922cc767affce76282b8e6c85 Gitweb: https://git.kernel.org/tip/411df123c017169922cc767affce76282= b8e6c85 Author: Borislav Petkov (AMD) AuthorDate: Thu, 19 Mar 2026 12:07:59 +01:00 Committer: Borislav Petkov (AMD) CommitterDate: Mon, 23 Mar 2026 14:12:03 +01:00 x86/cpu: Remove X86_CR4_FRED from the CR4 pinned bits mask Commit in Fixes added the FRED CR4 bit to the CR4 pinned bits mask so that whenever something else modifies CR4, that bit remains set. Which in itself is a perfectly fine idea. However, there's an issue when during boot FRED is initialized: first on the BSP and later on the APs. Thus, there's a window in time when exceptions cannot be handled. This becomes particularly nasty when running as SEV-{ES,SNP} or TDX guests which, when they manage to trigger exceptions during that short window described above, triple fault due to FRED MSRs not being set up yet. See Link tag below for a much more detailed explanation of the situation. So, as a result, the commit in that Link URL tried to address this shortcoming by temporarily disabling CR4 pinning when an AP is not online yet. However, that is a problem in itself because in this case, an attack on the kernel needs to only modify the online bit - a single bit in RW memory - and then disable CR4 pinning and then disable SM*P, leading to more and worse things to happen to the system. So, instead, remove the FRED bit from the CR4 pinning mask, thus obviating the need to temporarily disable CR4 pinning. If someone manages to disable FRED when poking at CR4, then idt_invalidate() would make sure the system would crash'n'burn on the first exception triggered, which is a much better outcome security-wise. Fixes: ff45746fbf00 ("x86/cpu: Add X86_CR4_FRED macro") Suggested-by: Dave Hansen Suggested-by: Peter Zijlstra Signed-off-by: Borislav Petkov (AMD) Cc: # 6.12+ Link: https://lore.kernel.org/r/177385987098.1647592.3381141860481415647.ti= p-bot2@tip-bot2 --- arch/x86/kernel/cpu/common.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 7840b22..c57e897 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -433,7 +433,7 @@ static __always_inline void setup_lass(struct cpuinfo_x= 86 *c) =20 /* These bits should not change their value after CPU init is finished. */ static const unsigned long cr4_pinned_mask =3D X86_CR4_SMEP | X86_CR4_SMAP= | X86_CR4_UMIP | - X86_CR4_FSGSBASE | X86_CR4_CET | X86_CR4_FRED; + X86_CR4_FSGSBASE | X86_CR4_CET; static DEFINE_STATIC_KEY_FALSE_RO(cr_pinning); static unsigned long cr4_pinned_bits __ro_after_init; =20