From nobody Mon Apr 6 16:47:57 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3D7A0332EBC; Wed, 18 Mar 2026 20:34:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773866075; cv=none; b=ZhT+ruKtyf6YYKhXvSN0jRHXd57xinf8a7BR3yDlDkEcP+xciTXygJnbcWky51GJaWOv+LkDu4coo3b9eLMlFgbCWfMNOxRJ5G0FADDHpFh0UdexaBmYU4ORSuzhV/zg4bzh7e1VPAzps1xUMUalrPb9kZ+MUyppIpp6WjIA+AA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773866075; c=relaxed/simple; bh=KvShYZ+D3Imm33PtX93U5t+SJ7ZnabW+H9ks1KboTBk=; h=Date:From:To:Subject:Cc:MIME-Version:Message-ID:Content-Type; b=mQSjJiuFMscxgB2nYtfc1AB3o8wP8KP7BxxSReJJypniJGrfesEu0ZhM5pJhKo+Icj0vILMfl2OWnuYCZAXzzrLCeadfIqZPeHRgpwgnYLrchm7W76coNBcElWcY3N9iWFpmch8ODzverB9J28JAfmgIAPvMWEhWE7uaz6G4PN4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=mTfr1La5; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=LoD6KGKV; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="mTfr1La5"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="LoD6KGKV" Date: Wed, 18 Mar 2026 20:34:30 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1773866071; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=8OpgSssdpfR3nI4URVD7jxzVdwKlRfyiiQadySN4dAc=; b=mTfr1La5bKTueR8K0fDatJezgfjzyZiDeaLsOG6xkJsoQ6Gv6UU3KF/bFnlRgV7eJ9m2Um Ly6f7THscEWiTq8aA73jc6V4NNFZSiYo64QCFEflLNMXXko3blZlTIlpksHwWumMTfrNAR yZaE4t841NakE+7vXjCW69ulBO1v3xAuP5AQ6Eqjl8kzMjA1y+IwGy0qXPGSNoM+zexaRe rc1ovs9jR4OZdiRU8qzIy5yi7wP2EUp+30VeAMhwMcEtTBBu81GJTUoUyZxMIGn2E1cdwU 4pWv5kDgiqFtvv2ihrLm6Kpsr9vDbrpAAUDBc5GvHcnhZ4MqKfuLYPIQ9s86Hw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1773866071; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=8OpgSssdpfR3nI4URVD7jxzVdwKlRfyiiQadySN4dAc=; b=LoD6KGKVvjb207Yf9FCJqckgioO6ho6I/qBhoFEn6SRUtr5/ToIojlbaWD7/8OS6TzSX09 SrDmkAiLHc0Yb/AQ== From: "tip-bot2 for William Roche" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: x86/urgent] x86/mce/amd: Check SMCA feature bit before accessing SMCA MSRs Cc: William Roche , "Borislav Petkov (AMD)" , Yazen Ghannam , stable@vger.kernel.org, x86@kernel.org, linux-kernel@vger.kernel.org Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <177386607039.1647592.4151788935615459894.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the x86/urgent branch of tip: Commit-ID: 06d45803a3c8d2390027443bbf329bba43f9f3e9 Gitweb: https://git.kernel.org/tip/06d45803a3c8d2390027443bbf329bba4= 3f9f3e9 Author: William Roche AuthorDate: Tue, 17 Mar 2026 10:38:10=20 Committer: Borislav Petkov (AMD) CommitterDate: Wed, 18 Mar 2026 21:25:26 +01:00 x86/mce/amd: Check SMCA feature bit before accessing SMCA MSRs People do effort to inject MCEs into guests in order to simulate/test handling of hardware errors. The real use case behind it is testing the handling of SIGBUS which the memory failure code sends to the process. If that process is QEMU, instead of killing the whole guest, the MCE can be injected into the guest kernel so that latter can attempt proper handling and kill the user *process* in the guest, instead, which caused the MCE. The assumption being here that the whole injection flow can supply enough information that the guest kernel can pinpoint the right process. But that's a different topic... Regardless of virtualization or not, access to SMCA-specific registers like MCA_DESTAT should only be done after having checked the smca feature bit. And there are AMD machines like Bulldozer (the one before Zen1) which do support deferred errors but are not SMCA machines. Therefore, properly check the feature bit before accessing related MSRs. [ bp: Rewrite commit message. ] Fixes: 7cb735d7c0cb ("x86/mce: Unify AMD DFR handler with MCA Polling") Signed-off-by: William Roche Signed-off-by: Borislav Petkov (AMD) Reviewed-by: Yazen Ghannam Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20260218163025.1316501-1-william.roche@orac= le.com --- arch/x86/kernel/cpu/mce/amd.c | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c index da13c1e..a030ee4 100644 --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -875,13 +875,18 @@ void amd_clear_bank(struct mce *m) { amd_reset_thr_limit(m->bank); =20 - /* Clear MCA_DESTAT for all deferred errors even those logged in MCA_STAT= US. */ - if (m->status & MCI_STATUS_DEFERRED) - mce_wrmsrq(MSR_AMD64_SMCA_MCx_DESTAT(m->bank), 0); + if (mce_flags.smca) { + /* + * Clear MCA_DESTAT for all deferred errors even those + * logged in MCA_STATUS. + */ + if (m->status & MCI_STATUS_DEFERRED) + mce_wrmsrq(MSR_AMD64_SMCA_MCx_DESTAT(m->bank), 0); =20 - /* Don't clear MCA_STATUS if MCA_DESTAT was used exclusively. */ - if (m->kflags & MCE_CHECK_DFR_REGS) - return; + /* Don't clear MCA_STATUS if MCA_DESTAT was used exclusively. */ + if (m->kflags & MCE_CHECK_DFR_REGS) + return; + } =20 mce_wrmsrq(mca_msr_reg(m->bank, MCA_STATUS), 0); }