From nobody Mon Apr 6 18:55:15 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7510338654C; Wed, 18 Mar 2026 08:41:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773823315; cv=none; b=FrvTWp6o6FAbVybQ4wFO/YHFmbomtWAm6tXEGPgxXHC4JfI7UtZJ+xoXHJhqFe7zKFTus5kRDpWqS6/BKp02Z4FXl2Xa3jVaaRgtffGlGqxSHUQF+AsAp0ZvaGkajcSDqdGRj/ez5UU1bJCcVNOAJqyHpwmk6DtSNO8R9IzM0Z8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773823315; c=relaxed/simple; bh=eenLEan8nToYBZgPFdqRhwwJCtVNBt/DIOZB9oLR0k4=; h=Date:From:To:Subject:Cc:MIME-Version:Message-ID:Content-Type; b=KT1vCf3tmDOXmiGXeBL2C4WFSr9eg7OrhgDB4JiIS4gCc3y/r1qHxb3q6kf0PJ0Fhm/omyjRKwGk5NmjfLGfvoRNv2vUBDcuheeKQhQRSNPN//vKfIdbIJtPVekJft3jbb3nh02oGxTCyNeKpOOfuui0w7jgScBcTc3SUoI8Keg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=Hy5Bonxp; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=E1hg2i3d; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="Hy5Bonxp"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="E1hg2i3d" Date: Wed, 18 Mar 2026 08:41:49 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1773823310; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=ta+xDmINad9ifBxtJDySmog/mZSc1TJsSLN+6Zmzuhk=; b=Hy5BonxpriVLCnW1mhbAVksEtAkwZE6HNLADQKq2p+Eg1TQ5Zk6SkU//IbbF0bTVCsXHGB VxfDROR8/I7yy/61aVZioPOogxH8hc4+50AyGuTFdIugrpXuRhavP4Ki8Yfgcdr8YryEh+ TQUkgGrTKInCZtGXlgYgqt9MT/lGowQHbhyy21QD6XthTJVnQomG9j0ZRiMaESCCHKxRJG 5XUPYYh9UU15rfHE/KbD39mT9FEBoSX+z/Zj+0/KiNgJuOK0RE8d66E4Wl7fxsd8LaVM5x Cu8Lrw1//HmYtUAPDIaakHyTz9GTL5hbkSy8ZC7ILMm+gTWVyixqiZHOL0ZrkQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1773823310; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=ta+xDmINad9ifBxtJDySmog/mZSc1TJsSLN+6Zmzuhk=; b=E1hg2i3dW3iE/0cmmhA7NsE2XKATgDmVH9J0gAp4Xy+O1njvj5IyNgClShKzG1r+llgqD+ +R4s+8aTnBpmfpCA== From: "tip-bot2 for Josh Poimboeuf" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: objtool/core] objtool/x86: Reorder ORC register numbering Cc: Peter Zijlstra , Josh Poimboeuf , x86@kernel.org, linux-kernel@vger.kernel.org Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <177382330938.1647592.52941916308809114.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the objtool/core branch of tip: Commit-ID: 1735858caa4bbb8b923860c0833d463b5d9c5f79 Gitweb: https://git.kernel.org/tip/1735858caa4bbb8b923860c0833d463b5= d9c5f79 Author: Josh Poimboeuf AuthorDate: Wed, 18 Mar 2026 09:38:38 +01:00 Committer: Peter Zijlstra CommitterDate: Wed, 18 Mar 2026 09:38:52 +01:00 objtool/x86: Reorder ORC register numbering Reorder the ORC register values so their ordering matches the x86 instruction set register encodings. No functional change intended. Suggested-by: Peter Zijlstra Signed-off-by: Josh Poimboeuf Signed-off-by: Peter Zijlstra (Intel) --- arch/x86/include/asm/orc_types.h | 10 +++---- arch/x86/kernel/unwind_orc.c | 30 ++++++++++++--------- tools/arch/x86/include/asm/orc_types.h | 10 +++---- tools/objtool/arch/x86/decode.c | 21 ++++++++------- tools/objtool/arch/x86/orc.c | 36 ++++++++++++------------- 5 files changed, 58 insertions(+), 49 deletions(-) diff --git a/arch/x86/include/asm/orc_types.h b/arch/x86/include/asm/orc_ty= pes.h index b3cc797..5837c2b 100644 --- a/arch/x86/include/asm/orc_types.h +++ b/arch/x86/include/asm/orc_types.h @@ -28,16 +28,16 @@ * and GCC realigned stacks. */ #define ORC_REG_UNDEFINED 0 -#define ORC_REG_PREV_SP 1 +#define ORC_REG_AX 1 #define ORC_REG_DX 2 -#define ORC_REG_DI 3 +#define ORC_REG_SP 3 #define ORC_REG_BP 4 -#define ORC_REG_SP 5 +#define ORC_REG_DI 5 #define ORC_REG_R10 6 #define ORC_REG_R13 7 -#define ORC_REG_BP_INDIRECT 8 +#define ORC_REG_PREV_SP 8 #define ORC_REG_SP_INDIRECT 9 -#define ORC_REG_AX 10 +#define ORC_REG_BP_INDIRECT 10 #define ORC_REG_MAX 15 =20 #define ORC_TYPE_UNDEFINED 0 diff --git a/arch/x86/kernel/unwind_orc.c b/arch/x86/kernel/unwind_orc.c index 32f7e91..6407bc9 100644 --- a/arch/x86/kernel/unwind_orc.c +++ b/arch/x86/kernel/unwind_orc.c @@ -546,17 +546,23 @@ bool unwind_next_frame(struct unwind_state *state) indirect =3D true; break; =20 - case ORC_REG_R10: - if (!get_reg(state, offsetof(struct pt_regs, r10), &sp)) { - orc_warn_current("missing R10 value at %pB\n", + /* + * Any of the below registers may temporarily hold the stack pointer, + * typically during a DRAP stack realignment sequence or some other + * stack swizzle. + */ + + case ORC_REG_AX: + if (!get_reg(state, offsetof(struct pt_regs, ax), &sp)) { + orc_warn_current("missing AX value at %pB\n", (void *)state->ip); goto err; } break; =20 - case ORC_REG_R13: - if (!get_reg(state, offsetof(struct pt_regs, r13), &sp)) { - orc_warn_current("missing R13 value at %pB\n", + case ORC_REG_DX: + if (!get_reg(state, offsetof(struct pt_regs, dx), &sp)) { + orc_warn_current("missing DX value at %pB\n", (void *)state->ip); goto err; } @@ -570,17 +576,17 @@ bool unwind_next_frame(struct unwind_state *state) } break; =20 - case ORC_REG_DX: - if (!get_reg(state, offsetof(struct pt_regs, dx), &sp)) { - orc_warn_current("missing DX value at %pB\n", + case ORC_REG_R10: + if (!get_reg(state, offsetof(struct pt_regs, r10), &sp)) { + orc_warn_current("missing R10 value at %pB\n", (void *)state->ip); goto err; } break; =20 - case ORC_REG_AX: - if (!get_reg(state, offsetof(struct pt_regs, ax), &sp)) { - orc_warn_current("missing AX value at %pB\n", + case ORC_REG_R13: + if (!get_reg(state, offsetof(struct pt_regs, r13), &sp)) { + orc_warn_current("missing R13 value at %pB\n", (void *)state->ip); goto err; } diff --git a/tools/arch/x86/include/asm/orc_types.h b/tools/arch/x86/includ= e/asm/orc_types.h index b3cc797..5837c2b 100644 --- a/tools/arch/x86/include/asm/orc_types.h +++ b/tools/arch/x86/include/asm/orc_types.h @@ -28,16 +28,16 @@ * and GCC realigned stacks. */ #define ORC_REG_UNDEFINED 0 -#define ORC_REG_PREV_SP 1 +#define ORC_REG_AX 1 #define ORC_REG_DX 2 -#define ORC_REG_DI 3 +#define ORC_REG_SP 3 #define ORC_REG_BP 4 -#define ORC_REG_SP 5 +#define ORC_REG_DI 5 #define ORC_REG_R10 6 #define ORC_REG_R13 7 -#define ORC_REG_BP_INDIRECT 8 +#define ORC_REG_PREV_SP 8 #define ORC_REG_SP_INDIRECT 9 -#define ORC_REG_AX 10 +#define ORC_REG_BP_INDIRECT 10 #define ORC_REG_MAX 15 =20 #define ORC_TYPE_UNDEFINED 0 diff --git a/tools/objtool/arch/x86/decode.c b/tools/objtool/arch/x86/decod= e.c index c3a10f3..23e48ea 100644 --- a/tools/objtool/arch/x86/decode.c +++ b/tools/objtool/arch/x86/decode.c @@ -891,14 +891,20 @@ int arch_decode_hint_reg(u8 sp_reg, int *base) case ORC_REG_UNDEFINED: *base =3D CFI_UNDEFINED; break; + case ORC_REG_AX: + *base =3D CFI_AX; + break; + case ORC_REG_DX: + *base =3D CFI_DX; + break; case ORC_REG_SP: *base =3D CFI_SP; break; case ORC_REG_BP: *base =3D CFI_BP; break; - case ORC_REG_SP_INDIRECT: - *base =3D CFI_SP_INDIRECT; + case ORC_REG_DI: + *base =3D CFI_DI; break; case ORC_REG_R10: *base =3D CFI_R10; @@ -906,14 +912,11 @@ int arch_decode_hint_reg(u8 sp_reg, int *base) case ORC_REG_R13: *base =3D CFI_R13; break; - case ORC_REG_DI: - *base =3D CFI_DI; - break; - case ORC_REG_DX: - *base =3D CFI_DX; + case ORC_REG_SP_INDIRECT: + *base =3D CFI_SP_INDIRECT; break; - case ORC_REG_AX: - *base =3D CFI_AX; + case ORC_REG_BP_INDIRECT: + *base =3D CFI_BP_INDIRECT; break; default: return -1; diff --git a/tools/objtool/arch/x86/orc.c b/tools/objtool/arch/x86/orc.c index 5494bb4..eff078e 100644 --- a/tools/objtool/arch/x86/orc.c +++ b/tools/objtool/arch/x86/orc.c @@ -46,17 +46,20 @@ int init_orc_entry(struct orc_entry *orc, struct cfi_st= ate *cfi, struct instruct orc->signal =3D cfi->signal; =20 switch (cfi->cfa.base) { + case CFI_AX: + orc->sp_reg =3D ORC_REG_AX; + break; + case CFI_DX: + orc->sp_reg =3D ORC_REG_DX; + break; case CFI_SP: orc->sp_reg =3D ORC_REG_SP; break; - case CFI_SP_INDIRECT: - orc->sp_reg =3D ORC_REG_SP_INDIRECT; - break; case CFI_BP: orc->sp_reg =3D ORC_REG_BP; break; - case CFI_BP_INDIRECT: - orc->sp_reg =3D ORC_REG_BP_INDIRECT; + case CFI_DI: + orc->sp_reg =3D ORC_REG_DI; break; case CFI_R10: orc->sp_reg =3D ORC_REG_R10; @@ -64,14 +67,11 @@ int init_orc_entry(struct orc_entry *orc, struct cfi_st= ate *cfi, struct instruct case CFI_R13: orc->sp_reg =3D ORC_REG_R13; break; - case CFI_DI: - orc->sp_reg =3D ORC_REG_DI; - break; - case CFI_DX: - orc->sp_reg =3D ORC_REG_DX; + case CFI_SP_INDIRECT: + orc->sp_reg =3D ORC_REG_SP_INDIRECT; break; - case CFI_AX: - orc->sp_reg =3D ORC_REG_AX; + case CFI_BP_INDIRECT: + orc->sp_reg =3D ORC_REG_BP_INDIRECT; break; default: ERROR_INSN(insn, "unknown CFA base reg %d", cfi->cfa.base); @@ -125,24 +125,24 @@ static const char *reg_name(unsigned int reg) switch (reg) { case ORC_REG_PREV_SP: return "prevsp"; + case ORC_REG_AX: + return "ax"; case ORC_REG_DX: return "dx"; - case ORC_REG_DI: - return "di"; case ORC_REG_BP: return "bp"; case ORC_REG_SP: return "sp"; + case ORC_REG_DI: + return "di"; case ORC_REG_R10: return "r10"; case ORC_REG_R13: return "r13"; - case ORC_REG_BP_INDIRECT: - return "bp(ind)"; case ORC_REG_SP_INDIRECT: return "sp(ind)"; - case ORC_REG_AX: - return "ax"; + case ORC_REG_BP_INDIRECT: + return "bp(ind)"; default: return "?"; }