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Mon, 16 Mar 2026 05:57:57 -0700 (PDT) Received: from DC6WP-EXCH02.marvell.com (10.76.176.209) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.25; Mon, 16 Mar 2026 05:57:56 -0700 Received: from maili.marvell.com (10.69.176.80) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server id 15.2.1544.25 via Frontend Transport; Mon, 16 Mar 2026 05:57:56 -0700 Received: from hyd1358.marvell.com (unknown [10.29.37.11]) by maili.marvell.com (Postfix) with ESMTP id AAFFF3F7061; Mon, 16 Mar 2026 05:57:52 -0700 (PDT) From: Subbaraya Sundeep To: , , , , , , , CC: , , Linu Cherian , Subbaraya Sundeep Subject: [net-next PATCH 1/4] octeontx2-af: npa: cn20k: Add NPA Halo support Date: Mon, 16 Mar 2026 18:27:36 +0530 Message-ID: <1773665859-4036-2-git-send-email-sbhatta@marvell.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1773665859-4036-1-git-send-email-sbhatta@marvell.com> References: <1773665859-4036-1-git-send-email-sbhatta@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzE2MDA5NyBTYWx0ZWRfXy6uTGs7EuC6I Ke6Wcyy9oxdl1Q6O++OWJOiXgwqVbVaR/to+5DSu6lKbn3u+EscZsYqWIgRqGnQBtfTdGhXgmLe 7qY8w0LVqsGPnptWS/VjvgnPPLOnHHsK2A6JZ6b5r1ntZuFxUMfAVchfcf/3nVcEFUExUbN6HDR NSACDGsIocJGAWyNFJDxWZmUpXFB1aUDFS2u3haz7pX+vyGt0FWf6uS7H2G0b+ghqYC252ySSfg 6R/q6fLlyd1elYVrrhlv68HkiTBTrHBeiIwRBUW9obp6JgpSkB4leXJGAwWBvU5onzQmXSmxGS6 TyLRjP6IQujoS84Clq2icXvlN4zvUTXyi52t/sqbqFrVwX7SipGoY1Wc6OtuNEi32kvd35i4+8J NRXcNBuv2jft71+rcRziTRqZZ3kFHg0T1Z1mYBDuL7hzllN17spGdnN55JWRBDsAKAUsdTyerDo /o8nKeKAOHGm+iYWM6Q== X-Proofpoint-GUID: NzdHb6_9XCazF0063_DeZpXX-eEleEPK X-Authority-Analysis: v=2.4 cv=cpuWUl4i c=1 sm=1 tr=0 ts=69b7fe55 cx=c_pps a=gIfcoYsirJbf48DBMSPrZA==:117 a=gIfcoYsirJbf48DBMSPrZA==:17 a=Yq5XynenixoA:10 a=VkNPw1HP01LnGYTKEx00:22 a=l0iWHRpgs5sLHlkKQ1IR:22 a=EAYMVhzMl8SCOHhVQcBL:22 a=M5GUcnROAAAA:8 a=Y-g3w6YZR3aQ1dYOMfkA:9 a=OBjm3rFKGHvpk9ecZwUJ:22 X-Proofpoint-ORIG-GUID: NzdHb6_9XCazF0063_DeZpXX-eEleEPK X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-16_04,2026-03-16_03,2025-10-01_01 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Linu Cherian CN20K silicon implements unified aura and pool context type called Halo for better resource usage. Add support to handle Halo context type operations. Signed-off-by: Linu Cherian Signed-off-by: Subbaraya Sundeep --- .../ethernet/marvell/octeontx2/af/cn20k/npa.c | 27 +++++++ .../marvell/octeontx2/af/cn20k/struct.h | 81 +++++++++++++++++++ .../net/ethernet/marvell/octeontx2/af/mbox.h | 6 ++ .../net/ethernet/marvell/octeontx2/af/rvu.h | 2 + .../ethernet/marvell/octeontx2/af/rvu_npa.c | 56 +++++++++++-- .../marvell/octeontx2/af/rvu_struct.h | 1 + 6 files changed, 168 insertions(+), 5 deletions(-) diff --git a/drivers/net/ethernet/marvell/octeontx2/af/cn20k/npa.c b/driver= s/net/ethernet/marvell/octeontx2/af/cn20k/npa.c index fe8f926c8b75..c963f43dc7b0 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/cn20k/npa.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/cn20k/npa.c @@ -19,3 +19,30 @@ int rvu_mbox_handler_npa_cn20k_aq_enq(struct rvu *rvu, (struct npa_aq_enq_rsp *)rsp); } EXPORT_SYMBOL(rvu_mbox_handler_npa_cn20k_aq_enq); + +int rvu_npa_halo_hwctx_disable(struct npa_aq_enq_req *req) +{ + struct npa_cn20k_aq_enq_req *hreq; + + hreq =3D (struct npa_cn20k_aq_enq_req *)req; + + hreq->halo.bp_ena_0 =3D 0; + hreq->halo.bp_ena_1 =3D 0; + hreq->halo.bp_ena_2 =3D 0; + hreq->halo.bp_ena_3 =3D 0; + hreq->halo.bp_ena_4 =3D 0; + hreq->halo.bp_ena_5 =3D 0; + hreq->halo.bp_ena_6 =3D 0; + hreq->halo.bp_ena_7 =3D 0; + + hreq->halo_mask.bp_ena_0 =3D 1; + hreq->halo_mask.bp_ena_1 =3D 1; + hreq->halo_mask.bp_ena_2 =3D 1; + hreq->halo_mask.bp_ena_3 =3D 1; + hreq->halo_mask.bp_ena_4 =3D 1; + hreq->halo_mask.bp_ena_5 =3D 1; + hreq->halo_mask.bp_ena_6 =3D 1; + hreq->halo_mask.bp_ena_7 =3D 1; + + return 0; +} diff --git a/drivers/net/ethernet/marvell/octeontx2/af/cn20k/struct.h b/dri= vers/net/ethernet/marvell/octeontx2/af/cn20k/struct.h index 763f6cabd7c2..2364bafd329d 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/cn20k/struct.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/cn20k/struct.h @@ -377,4 +377,85 @@ struct npa_cn20k_pool_s { =20 static_assert(sizeof(struct npa_cn20k_pool_s) =3D=3D NIX_MAX_CTX_SIZE); =20 +struct npa_cn20k_halo_s { + u64 stack_base : 64; + u64 ena : 1; + u64 nat_align : 1; + u64 reserved_66_67 : 2; + u64 stack_caching : 1; + u64 reserved_69_71 : 3; + u64 aura_drop_ena : 1; + u64 reserved_73_79 : 7; + u64 aura_drop : 8; + u64 buf_offset : 12; + u64 reserved_100_103 : 4; + u64 buf_size : 12; + u64 reserved_116_119 : 4; + u64 ref_cnt_prof : 3; + u64 reserved_123_127 : 5; + u64 stack_max_pages : 32; + u64 stack_pages : 32; + u64 bp_0 : 7; + u64 bp_1 : 7; + u64 bp_2 : 7; + u64 bp_3 : 7; + u64 bp_4 : 7; + u64 bp_5 : 7; + u64 bp_6 : 7; + u64 bp_7 : 7; + u64 bp_ena_0 : 1; + u64 bp_ena_1 : 1; + u64 bp_ena_2 : 1; + u64 bp_ena_3 : 1; + u64 bp_ena_4 : 1; + u64 bp_ena_5 : 1; + u64 bp_ena_6 : 1; + u64 bp_ena_7 : 1; + u64 stack_offset : 4; + u64 reserved_260_263 : 4; + u64 shift : 6; + u64 reserved_270_271 : 2; + u64 avg_level : 8; + u64 avg_con : 9; + u64 fc_ena : 1; + u64 fc_stype : 2; + u64 fc_hyst_bits : 4; + u64 fc_up_crossing : 1; + u64 reserved_297_299 : 3; + u64 update_time : 16; + u64 reserved_316_319 : 4; + u64 fc_addr : 64; + u64 ptr_start : 64; + u64 ptr_end : 64; + u64 bpid_0 : 12; + u64 reserved_524_535 : 12; + u64 err_int : 8; + u64 err_int_ena : 8; + u64 thresh_int : 1; + u64 thresh_int_ena : 1; + u64 thresh_up : 1; + u64 reserved_555 : 1; + u64 thresh_qint_idx : 7; + u64 reserved_563 : 1; + u64 err_qint_idx : 7; + u64 reserved_571_575 : 5; + u64 thresh : 36; + u64 reserved_612_615 : 4; + u64 fc_msh_dst : 11; + u64 reserved_627_630 : 4; + u64 op_dpc_ena : 1; + u64 op_dpc_set : 5; + u64 reserved_637_637 : 1; + u64 stream_ctx : 1; + u64 unified_ctx : 1; + u64 reserved_640_703 : 64; + u64 reserved_704_767 : 64; + u64 reserved_768_831 : 64; + u64 reserved_832_895 : 64; + u64 reserved_896_959 : 64; + u64 reserved_960_1023 : 64; +}; + +static_assert(sizeof(struct npa_cn20k_halo_s) =3D=3D NIX_MAX_CTX_SIZE); + #endif diff --git a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h b/drivers/net= /ethernet/marvell/octeontx2/af/mbox.h index dc42c81c0942..4a97bd93d882 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h @@ -884,6 +884,8 @@ struct npa_cn20k_aq_enq_req { struct npa_cn20k_aura_s aura; /* Valid when op =3D=3D WRITE/INIT and ctype =3D=3D POOL */ struct npa_cn20k_pool_s pool; + /* Valid when op =3D=3D WRITE/INIT and ctype =3D=3D HALO */ + struct npa_cn20k_halo_s halo; }; /* Mask data when op =3D=3D WRITE (1=3Dwrite, 0=3Ddon't write) */ union { @@ -891,6 +893,8 @@ struct npa_cn20k_aq_enq_req { struct npa_cn20k_aura_s aura_mask; /* Valid when op =3D=3D WRITE and ctype =3D=3D POOL */ struct npa_cn20k_pool_s pool_mask; + /* Valid when op =3D=3D WRITE/INIT and ctype =3D=3D HALO */ + struct npa_cn20k_halo_s halo_mask; }; }; =20 @@ -901,6 +905,8 @@ struct npa_cn20k_aq_enq_rsp { struct npa_cn20k_aura_s aura; /* Valid when op =3D=3D READ and ctype =3D=3D POOL */ struct npa_cn20k_pool_s pool; + /* Valid when op =3D=3D READ and ctype =3D=3D HALO */ + struct npa_cn20k_halo_s halo; }; }; =20 diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h b/drivers/net/= ethernet/marvell/octeontx2/af/rvu.h index a466181cf908..1ffb338401ac 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu.h @@ -261,6 +261,7 @@ struct rvu_pfvf { struct qmem *pool_ctx; struct qmem *npa_qints_ctx; unsigned long *aura_bmap; + unsigned long *halo_bmap; /* Aura and Halo bmap are mutually exclusive */ unsigned long *pool_bmap; =20 /* NIX contexts */ @@ -1008,6 +1009,7 @@ void rvu_npa_freemem(struct rvu *rvu); void rvu_npa_lf_teardown(struct rvu *rvu, u16 pcifunc, int npalf); int rvu_npa_aq_enq_inst(struct rvu *rvu, struct npa_aq_enq_req *req, struct npa_aq_enq_rsp *rsp); +int rvu_npa_halo_hwctx_disable(struct npa_aq_enq_req *req); =20 /* NIX APIs */ bool is_nixlf_attached(struct rvu *rvu, u16 pcifunc); diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c b/drivers/= net/ethernet/marvell/octeontx2/af/rvu_npa.c index e2a33e46b48a..aa2b8acf6be4 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c @@ -12,6 +12,11 @@ #include "rvu_reg.h" #include "rvu.h" =20 +static inline bool npa_ctype_invalid(struct rvu *rvu, int ctype) +{ + return !is_cn20k(rvu->pdev) && ctype =3D=3D NPA_AQ_CTYPE_HALO; +} + static int npa_aq_enqueue_wait(struct rvu *rvu, struct rvu_block *block, struct npa_aq_inst_s *inst) { @@ -72,13 +77,19 @@ int rvu_npa_aq_enq_inst(struct rvu *rvu, struct npa_aq_= enq_req *req, bool ena; =20 pfvf =3D rvu_get_pfvf(rvu, pcifunc); - if (!pfvf->aura_ctx || req->aura_id >=3D pfvf->aura_ctx->qsize) + if (!pfvf->aura_ctx || req->aura_id >=3D pfvf->aura_ctx->qsize || + npa_ctype_invalid(rvu, req->ctype)) return NPA_AF_ERR_AQ_ENQUEUE; =20 blkaddr =3D rvu_get_blkaddr(rvu, BLKTYPE_NPA, pcifunc); if (!pfvf->npalf || blkaddr < 0) return NPA_AF_ERR_AF_LF_INVALID; =20 + /* Ensure halo bitmap is exclusive to halo ctype */ + if (is_cn20k(rvu->pdev) && req->ctype !=3D NPA_AQ_CTYPE_HALO && + test_bit(req->aura_id, pfvf->halo_bmap)) + return NPA_AF_ERR_AQ_ENQUEUE; + block =3D &hw->block[blkaddr]; aq =3D block->aq; if (!aq) { @@ -119,7 +130,7 @@ int rvu_npa_aq_enq_inst(struct rvu *rvu, struct npa_aq_= enq_req *req, memcpy(mask, &req->aura_mask, sizeof(struct npa_aura_s)); memcpy(ctx, &req->aura, sizeof(struct npa_aura_s)); - } else { + } else { /* Applies to both pool and halo as the size is compatible */ memcpy(mask, &req->pool_mask, sizeof(struct npa_pool_s)); memcpy(ctx, &req->pool, sizeof(struct npa_pool_s)); @@ -135,7 +146,7 @@ int rvu_npa_aq_enq_inst(struct rvu *rvu, struct npa_aq_= enq_req *req, req->aura.pool_addr =3D pfvf->pool_ctx->iova + (req->aura.pool_addr * pfvf->pool_ctx->entry_sz); memcpy(ctx, &req->aura, sizeof(struct npa_aura_s)); - } else { /* POOL's context */ + } else { /* Applies to both pool and halo as the size is compatible */ memcpy(ctx, &req->pool, sizeof(struct npa_pool_s)); } break; @@ -176,6 +187,20 @@ int rvu_npa_aq_enq_inst(struct rvu *rvu, struct npa_aq= _enq_req *req, } } =20 + if (req->ctype =3D=3D NPA_AQ_CTYPE_HALO) { + if (req->op =3D=3D NPA_AQ_INSTOP_INIT && req->aura.ena) + __set_bit(req->aura_id, pfvf->halo_bmap); + if (req->op =3D=3D NPA_AQ_INSTOP_WRITE) { + ena =3D (req->aura.ena & req->aura_mask.ena) | + (test_bit(req->aura_id, pfvf->halo_bmap) & + ~req->aura_mask.ena); + if (ena) + __set_bit(req->aura_id, pfvf->halo_bmap); + else + __clear_bit(req->aura_id, pfvf->halo_bmap); + } + } + /* Set pool bitmap if pool hw context is enabled */ if (req->ctype =3D=3D NPA_AQ_CTYPE_POOL) { if (req->op =3D=3D NPA_AQ_INSTOP_INIT && req->pool.ena) @@ -198,7 +223,7 @@ int rvu_npa_aq_enq_inst(struct rvu *rvu, struct npa_aq_= enq_req *req, if (req->ctype =3D=3D NPA_AQ_CTYPE_AURA) memcpy(&rsp->aura, ctx, sizeof(struct npa_aura_s)); - else + else /* Applies to both pool and halo as the size is compatible */ memcpy(&rsp->pool, ctx, sizeof(struct npa_pool_s)); } @@ -215,7 +240,8 @@ static int npa_lf_hwctx_disable(struct rvu *rvu, struct= hwctx_disable_req *req) int id, cnt =3D 0; int err =3D 0, rc; =20 - if (!pfvf->pool_ctx || !pfvf->aura_ctx) + if (!pfvf->pool_ctx || !pfvf->aura_ctx || + npa_ctype_invalid(rvu, req->ctype)) return NPA_AF_ERR_AQ_ENQUEUE; =20 memset(&aq_req, 0, sizeof(struct npa_aq_enq_req)); @@ -233,6 +259,12 @@ static int npa_lf_hwctx_disable(struct rvu *rvu, struc= t hwctx_disable_req *req) aq_req.aura_mask.bp_ena =3D 1; cnt =3D pfvf->aura_ctx->qsize; bmap =3D pfvf->aura_bmap; + } else if (req->ctype =3D=3D NPA_AQ_CTYPE_HALO) { + aq_req.aura.ena =3D 0; + aq_req.aura_mask.ena =3D 1; + rvu_npa_halo_hwctx_disable(&aq_req); + cnt =3D pfvf->aura_ctx->qsize; + bmap =3D pfvf->halo_bmap; } =20 aq_req.ctype =3D req->ctype; @@ -311,6 +343,9 @@ static void npa_ctx_free(struct rvu *rvu, struct rvu_pf= vf *pfvf) kfree(pfvf->aura_bmap); pfvf->aura_bmap =3D NULL; =20 + kfree(pfvf->halo_bmap); + pfvf->halo_bmap =3D NULL; + qmem_free(rvu->dev, pfvf->aura_ctx); pfvf->aura_ctx =3D NULL; =20 @@ -374,6 +409,13 @@ int rvu_mbox_handler_npa_lf_alloc(struct rvu *rvu, if (!pfvf->aura_bmap) goto free_mem; =20 + if (is_cn20k(rvu->pdev)) { + pfvf->halo_bmap =3D kcalloc(NPA_AURA_COUNT(req->aura_sz), sizeof(long), + GFP_KERNEL); + if (!pfvf->halo_bmap) + goto free_mem; + } + /* Alloc memory for pool HW contexts */ hwctx_size =3D 1UL << ((ctx_cfg >> 4) & 0xF); err =3D qmem_alloc(rvu->dev, &pfvf->pool_ctx, req->nr_pools, hwctx_size); @@ -562,6 +604,10 @@ void rvu_npa_lf_teardown(struct rvu *rvu, u16 pcifunc,= int npalf) ctx_req.ctype =3D NPA_AQ_CTYPE_AURA; npa_lf_hwctx_disable(rvu, &ctx_req); =20 + /* Disable all Halos */ + ctx_req.ctype =3D NPA_AQ_CTYPE_HALO; + npa_lf_hwctx_disable(rvu, &ctx_req); + npa_ctx_free(rvu, pfvf); } =20 diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_struct.h b/drive= rs/net/ethernet/marvell/octeontx2/af/rvu_struct.h index 8e868f815de1..d37cf2cf0fee 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_struct.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_struct.h @@ -130,6 +130,7 @@ enum npa_aq_comp { enum npa_aq_ctype { NPA_AQ_CTYPE_AURA =3D 0x0, NPA_AQ_CTYPE_POOL =3D 0x1, + NPA_AQ_CTYPE_HALO =3D 0x2, }; =20 /* NPA admin queue instruction opcodes */ --=20 2.48.1 From nobody Tue Apr 7 04:18:29 2026 Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8AEB83976AA; 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charset="utf-8" From: Linu Cherian CN20k introduces 32 diagnostic and performance counters that are shared across all NPA LFs. Counters being shared, each PF driver need to request for a counter with the required configuration to the AF, so that a counter can be allocated and mapped to the respective LF with the requested configuration. Add new mbox messages, npa_dpc_alloc/free to handle this. Also ensure all the LF to DPC counter mappings are cleared at the time of LF free/teardown. Signed-off-by: Linu Cherian Signed-off-by: Subbaraya Sundeep --- .../ethernet/marvell/octeontx2/af/cn20k/api.h | 6 + .../ethernet/marvell/octeontx2/af/cn20k/npa.c | 113 ++++++++++++++++++ .../ethernet/marvell/octeontx2/af/cn20k/reg.h | 7 ++ .../net/ethernet/marvell/octeontx2/af/mbox.h | 19 +++ .../net/ethernet/marvell/octeontx2/af/rvu.h | 3 + .../ethernet/marvell/octeontx2/af/rvu_npa.c | 14 ++- 6 files changed, 161 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/marvell/octeontx2/af/cn20k/api.h b/driver= s/net/ethernet/marvell/octeontx2/af/cn20k/api.h index 4285b5d6a6a2..b13e7628f767 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/cn20k/api.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/cn20k/api.h @@ -29,4 +29,10 @@ int cn20k_mbox_setup(struct otx2_mbox *mbox, struct pci_= dev *pdev, void *reg_base, int direction, int ndevs); void cn20k_rvu_enable_afvf_intr(struct rvu *rvu, int vfs); void cn20k_rvu_disable_afvf_intr(struct rvu *rvu, int vfs); + +int npa_cn20k_dpc_alloc(struct rvu *rvu, struct npa_cn20k_dpc_alloc_req *r= eq, + struct npa_cn20k_dpc_alloc_rsp *rsp); +int npa_cn20k_dpc_free(struct rvu *rvu, struct npa_cn20k_dpc_free_req *req= ); +void npa_cn20k_dpc_free_all(struct rvu *rvu, u16 pcifunc); + #endif /* CN20K_API_H */ diff --git a/drivers/net/ethernet/marvell/octeontx2/af/cn20k/npa.c b/driver= s/net/ethernet/marvell/octeontx2/af/cn20k/npa.c index c963f43dc7b0..325c4f013d29 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/cn20k/npa.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/cn20k/npa.c @@ -8,6 +8,8 @@ #include #include =20 +#include "cn20k/api.h" +#include "cn20k/reg.h" #include "struct.h" #include "../rvu.h" =20 @@ -46,3 +48,114 @@ int rvu_npa_halo_hwctx_disable(struct npa_aq_enq_req *r= eq) =20 return 0; } + +int npa_cn20k_dpc_alloc(struct rvu *rvu, struct npa_cn20k_dpc_alloc_req *r= eq, + struct npa_cn20k_dpc_alloc_rsp *rsp) +{ + struct rvu_hwinfo *hw =3D rvu->hw; + u16 pcifunc =3D req->hdr.pcifunc; + int cntr, lf, blkaddr, ridx; + struct rvu_block *block; + struct rvu_pfvf *pfvf; + u64 val, lfmask; + + pfvf =3D rvu_get_pfvf(rvu, pcifunc); + + blkaddr =3D rvu_get_blkaddr(rvu, BLKTYPE_NPA, 0); + if (!pfvf->npalf || blkaddr < 0) + return NPA_AF_ERR_AF_LF_INVALID; + + block =3D &hw->block[blkaddr]; + lf =3D rvu_get_lf(rvu, block, pcifunc, 0); + if (lf < 0) + return NPA_AF_ERR_AF_LF_INVALID; + + /* allocate a new counter */ + cntr =3D rvu_alloc_rsrc(&rvu->npa_dpc); + if (cntr < 0) + return cntr; + rsp->cntr_id =3D cntr; + + /* DPC counter config */ + rvu_write64(rvu, blkaddr, NPA_AF_DPCX_CFG(cntr), req->dpc_conf); + + /* 0 to 63 lfs -> idx 0, 64 - 127 lfs -> idx 1 */ + ridx =3D lf >> 6; + lfmask =3D BIT_ULL(ridx ? lf - NPA_DPC_LFS_PER_REG : lf); + + ridx =3D 2 * cntr + ridx; + /* Give permission for LF access */ + val =3D rvu_read64(rvu, blkaddr, NPA_AF_DPC_PERMITX(ridx)); + val |=3D lfmask; + rvu_write64(rvu, blkaddr, NPA_AF_DPC_PERMITX(ridx), val); + + return 0; +} + +int rvu_mbox_handler_npa_cn20k_dpc_alloc(struct rvu *rvu, + struct npa_cn20k_dpc_alloc_req *req, + struct npa_cn20k_dpc_alloc_rsp *rsp) +{ + return npa_cn20k_dpc_alloc(rvu, req, rsp); +} + +int npa_cn20k_dpc_free(struct rvu *rvu, struct npa_cn20k_dpc_free_req *req) +{ + struct rvu_hwinfo *hw =3D rvu->hw; + u16 pcifunc =3D req->hdr.pcifunc; + int cntr, lf, blkaddr, ridx; + struct rvu_block *block; + struct rvu_pfvf *pfvf; + u64 val, lfmask; + + pfvf =3D rvu_get_pfvf(rvu, pcifunc); + + blkaddr =3D rvu_get_blkaddr(rvu, BLKTYPE_NPA, 0); + if (!pfvf->npalf || blkaddr < 0) + return NPA_AF_ERR_AF_LF_INVALID; + + block =3D &hw->block[blkaddr]; + lf =3D rvu_get_lf(rvu, block, pcifunc, 0); + if (lf < 0) + return NPA_AF_ERR_AF_LF_INVALID; + + /* 0 to 63 lfs -> idx 0, 64 - 127 lfs -> idx 1 */ + ridx =3D lf >> 6; + lfmask =3D BIT_ULL(ridx ? lf - NPA_DPC_LFS_PER_REG : lf); + cntr =3D req->cntr_id; + + ridx =3D 2 * cntr + ridx; + + val =3D rvu_read64(rvu, blkaddr, NPA_AF_DPC_PERMITX(ridx)); + /* Check if the counter is allotted to this LF */ + if (!(val & lfmask)) + return 0; + + /* Revert permission */ + val &=3D ~lfmask; + rvu_write64(rvu, blkaddr, NPA_AF_DPC_PERMITX(ridx), val); + + /* Free this counter */ + rvu_free_rsrc(&rvu->npa_dpc, req->cntr_id); + + return 0; +} + +void npa_cn20k_dpc_free_all(struct rvu *rvu, u16 pcifunc) +{ + struct npa_cn20k_dpc_free_req req; + int i; + + req.hdr.pcifunc =3D pcifunc; + for (i =3D 0; i < NPA_DPC_MAX; i++) { + req.cntr_id =3D i; + npa_cn20k_dpc_free(rvu, &req); + } +} + +int rvu_mbox_handler_npa_cn20k_dpc_free(struct rvu *rvu, + struct npa_cn20k_dpc_free_req *req, + struct msg_rsp *rsp) +{ + return npa_cn20k_dpc_free(rvu, req); +} diff --git a/drivers/net/ethernet/marvell/octeontx2/af/cn20k/reg.h b/driver= s/net/ethernet/marvell/octeontx2/af/cn20k/reg.h index 8bfaa507ee50..9b49e376878e 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/cn20k/reg.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/cn20k/reg.h @@ -143,4 +143,11 @@ offset =3D (0xb000000ull | (a) << 4 | (b) << 20); \ offset; }) =20 +/* NPA Registers */ +#define NPA_AF_DPCX_CFG(a) (0x800 | (a) << 6) +#define NPA_AF_DPC_PERMITX(a) (0x1000 | (a) << 3) + +#define NPA_DPC_MAX 32 +#define NPA_DPC_LFS_PER_REG 64 + #endif /* RVU_MBOX_REG_H */ diff --git a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h b/drivers/net= /ethernet/marvell/octeontx2/af/mbox.h index 4a97bd93d882..b29ec26b66b7 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h @@ -213,6 +213,10 @@ M(NPA_AQ_ENQ, 0x402, npa_aq_enq, npa_aq_enq_req, npa_= aq_enq_rsp) \ M(NPA_HWCTX_DISABLE, 0x403, npa_hwctx_disable, hwctx_disable_req, msg_rsp)\ M(NPA_CN20K_AQ_ENQ, 0x404, npa_cn20k_aq_enq, npa_cn20k_aq_enq_req, \ npa_cn20k_aq_enq_rsp) \ +M(NPA_CN20K_DPC_ALLOC, 0x405, npa_cn20k_dpc_alloc, npa_cn20k_dpc_alloc_req= , \ + npa_cn20k_dpc_alloc_rsp) \ +M(NPA_CN20K_DPC_FREE, 0x406, npa_cn20k_dpc_free, npa_cn20k_dpc_free_req, \ + msg_rsp) \ /* SSO/SSOW mbox IDs (range 0x600 - 0x7FF) */ \ /* TIM mbox IDs (range 0x800 - 0x9FF) */ \ /* CPT mbox IDs (range 0xA00 - 0xBFF) */ \ @@ -910,6 +914,21 @@ struct npa_cn20k_aq_enq_rsp { }; }; =20 +struct npa_cn20k_dpc_alloc_req { + struct mbox_msghdr hdr; + u16 dpc_conf; +}; + +struct npa_cn20k_dpc_alloc_rsp { + struct mbox_msghdr hdr; + u8 cntr_id; +}; + +struct npa_cn20k_dpc_free_req { + struct mbox_msghdr hdr; + u8 cntr_id; +}; + /* Disable all contexts of type 'ctype' */ struct hwctx_disable_req { struct mbox_msghdr hdr; diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h b/drivers/net/= ethernet/marvell/octeontx2/af/rvu.h index 1ffb338401ac..f875bfce1edf 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu.h @@ -663,6 +663,9 @@ struct rvu { /* CPT interrupt lock */ spinlock_t cpt_intr_lock; =20 + /* NPA */ + struct rsrc_bmap npa_dpc; + struct mutex mbox_lock; /* Serialize mbox up and down msgs */ u16 rep_pcifunc; bool altaf_ready; diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c b/drivers/= net/ethernet/marvell/octeontx2/af/rvu_npa.c index aa2b8acf6be4..dd1b77e24751 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c @@ -8,6 +8,8 @@ #include #include =20 +#include "cn20k/api.h" +#include "cn20k/reg.h" #include "rvu_struct.h" #include "rvu_reg.h" #include "rvu.h" @@ -501,6 +503,8 @@ int rvu_mbox_handler_npa_lf_free(struct rvu *rvu, struc= t msg_req *req, return NPA_AF_ERR_LF_RESET; } =20 + if (is_cn20k(rvu->pdev)) + npa_cn20k_dpc_free_all(rvu, pcifunc); npa_ctx_free(rvu, pfvf); =20 return 0; @@ -566,12 +570,17 @@ static int npa_aq_init(struct rvu *rvu, struct rvu_bl= ock *block) int rvu_npa_init(struct rvu *rvu) { struct rvu_hwinfo *hw =3D rvu->hw; - int blkaddr; + int err, blkaddr; =20 blkaddr =3D rvu_get_blkaddr(rvu, BLKTYPE_NPA, 0); if (blkaddr < 0) return 0; =20 + rvu->npa_dpc.max =3D NPA_DPC_MAX; + err =3D rvu_alloc_bitmap(&rvu->npa_dpc); + if (err) + return err; + /* Initialize admin queue */ return npa_aq_init(rvu, &hw->block[blkaddr]); } @@ -588,6 +597,7 @@ void rvu_npa_freemem(struct rvu *rvu) =20 block =3D &hw->block[blkaddr]; rvu_aq_free(rvu, block->aq); + kfree(rvu->npa_dpc.bmap); } =20 void rvu_npa_lf_teardown(struct rvu *rvu, u16 pcifunc, int npalf) @@ -608,6 +618,8 @@ void rvu_npa_lf_teardown(struct rvu *rvu, u16 pcifunc, = int npalf) ctx_req.ctype =3D NPA_AQ_CTYPE_HALO; npa_lf_hwctx_disable(rvu, &ctx_req); =20 + if (is_cn20k(rvu->pdev)) + npa_cn20k_dpc_free_all(rvu, pcifunc); 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Mon, 16 Mar 2026 05:58:05 -0700 (PDT) Received: from DC6WP-EXCH02.marvell.com (10.76.176.209) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.25; Mon, 16 Mar 2026 05:58:03 -0700 Received: from maili.marvell.com (10.69.176.80) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server id 15.2.1544.25 via Frontend Transport; Mon, 16 Mar 2026 05:58:03 -0700 Received: from hyd1358.marvell.com (unknown [10.29.37.11]) by maili.marvell.com (Postfix) with ESMTP id 46B593F7061; Mon, 16 Mar 2026 05:58:00 -0700 (PDT) From: Subbaraya Sundeep To: , , , , , , , CC: , , Linu Cherian , Subbaraya Sundeep Subject: [net-next PATCH 3/4] octeontx2-af: npa: cn20k: Add debugfs for Halo Date: Mon, 16 Mar 2026 18:27:38 +0530 Message-ID: <1773665859-4036-4-git-send-email-sbhatta@marvell.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1773665859-4036-1-git-send-email-sbhatta@marvell.com> References: <1773665859-4036-1-git-send-email-sbhatta@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzE2MDA5NyBTYWx0ZWRfXzPjx5pqCQj/Z QkWh6F8bSWFyM6e54buvy0c9WXT1wsbRa119ebdBoae5FV7VItwxNxrOD5rT6qyaZkazR8w8569 DhJnOLjT9zGOU+se0msqgXSVi9mS2/LJc4k0b+Gx+s9Z8cZk/VjdsP7mS2Fh3RuJdjP5WvEZxsf zlCdhpO1zn91fxu6cUeWtGj7K0Uj825rJh5mTa9Rj1D/jTqVuzvlS8vjCmnLo3jmAhPeFxBDE5T n+xBvousJ8F3UEopL/VIrKQjhoONHmvDiX42jnOOONdlAk5VtKr2w/KD9Pyow84zodWz4SD2EvY hxjEUmAvR1OSHQB8zL5j/75t9gawTHSSoHUjoNaKTo4/4EesLPnDnVExyUxkR/d6AS0ACUChi+i 1pEicE7jaAVRCMXpmq52JitMOlggWdy67QbPvAU2IIjMUx2rhuqcPVe49xq419H3x6IZKpFc8ty 41ZmY5A1l1X9tDSJLEA== X-Proofpoint-GUID: HJ6CtXOvGVWtJAVk8j9OI8dytl5epGXA X-Authority-Analysis: v=2.4 cv=KNtXzVFo c=1 sm=1 tr=0 ts=69b7fe5d cx=c_pps a=gIfcoYsirJbf48DBMSPrZA==:117 a=gIfcoYsirJbf48DBMSPrZA==:17 a=Yq5XynenixoA:10 a=VkNPw1HP01LnGYTKEx00:22 a=l0iWHRpgs5sLHlkKQ1IR:22 a=TtqV-g6YmW1Jfm2GSLaY:22 a=M5GUcnROAAAA:8 a=xE7MTFBHVDZtU5icdfMA:9 a=OBjm3rFKGHvpk9ecZwUJ:22 X-Proofpoint-ORIG-GUID: HJ6CtXOvGVWtJAVk8j9OI8dytl5epGXA X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-16_04,2026-03-16_03,2025-10-01_01 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Linu Cherian Similar to other hardware contexts add debugfs support for unified Halo context. Sample output on cn20k:: /sys/kernel/debug/cn20k/npa # cat halo_ctx =3D=3D=3D=3D=3D=3Dhalo : 2=3D=3D=3D=3D=3D=3D=3D W0: Stack base ffffff790000 W1: ena 1 W1: nat_align 0 W1: stack_caching 1 W1: aura drop ena 0 W1: aura drop 0 W1: buf_offset 0 W1: buf_size 32 W1: ref_cnt_prof 0 W2: stack_max_pages 13 W2: stack_pages 11 W3: bp_0 0 W3: bp_1 0 W3: bp_2 0 snip .. Signed-off-by: Linu Cherian Signed-off-by: Subbaraya Sundeep --- .../marvell/octeontx2/af/cn20k/debugfs.c | 60 ++++++++++++++++ .../marvell/octeontx2/af/cn20k/debugfs.h | 2 + .../marvell/octeontx2/af/rvu_debugfs.c | 71 ++++++++++++++++--- 3 files changed, 125 insertions(+), 8 deletions(-) diff --git a/drivers/net/ethernet/marvell/octeontx2/af/cn20k/debugfs.c b/dr= ivers/net/ethernet/marvell/octeontx2/af/cn20k/debugfs.c index 3debf2fae1a4..c0cfd3a39c23 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/cn20k/debugfs.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/cn20k/debugfs.c @@ -489,3 +489,63 @@ void print_npa_cn20k_pool_ctx(struct seq_file *m, pool->thresh_qint_idx, pool->err_qint_idx); seq_printf(m, "W8: fc_msh_dst\t\t%d\n", pool->fc_msh_dst); } + +void print_npa_cn20k_halo_ctx(struct seq_file *m, struct npa_aq_enq_rsp *r= sp) +{ + struct npa_cn20k_aq_enq_rsp *cn20k_rsp; + struct npa_cn20k_halo_s *halo; + + cn20k_rsp =3D (struct npa_cn20k_aq_enq_rsp *)rsp; + halo =3D &cn20k_rsp->halo; + + seq_printf(m, "W0: Stack base\t\t%llx\n", halo->stack_base); + + seq_printf(m, "W1: ena \t\t%d\nW1: nat_align \t\t%d\n", + halo->ena, halo->nat_align); + seq_printf(m, "W1: stack_caching\t%d\n", + halo->stack_caching); + seq_printf(m, "W1: aura drop ena\t%d\n", halo->aura_drop_ena); + seq_printf(m, "W1: aura drop\t\t%d\n", halo->aura_drop); + seq_printf(m, "W1: buf_offset\t\t%d\nW1: buf_size\t\t%d\n", + halo->buf_offset, halo->buf_size); + seq_printf(m, "W1: ref_cnt_prof\t\t%d\n", halo->ref_cnt_prof); + seq_printf(m, "W2: stack_max_pages \t%d\nW2: stack_pages\t\t%d\n", + halo->stack_max_pages, halo->stack_pages); + seq_printf(m, "W3: bp_0\t\t%d\nW3: bp_1\t\t%d\nW3: bp_2\t\t%d\n", + halo->bp_0, halo->bp_1, halo->bp_2); + seq_printf(m, "W3: bp_3\t\t%d\nW3: bp_4\t\t%d\nW3: bp_5\t\t%d\n", + halo->bp_3, halo->bp_4, halo->bp_5); + seq_printf(m, "W3: bp_6\t\t%d\nW3: bp_7\t\t%d\nW3: bp_ena_0\t\t%d\n", + halo->bp_6, halo->bp_7, halo->bp_ena_0); + seq_printf(m, "W3: bp_ena_1\t\t%d\nW3: bp_ena_2\t\t%d\n", + halo->bp_ena_1, halo->bp_ena_2); + seq_printf(m, "W3: bp_ena_3\t\t%d\nW3: bp_ena_4\t\t%d\n", + halo->bp_ena_3, halo->bp_ena_4); + seq_printf(m, "W3: bp_ena_5\t\t%d\nW3: bp_ena_6\t\t%d\n", + halo->bp_ena_5, halo->bp_ena_6); + seq_printf(m, "W3: bp_ena_7\t\t%d\n", halo->bp_ena_7); + seq_printf(m, "W4: stack_offset\t%d\nW4: shift\t\t%d\nW4: avg_level\t\t%d= \n", + halo->stack_offset, halo->shift, halo->avg_level); + seq_printf(m, "W4: avg_con \t\t%d\nW4: fc_ena\t\t%d\nW4: fc_stype\t\t%d\n= ", + halo->avg_con, halo->fc_ena, halo->fc_stype); + seq_printf(m, "W4: fc_hyst_bits\t%d\nW4: fc_up_crossing\t%d\n", + halo->fc_hyst_bits, halo->fc_up_crossing); + seq_printf(m, "W4: update_time\t\t%d\n", halo->update_time); + seq_printf(m, "W5: fc_addr\t\t%llx\n", halo->fc_addr); + seq_printf(m, "W6: ptr_start\t\t%llx\n", halo->ptr_start); + seq_printf(m, "W7: ptr_end\t\t%llx\n", halo->ptr_end); + seq_printf(m, "W8: bpid_0\t\t%d\n", halo->bpid_0); + seq_printf(m, "W8: err_int \t\t%d\nW8: err_int_ena\t\t%d\n", + halo->err_int, halo->err_int_ena); + seq_printf(m, "W8: thresh_int\t\t%d\nW8: thresh_int_ena \t%d\n", + halo->thresh_int, halo->thresh_int_ena); + seq_printf(m, "W8: thresh_up\t\t%d\nW8: thresh_qint_idx\t%d\n", + halo->thresh_up, halo->thresh_qint_idx); + seq_printf(m, "W8: err_qint_idx \t%d\n", halo->err_qint_idx); + seq_printf(m, "W9: thresh\t\t%llu\n", (u64)halo->thresh); + seq_printf(m, "W9: fc_msh_dst\t\t%d\n", halo->fc_msh_dst); + seq_printf(m, "W9: op_dpc_ena\t\t%d\nW9: op_dpc_set\t\t%d\n", + halo->op_dpc_ena, halo->op_dpc_set); + seq_printf(m, "W9: stream_ctx\t\t%d\nW9: unified_ctx\t\t%d\n", + halo->stream_ctx, halo->unified_ctx); +} diff --git a/drivers/net/ethernet/marvell/octeontx2/af/cn20k/debugfs.h b/dr= ivers/net/ethernet/marvell/octeontx2/af/cn20k/debugfs.h index 0c5f05883666..7e00c7499e35 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/cn20k/debugfs.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/cn20k/debugfs.h @@ -27,5 +27,7 @@ void print_npa_cn20k_aura_ctx(struct seq_file *m, struct npa_cn20k_aq_enq_rsp *rsp); void print_npa_cn20k_pool_ctx(struct seq_file *m, struct npa_cn20k_aq_enq_rsp *rsp); +void print_npa_cn20k_halo_ctx(struct seq_file *m, + struct npa_aq_enq_rsp *rsp); =20 #endif diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c b/driv= ers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c index 413f9fa40b33..040d8a1bf9d7 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c @@ -975,6 +975,12 @@ static void print_npa_qsize(struct seq_file *m, struct= rvu_pfvf *pfvf) pfvf->aura_ctx->qsize); seq_printf(m, "Aura count : %d\n", pfvf->aura_ctx->qsize); seq_printf(m, "Aura context ena/dis bitmap : %s\n", buf); + if (pfvf->halo_bmap) { + bitmap_print_to_pagebuf(false, buf, pfvf->halo_bmap, + pfvf->aura_ctx->qsize); + seq_printf(m, "Halo context ena/dis bitmap : %s\n", + buf); + } } =20 if (!pfvf->pool_ctx) { @@ -1204,6 +1210,20 @@ static void print_npa_pool_ctx(struct seq_file *m, s= truct npa_aq_enq_rsp *rsp) seq_printf(m, "W8: fc_msh_dst\t\t%d\n", pool->fc_msh_dst); } =20 +static inline char *npa_ctype_str(int ctype) +{ + switch (ctype) { + case NPA_AQ_CTYPE_AURA: + return "aura"; + case NPA_AQ_CTYPE_HALO: + return "halo"; + case NPA_AQ_CTYPE_POOL: + return "pool"; + default: + return NULL; + } +} + /* Reads aura/pool's ctx from admin queue */ static int rvu_dbg_npa_ctx_display(struct seq_file *m, void *unused, int c= type) { @@ -1220,6 +1240,7 @@ static int rvu_dbg_npa_ctx_display(struct seq_file *m= , void *unused, int ctype) =20 switch (ctype) { case NPA_AQ_CTYPE_AURA: + case NPA_AQ_CTYPE_HALO: npalf =3D rvu->rvu_dbg.npa_aura_ctx.lf; id =3D rvu->rvu_dbg.npa_aura_ctx.id; all =3D rvu->rvu_dbg.npa_aura_ctx.all; @@ -1244,6 +1265,9 @@ static int rvu_dbg_npa_ctx_display(struct seq_file *m= , void *unused, int ctype) } else if (ctype =3D=3D NPA_AQ_CTYPE_POOL && !pfvf->pool_ctx) { seq_puts(m, "Pool context is not initialized\n"); return -EINVAL; + } else if (ctype =3D=3D NPA_AQ_CTYPE_HALO && !pfvf->aura_ctx) { + seq_puts(m, "Halo context is not initialized\n"); + return -EINVAL; } =20 memset(&aq_req, 0, sizeof(struct npa_aq_enq_req)); @@ -1253,6 +1277,9 @@ static int rvu_dbg_npa_ctx_display(struct seq_file *m= , void *unused, int ctype) if (ctype =3D=3D NPA_AQ_CTYPE_AURA) { max_id =3D pfvf->aura_ctx->qsize; print_npa_ctx =3D print_npa_aura_ctx; + } else if (ctype =3D=3D NPA_AQ_CTYPE_HALO) { + max_id =3D pfvf->aura_ctx->qsize; + print_npa_ctx =3D print_npa_cn20k_halo_ctx; } else { max_id =3D pfvf->pool_ctx->qsize; print_npa_ctx =3D print_npa_pool_ctx; @@ -1260,8 +1287,7 @@ static int rvu_dbg_npa_ctx_display(struct seq_file *m= , void *unused, int ctype) =20 if (id < 0 || id >=3D max_id) { seq_printf(m, "Invalid %s, valid range is 0-%d\n", - (ctype =3D=3D NPA_AQ_CTYPE_AURA) ? "aura" : "pool", - max_id - 1); + npa_ctype_str(ctype), max_id - 1); return -EINVAL; } =20 @@ -1274,12 +1300,17 @@ static int rvu_dbg_npa_ctx_display(struct seq_file = *m, void *unused, int ctype) aq_req.aura_id =3D aura; =20 /* Skip if queue is uninitialized */ + if (ctype =3D=3D NPA_AQ_CTYPE_AURA && !test_bit(aura, pfvf->aura_bmap)) + continue; + + if (ctype =3D=3D NPA_AQ_CTYPE_HALO && !test_bit(aura, pfvf->halo_bmap)) + continue; + if (ctype =3D=3D NPA_AQ_CTYPE_POOL && !test_bit(aura, pfvf->pool_bmap)) continue; =20 - seq_printf(m, "=3D=3D=3D=3D=3D=3D%s : %d=3D=3D=3D=3D=3D=3D=3D\n", - (ctype =3D=3D NPA_AQ_CTYPE_AURA) ? "AURA" : "POOL", - aq_req.aura_id); + seq_printf(m, "=3D=3D=3D=3D=3D=3D%s : %d=3D=3D=3D=3D=3D=3D=3D\n", npa_ct= ype_str(ctype), + aq_req.aura_id); rc =3D rvu_npa_aq_enq_inst(rvu, &aq_req, &rsp); if (rc) { seq_puts(m, "Failed to read context\n"); @@ -1308,6 +1339,12 @@ static int write_npa_ctx(struct rvu *rvu, bool all, return -EINVAL; } max_id =3D pfvf->aura_ctx->qsize; + } else if (ctype =3D=3D NPA_AQ_CTYPE_HALO) { + if (!pfvf->aura_ctx) { + dev_warn(rvu->dev, "Halo context is not initialized\n"); + return -EINVAL; + } + max_id =3D pfvf->aura_ctx->qsize; } else if (ctype =3D=3D NPA_AQ_CTYPE_POOL) { if (!pfvf->pool_ctx) { dev_warn(rvu->dev, "Pool context is not initialized\n"); @@ -1318,13 +1355,14 @@ static int write_npa_ctx(struct rvu *rvu, bool all, =20 if (id < 0 || id >=3D max_id) { dev_warn(rvu->dev, "Invalid %s, valid range is 0-%d\n", - (ctype =3D=3D NPA_AQ_CTYPE_AURA) ? "aura" : "pool", + npa_ctype_str(ctype), max_id - 1); return -EINVAL; } =20 switch (ctype) { case NPA_AQ_CTYPE_AURA: + case NPA_AQ_CTYPE_HALO: rvu->rvu_dbg.npa_aura_ctx.lf =3D npalf; rvu->rvu_dbg.npa_aura_ctx.id =3D id; rvu->rvu_dbg.npa_aura_ctx.all =3D all; @@ -1383,8 +1421,7 @@ static ssize_t rvu_dbg_npa_ctx_write(struct file *fil= p, const char __user *buffer, size_t count, loff_t *ppos, int ctype) { - char *cmd_buf, *ctype_string =3D (ctype =3D=3D NPA_AQ_CTYPE_AURA) ? - "aura" : "pool"; + char *cmd_buf, *ctype_string =3D npa_ctype_str(ctype); struct seq_file *seqfp =3D filp->private_data; struct rvu *rvu =3D seqfp->private; int npalf, id =3D 0, ret; @@ -1426,6 +1463,21 @@ static int rvu_dbg_npa_aura_ctx_display(struct seq_f= ile *filp, void *unused) =20 RVU_DEBUG_SEQ_FOPS(npa_aura_ctx, npa_aura_ctx_display, npa_aura_ctx_write); =20 +static ssize_t rvu_dbg_npa_halo_ctx_write(struct file *filp, + const char __user *buffer, + size_t count, loff_t *ppos) +{ + return rvu_dbg_npa_ctx_write(filp, buffer, count, ppos, + NPA_AQ_CTYPE_HALO); +} + +static int rvu_dbg_npa_halo_ctx_display(struct seq_file *filp, void *unuse= d) +{ + return rvu_dbg_npa_ctx_display(filp, unused, NPA_AQ_CTYPE_HALO); +} + +RVU_DEBUG_SEQ_FOPS(npa_halo_ctx, npa_halo_ctx_display, npa_halo_ctx_write); + static ssize_t rvu_dbg_npa_pool_ctx_write(struct file *filp, const char __user *buffer, size_t count, loff_t *ppos) @@ -2816,6 +2868,9 @@ static void rvu_dbg_npa_init(struct rvu *rvu) &rvu_dbg_npa_qsize_fops); debugfs_create_file("aura_ctx", 0600, rvu->rvu_dbg.npa, rvu, &rvu_dbg_npa_aura_ctx_fops); + if (is_cn20k(rvu->pdev)) + debugfs_create_file("halo_ctx", 0600, rvu->rvu_dbg.npa, rvu, + &rvu_dbg_npa_halo_ctx_fops); debugfs_create_file("pool_ctx", 0600, rvu->rvu_dbg.npa, rvu, &rvu_dbg_npa_pool_ctx_fops); =20 --=20 2.48.1 From nobody Tue Apr 7 04:18:29 2026 Received: from mx0a-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5FB8E397E80; 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Mon, 16 Mar 2026 05:58:08 -0700 (PDT) Received: from DC6WP-EXCH02.marvell.com (10.76.176.209) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.25; Mon, 16 Mar 2026 05:58:07 -0700 Received: from maili.marvell.com (10.69.176.80) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server id 15.2.1544.25 via Frontend Transport; Mon, 16 Mar 2026 05:58:07 -0700 Received: from hyd1358.marvell.com (unknown [10.29.37.11]) by maili.marvell.com (Postfix) with ESMTP id 149913F7092; Mon, 16 Mar 2026 05:58:03 -0700 (PDT) From: Subbaraya Sundeep To: , , , , , , , CC: , , "Subbaraya Sundeep" Subject: [net-next PATCH 4/4] octeontx2-pf: cn20k: Use unified Halo context Date: Mon, 16 Mar 2026 18:27:39 +0530 Message-ID: <1773665859-4036-5-git-send-email-sbhatta@marvell.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1773665859-4036-1-git-send-email-sbhatta@marvell.com> References: <1773665859-4036-1-git-send-email-sbhatta@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzE2MDA5NyBTYWx0ZWRfX5Xcuw5lvgya0 7euk4xt6czyOcOUMS9lJ/IykvmH7fAdYlPuMnh9cNAOjBCTrkPmXlVBnXCyaFz2Sj+s7zig6uV1 iNBxxVEBQZSIhQpFrBgEi3WctGZWzXOqSALS4WwK+SMc6j1oTTouGmf6uIdch7gINvCFkT33fc3 pjrGyzeX2fKCAmZ0hWemSCW7zCQ8A4FvbMTRTkYoAWRcr3VsXznewzLZrR4qLtSEhYbk60/UUu0 vHGI6kgI4rHy1QFoYxnP+qFVA2+PnaqG5D0h7Y2HPyigest8/DCfwuQHtcS2FssqJ7qcgwn0XO5 ka3BY3nc01aA1lVr40jXriDPpFBjkz0KqInAJSjwshiLAZ4WZIRalo16pVVE5CP3lVMdabaR9BB 7e4xEKGLUB1WMG971gSPLUoF0jn+op76/yiQysQ6gOyMBc9w2KZj95W27TdGPfiwX6dKHYdCkGC P1o3GHxARKMs7OajI4g== X-Proofpoint-GUID: vOl2fyUSQEC1i20WiSKfxdxqhMwQPE7o X-Authority-Analysis: v=2.4 cv=KNtXzVFo c=1 sm=1 tr=0 ts=69b7fe60 cx=c_pps a=gIfcoYsirJbf48DBMSPrZA==:117 a=gIfcoYsirJbf48DBMSPrZA==:17 a=Yq5XynenixoA:10 a=VkNPw1HP01LnGYTKEx00:22 a=l0iWHRpgs5sLHlkKQ1IR:22 a=TtqV-g6YmW1Jfm2GSLaY:22 a=M5GUcnROAAAA:8 a=i30aNKtkkqzyxUofeHAA:9 a=OBjm3rFKGHvpk9ecZwUJ:22 X-Proofpoint-ORIG-GUID: vOl2fyUSQEC1i20WiSKfxdxqhMwQPE7o X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-16_04,2026-03-16_03,2025-10-01_01 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Use unified Halo context present in CN20K hardware for octeontx2 netdevs instead of aura and pool contexts. Signed-off-by: Subbaraya Sundeep --- .../ethernet/marvell/octeontx2/nic/cn20k.c | 190 +++++++++--------- .../ethernet/marvell/octeontx2/nic/cn20k.h | 3 + .../marvell/octeontx2/nic/otx2_common.h | 2 + .../ethernet/marvell/octeontx2/nic/otx2_pf.c | 6 + 4 files changed, 107 insertions(+), 94 deletions(-) diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/cn20k.c b/drivers/n= et/ethernet/marvell/octeontx2/nic/cn20k.c index a5a8f4558717..db2742588bf6 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/cn20k.c +++ b/drivers/net/ethernet/marvell/octeontx2/nic/cn20k.c @@ -517,84 +517,7 @@ int cn20k_tc_alloc_entry(struct otx2_nic *nic, return 0; } =20 -static int cn20k_aura_aq_init(struct otx2_nic *pfvf, int aura_id, - int pool_id, int numptrs) -{ - struct npa_cn20k_aq_enq_req *aq; - struct otx2_pool *pool; - u8 bpid_idx; - int err; - - pool =3D &pfvf->qset.pool[pool_id]; - - /* Allocate memory for HW to update Aura count. - * Alloc one cache line, so that it fits all FC_STYPE modes. - */ - if (!pool->fc_addr) { - err =3D qmem_alloc(pfvf->dev, &pool->fc_addr, 1, OTX2_ALIGN); - if (err) - return err; - } - - /* Initialize this aura's context via AF */ - aq =3D otx2_mbox_alloc_msg_npa_cn20k_aq_enq(&pfvf->mbox); - if (!aq) { - /* Shared mbox memory buffer is full, flush it and retry */ - err =3D otx2_sync_mbox_msg(&pfvf->mbox); - if (err) - return err; - aq =3D otx2_mbox_alloc_msg_npa_cn20k_aq_enq(&pfvf->mbox); - if (!aq) - return -ENOMEM; - } - - aq->aura_id =3D aura_id; - - /* Will be filled by AF with correct pool context address */ - aq->aura.pool_addr =3D pool_id; - aq->aura.pool_caching =3D 1; - aq->aura.shift =3D ilog2(numptrs) - 8; - aq->aura.count =3D numptrs; - aq->aura.limit =3D numptrs; - aq->aura.avg_level =3D 255; - aq->aura.ena =3D 1; - aq->aura.fc_ena =3D 1; - aq->aura.fc_addr =3D pool->fc_addr->iova; - aq->aura.fc_hyst_bits =3D 0; /* Store count on all updates */ - - /* Enable backpressure for RQ aura */ - if (aura_id < pfvf->hw.rqpool_cnt && !is_otx2_lbkvf(pfvf->pdev)) { - aq->aura.bp_ena =3D 0; - /* If NIX1 LF is attached then specify NIX1_RX. - * - * Below NPA_AURA_S[BP_ENA] is set according to the - * NPA_BPINTF_E enumeration given as: - * 0x0 + a*0x1 where 'a' is 0 for NIX0_RX and 1 for NIX1_RX so - * NIX0_RX is 0x0 + 0*0x1 =3D 0 - * NIX1_RX is 0x0 + 1*0x1 =3D 1 - * But in HRM it is given that - * "NPA_AURA_S[BP_ENA](w1[33:32]) - Enable aura backpressure to - * NIX-RX based on [BP] level. One bit per NIX-RX; index - * enumerated by NPA_BPINTF_E." - */ - if (pfvf->nix_blkaddr =3D=3D BLKADDR_NIX1) - aq->aura.bp_ena =3D 1; - - bpid_idx =3D cn20k_aura_bpid_idx(pfvf, aura_id); - aq->aura.bpid =3D pfvf->bpid[bpid_idx]; - - /* Set backpressure level for RQ's Aura */ - aq->aura.bp =3D RQ_BP_LVL_AURA; - } - - /* Fill AQ info */ - aq->ctype =3D NPA_AQ_CTYPE_AURA; - aq->op =3D NPA_AQ_INSTOP_INIT; - - return 0; -} - -static int cn20k_pool_aq_init(struct otx2_nic *pfvf, u16 pool_id, +static int cn20k_halo_aq_init(struct otx2_nic *pfvf, u16 pool_id, int stack_pages, int numptrs, int buf_size, int type) { @@ -610,36 +533,55 @@ static int cn20k_pool_aq_init(struct otx2_nic *pfvf, = u16 pool_id, if (err) return err; =20 + /* Allocate memory for HW to update Aura count. + * Alloc one cache line, so that it fits all FC_STYPE modes. + */ + if (!pool->fc_addr) { + err =3D qmem_alloc(pfvf->dev, &pool->fc_addr, 1, OTX2_ALIGN); + if (err) { + qmem_free(pfvf->dev, pool->stack); + return err; + } + } + pool->rbsize =3D buf_size; =20 - /* Initialize this pool's context via AF */ + /* Initialize this aura's context via AF */ aq =3D otx2_mbox_alloc_msg_npa_cn20k_aq_enq(&pfvf->mbox); if (!aq) { /* Shared mbox memory buffer is full, flush it and retry */ err =3D otx2_sync_mbox_msg(&pfvf->mbox); - if (err) { - qmem_free(pfvf->dev, pool->stack); - return err; - } + if (err) + goto free_mem; aq =3D otx2_mbox_alloc_msg_npa_cn20k_aq_enq(&pfvf->mbox); if (!aq) { - qmem_free(pfvf->dev, pool->stack); - return -ENOMEM; + err =3D -ENOMEM; + goto free_mem; } } =20 aq->aura_id =3D pool_id; - aq->pool.stack_base =3D pool->stack->iova; - aq->pool.stack_caching =3D 1; - aq->pool.ena =3D 1; - aq->pool.buf_size =3D buf_size / 128; - aq->pool.stack_max_pages =3D stack_pages; - aq->pool.shift =3D ilog2(numptrs) - 8; - aq->pool.ptr_start =3D 0; - aq->pool.ptr_end =3D ~0ULL; + + aq->halo.stack_base =3D pool->stack->iova; + aq->halo.stack_caching =3D 1; + aq->halo.ena =3D 1; + aq->halo.buf_size =3D buf_size / 128; + aq->halo.stack_max_pages =3D stack_pages; + aq->halo.shift =3D ilog2(numptrs) - 8; + aq->halo.ptr_start =3D 0; + aq->halo.ptr_end =3D ~0ULL; + + aq->halo.avg_level =3D 255; + aq->halo.fc_ena =3D 1; + aq->halo.fc_addr =3D pool->fc_addr->iova; + aq->halo.fc_hyst_bits =3D 0; /* Store count on all updates */ + + aq->halo.op_dpc_ena =3D 1; + aq->halo.op_dpc_set =3D pfvf->npa_dpc; + aq->halo.unified_ctx =3D 1; =20 /* Fill AQ info */ - aq->ctype =3D NPA_AQ_CTYPE_POOL; + aq->ctype =3D NPA_AQ_CTYPE_HALO; aq->op =3D NPA_AQ_INSTOP_INIT; =20 if (type !=3D AURA_NIX_RQ) { @@ -661,6 +603,66 @@ static int cn20k_pool_aq_init(struct otx2_nic *pfvf, u= 16 pool_id, } =20 return 0; + +free_mem: + qmem_free(pfvf->dev, pool->stack); + qmem_free(pfvf->dev, pool->fc_addr); + return err; +} + +static int cn20k_aura_aq_init(struct otx2_nic *pfvf, int aura_id, + int pool_id, int numptrs) +{ + return 0; +} + +static int cn20k_pool_aq_init(struct otx2_nic *pfvf, u16 pool_id, + int stack_pages, int numptrs, int buf_size, + int type) +{ + return cn20k_halo_aq_init(pfvf, pool_id, stack_pages, + numptrs, buf_size, type); +} + +int cn20k_npa_alloc_dpc(struct otx2_nic *nic) +{ + struct npa_cn20k_dpc_alloc_req *req; + struct npa_cn20k_dpc_alloc_rsp *rsp; + int err; + + req =3D otx2_mbox_alloc_msg_npa_cn20k_dpc_alloc(&nic->mbox); + if (!req) + return -ENOMEM; + + /* Count successful ALLOC requests only */ + req->dpc_conf =3D 1ULL << 4; + + err =3D otx2_sync_mbox_msg(&nic->mbox); + if (err) + return err; + + rsp =3D (struct npa_cn20k_dpc_alloc_rsp *)otx2_mbox_get_rsp(&nic->mbox.mb= ox, + 0, &req->hdr); + + nic->npa_dpc =3D rsp->cntr_id; + + return 0; +} + +int cn20k_npa_free_dpc(struct otx2_nic *nic) +{ + struct npa_cn20k_dpc_free_req *req; + int err; + + req =3D otx2_mbox_alloc_msg_npa_cn20k_dpc_free(&nic->mbox); + if (!req) + return -ENOMEM; + + req->cntr_id =3D nic->npa_dpc; + + err =3D otx2_sync_mbox_msg(&nic->mbox); + + return err; } =20 static int cn20k_sq_aq_init(void *dev, u16 qidx, u8 chan_offset, u16 sqb_a= ura) diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/cn20k.h b/drivers/n= et/ethernet/marvell/octeontx2/nic/cn20k.h index b5e527f6d7eb..16a69d84ea79 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/cn20k.h +++ b/drivers/net/ethernet/marvell/octeontx2/nic/cn20k.h @@ -28,4 +28,7 @@ int cn20k_tc_alloc_entry(struct otx2_nic *nic, struct otx2_tc_flow *new_node, struct npc_install_flow_req *dummy); int cn20k_tc_free_mcam_entry(struct otx2_nic *nic, u16 entry); +int cn20k_npa_alloc_dpc(struct otx2_nic *nic); +int cn20k_npa_free_dpc(struct otx2_nic *nic); + #endif /* CN20K_H */ diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h b/dri= vers/net/ethernet/marvell/octeontx2/nic/otx2_common.h index eecee612b7b2..06d96059d026 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h @@ -592,6 +592,8 @@ struct otx2_nic { struct cn10k_ipsec ipsec; /* af_xdp zero-copy */ unsigned long *af_xdp_zc_qidx; + + u8 npa_dpc; /* NPA DPC counter id */ }; =20 static inline bool is_otx2_lbkvf(struct pci_dev *pdev) diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c b/drivers= /net/ethernet/marvell/octeontx2/nic/otx2_pf.c index ee623476e5ff..2941549d46c8 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c @@ -1651,6 +1651,9 @@ int otx2_init_hw_resources(struct otx2_nic *pf) if (!is_otx2_lbkvf(pf->pdev)) otx2_nix_config_bp(pf, true); =20 + if (is_cn20k(pf->pdev)) + cn20k_npa_alloc_dpc(pf); + /* Init Auras and pools used by NIX RQ, for free buffer ptrs */ err =3D otx2_rq_aura_pool_init(pf); if (err) { @@ -1790,6 +1793,9 @@ void otx2_free_hw_resources(struct otx2_nic *pf) =20 otx2_free_sq_res(pf); =20 + if (is_cn20k(pf->pdev)) + cn20k_npa_free_dpc(pf); + /* Free RQ buffer pointers*/ otx2_free_aura_ptr(pf, AURA_NIX_RQ); =20 --=20 2.48.1