From nobody Tue Apr 7 04:21:20 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 59D4323EA8A; Mon, 16 Mar 2026 09:50:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773654632; cv=none; b=YcNcpUVeNp5yhdN2yijVHDcu4RLuHaVQjB8BQqMsAhypKBje4lNYuRchQvrYIFVDcfAuSH8/lwF3jBwlMWaFJFAGO6K5nbbKfjW0GDmiLZQtpQg/SXr5zRysabJ+S1dYWo7kD5Kb+AX56TuvG3yAuNDHklLneXGv7PXQV7cObxM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773654632; c=relaxed/simple; bh=yBFJXEfNeWu3pYhAjqw7qlGYzpC1t3E1UGAepZk3aGI=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=lKRKqI6JQxpMfvRKggpDjPPjEucI6gCYwH+oFO9+Al4AIEq6AfVTNvcT3A8nMtCgsuBh07rSuRXoUPGUqEpFdDfL1TE7KfPYDiYNUdeLlEhh7mhD42AZxL0vyH/EEcLcTMcs/1KV5y/TBd8T7UBJGxCIuQcG0HcALMttdh8guX4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=SRr9cdFD; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=Zky9QRQR; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="SRr9cdFD"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="Zky9QRQR" Date: Mon, 16 Mar 2026 09:50:26 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1773654627; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=sk+lNIvwrN8FNlvlmF7vD52vyHM3ML5AWnCPuepQU+A=; b=SRr9cdFD8UXcZZvvIJ1HH7XPTr2J4R/7xz/+K3ja3PCQZg4YZPyiRVR37ocqliXUBvF+Er TBabxERfepbwWX/gAx/QwJiVtWFoPopI1mv2nCKXefvns9SMF1n7geCEKPSBXnPCM/XUYb krrcAP7dRx/PEVZlxH+1s0I4Y03Z4BheHET+qykwNvcXw/2I455SKgp5M/e5bLNnzjBEVn puVCOVN+1ckPV1tSKEyA805IBcWxRjHoBxgu/L+ROb3/u96rlKqbqqe4BjKDfWu1FiVIOQ PTw7u3N2hpJpxlePdKjjJF6vfQolrtuW7RgttJ+FEd7wz5y19uCOd48FeLfdPA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1773654627; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=sk+lNIvwrN8FNlvlmF7vD52vyHM3ML5AWnCPuepQU+A=; b=Zky9QRQRLtYDYxKIk0EJEnxil94X9aKHCAQxjJv1zkQjnoiTJBnWGMt8etcz5nZEtSeGH+ 8vF+TKIMBvEvYFDg== From: "tip-bot2 for Dapeng Mi" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: perf/core] perf/x86/intel: Only check GP counters for PEBS constraints validation Cc: Dapeng Mi , "Peter Zijlstra (Intel)" , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20260228053320.140406-1-dapeng1.mi@linux.intel.com> References: <20260228053320.140406-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <177365462602.1647592.10264188395764835683.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the perf/core branch of tip: Commit-ID: b191aa32be2c960ca2391b40e862c389230cadef Gitweb: https://git.kernel.org/tip/b191aa32be2c960ca2391b40e862c3892= 30cadef Author: Dapeng Mi AuthorDate: Sat, 28 Feb 2026 13:33:19 +08:00 Committer: Peter Zijlstra CommitterDate: Thu, 12 Mar 2026 11:29:17 +01:00 perf/x86/intel: Only check GP counters for PEBS constraints validation It's good enough to only check GP counters for PEBS constraints validation since constraints overlap can only happen on GP counters. Besides opportunistically refine the code style and use pr_warn() to replace pr_info() as the message itself is a warning message. Signed-off-by: Dapeng Mi Signed-off-by: Peter Zijlstra (Intel) Link: https://patch.msgid.link/20260228053320.140406-1-dapeng1.mi@linux.int= el.com --- arch/x86/events/intel/core.c | 22 ++++++++++++++-------- 1 file changed, 14 insertions(+), 8 deletions(-) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index cf3a4fe..4768236 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -5770,7 +5770,7 @@ static void __intel_pmu_check_dyn_constr(struct event= _constraint *constr, } =20 if (check_fail) { - pr_info("The two events 0x%llx and 0x%llx may not be " + pr_warn("The two events 0x%llx and 0x%llx may not be " "fully scheduled under some circumstances as " "%s.\n", c1->code, c2->code, dyn_constr_type_name[type]); @@ -5783,6 +5783,7 @@ static void intel_pmu_check_dyn_constr(struct pmu *pm= u, struct event_constraint *constr, u64 cntr_mask) { + u64 gp_mask =3D GENMASK_ULL(INTEL_PMC_MAX_GENERIC - 1, 0); enum dyn_constr_type i; u64 mask; =20 @@ -5797,20 +5798,25 @@ static void intel_pmu_check_dyn_constr(struct pmu *= pmu, mask =3D x86_pmu.lbr_counters; break; case DYN_CONSTR_ACR_CNTR: - mask =3D hybrid(pmu, acr_cntr_mask64) & GENMASK_ULL(INTEL_PMC_MAX_GENER= IC - 1, 0); + mask =3D hybrid(pmu, acr_cntr_mask64) & gp_mask; break; case DYN_CONSTR_ACR_CAUSE: - if (hybrid(pmu, acr_cntr_mask64) =3D=3D hybrid(pmu, acr_cause_mask64)) + if (hybrid(pmu, acr_cntr_mask64) =3D=3D + hybrid(pmu, acr_cause_mask64)) continue; - mask =3D hybrid(pmu, acr_cause_mask64) & GENMASK_ULL(INTEL_PMC_MAX_GENE= RIC - 1, 0); + mask =3D hybrid(pmu, acr_cause_mask64) & gp_mask; break; case DYN_CONSTR_PEBS: - if (x86_pmu.arch_pebs) - mask =3D hybrid(pmu, arch_pebs_cap).counters; + if (x86_pmu.arch_pebs) { + mask =3D hybrid(pmu, arch_pebs_cap).counters & + gp_mask; + } break; case DYN_CONSTR_PDIST: - if (x86_pmu.arch_pebs) - mask =3D hybrid(pmu, arch_pebs_cap).pdists; + if (x86_pmu.arch_pebs) { + mask =3D hybrid(pmu, arch_pebs_cap).pdists & + gp_mask; + } break; default: pr_warn("Unsupported dynamic constraint type %d\n", i);