From nobody Tue Apr 7 16:32:14 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0361523EAB0; Thu, 12 Mar 2026 10:42:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773312124; cv=none; b=nXMcmQQBGvTzgnhF7aIp+XIK+zMl89t+bKqBFETuaq6h4vA3DKTNG4tdqNT/GApls9uwA3o77ZckbWvoqeF4PnkczLLPOJCt81QQCUyEyTcMBlOMT42MDVJipupztHO/No13zsQ/gdkrbjoJh169RmLEcUiYNwJO9Ah5gRfpGEA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773312124; c=relaxed/simple; bh=M/le7j/qlES0Advh1wU3bgHyTmluzbfGmCup/cDLcpI=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=XlARKep4pJE7uKNsxAfvlxeh9svK2xQANtaDfdcbw4eQbBKtfr1OyAkCHVvwBcQG1Zm1Lr/3DssQY6mVr0vAAK+iUsJm7lyor+orIQYE1GDfpulTZng2xASpN0DPgKD4tnIct4zwgZTNCwrPAYgGvYaRWllPqcUJd02z/9RE7Hc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=ndSG2BaL; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=UErmzdsm; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="ndSG2BaL"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="UErmzdsm" Date: Thu, 12 Mar 2026 10:41:59 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1773312121; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=hXihBV8iqrdEqj5i7tnIqFDOBIwFhYNVU7OPpuQAtJg=; b=ndSG2BaLxsDOVxpXMZEdo7fEhiLBDDFqw/juf54OeQ5WOWcKtUA/CXcJRNMLhy1IhZ0vn+ JsgGMwpe3PZ/QnBRVAvQ81V4sZvrXCgkL777JiXKiwIg6Ebqg/AOXwTK1oyUbprXojq6Kg sJw3kzhFRD+tLhIMwcDBkzWaP3EZRj4kDbph4I7Qsth0YCDFWGVpIdCZOixg5HXmXQg/+v MHFQCJYPzI6TfOtE2sa+ecXTQOadPpcSx0TdvMccjETD2Jp74lRhIfJ/IWwfccQqZkbEQj MVl06D56NUI5SdY8SUvCj6gPlpJip+tS/rVYeLmYRjs/Va6i/Q7Ji9xzz5MM+Q== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1773312121; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=hXihBV8iqrdEqj5i7tnIqFDOBIwFhYNVU7OPpuQAtJg=; b=UErmzdsm0QI0evEf+dhyNKu2BzOaUCTSECcvz62jpzHbDE2EHq/6mv9fRmeQXbjDYwRoqo U101r9TPKYtY9uCg== From: "tip-bot2 for Yazen Ghannam" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: ras/core] x86/mce, EDAC/mce_amd: Add new SMCA bank types Cc: Yazen Ghannam , "Borislav Petkov (AMD)" , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20260307163316.345923-4-yazen.ghannam@amd.com> References: <20260307163316.345923-4-yazen.ghannam@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <177331211996.1647592.1561799657048529893.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the ras/core branch of tip: Commit-ID: b90d398138ab3088d168cacb2c3d5248feaa1ef7 Gitweb: https://git.kernel.org/tip/b90d398138ab3088d168cacb2c3d5248f= eaa1ef7 Author: Yazen Ghannam AuthorDate: Sat, 07 Mar 2026 11:33:16 -05:00 Committer: Borislav Petkov (AMD) CommitterDate: Wed, 11 Mar 2026 13:51:59 +01:00 x86/mce, EDAC/mce_amd: Add new SMCA bank types Recognize new SMCA bank types and include their short names for sysfs and long names for decoding. Signed-off-by: Yazen Ghannam Signed-off-by: Borislav Petkov (AMD) Link: https://patch.msgid.link/20260307163316.345923-4-yazen.ghannam@amd.com --- arch/x86/include/asm/mce.h | 11 +++++++++++ arch/x86/kernel/cpu/mce/amd.c | 21 +++++++++++++++++++++ drivers/edac/mce_amd.c | 10 ++++++++++ 3 files changed, 42 insertions(+) diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h index af05ae8..0175d39 100644 --- a/arch/x86/include/asm/mce.h +++ b/arch/x86/include/asm/mce.h @@ -352,7 +352,10 @@ extern void apei_mce_report_mem_error(int corrected, enum smca_bank_types { SMCA_CS, /* Coherent Station */ SMCA_CS_V2, + SMCA_DACC_BE, /* Data Acceleration Back-end */ + SMCA_DACC_FE, /* Data Acceleration Front-end */ SMCA_DE, /* Decoder Unit */ + SMCA_EDDR5CMN, /* eDDR5 CMN */ SMCA_EX, /* Execution Unit */ SMCA_FP, /* Floating Point */ SMCA_GMI_PCS, /* GMI PCS Unit */ @@ -364,12 +367,19 @@ enum smca_bank_types { SMCA_LS_V2, SMCA_MA_LLC, /* Memory Attached Last Level Cache */ SMCA_MP5, /* Microprocessor 5 Unit */ + SMCA_MPART, /* AMD Root of Trust Microprocessor */ + SMCA_MPASP, /* AMD Secure Processor */ + SMCA_MPASP_V2, + SMCA_MPDACC, /* MP for Data Acceleration */ SMCA_MPDMA, /* MPDMA Unit */ + SMCA_MPM, /* Microprocessor Manageability Core */ + SMCA_MPRAS, /* MP for RAS */ SMCA_NBIF, /* NBIF Unit */ SMCA_NBIO, /* Northbridge IO Unit */ SMCA_PB, /* Parameter Block */ SMCA_PCIE, /* PCI Express Unit */ SMCA_PCIE_V2, + SMCA_PCIE_PL, /* PCIe Link */ SMCA_PIE, /* Power, Interrupts, etc. */ SMCA_PSP, /* Platform Security Processor */ SMCA_PSP_V2, @@ -378,6 +388,7 @@ enum smca_bank_types { SMCA_SHUB, /* System HUB Unit */ SMCA_SMU, /* System Management Unit */ SMCA_SMU_V2, + SMCA_SSBDCI, /* Die to Die Interconnect */ SMCA_UMC, /* Unified Memory Controller */ SMCA_UMC_V2, SMCA_USB, /* USB Unit */ diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c index 829a9b6..f746d03 100644 --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -96,7 +96,10 @@ static DEFINE_PER_CPU_READ_MOSTLY(u8[N_SMCA_BANK_TYPES],= smca_bank_counts); =20 static const char * const smca_names[] =3D { [SMCA_CS ... SMCA_CS_V2] =3D "coherent_station", + [SMCA_DACC_BE] =3D "dacc_be", + [SMCA_DACC_FE] =3D "dacc_fe", [SMCA_DE] =3D "decode_unit", + [SMCA_EDDR5CMN] =3D "eddr5_cmn", [SMCA_EX] =3D "execution_unit", [SMCA_FP] =3D "floating_point", [SMCA_GMI_PCS] =3D "gmi_pcs", @@ -107,17 +110,24 @@ static const char * const smca_names[] =3D { [SMCA_LS ... SMCA_LS_V2] =3D "load_store", [SMCA_MA_LLC] =3D "ma_llc", [SMCA_MP5] =3D "mp5", + [SMCA_MPART] =3D "mpart", + [SMCA_MPASP ... SMCA_MPASP_V2] =3D "mpasp", + [SMCA_MPDACC] =3D "mpdacc", [SMCA_MPDMA] =3D "mpdma", + [SMCA_MPM] =3D "mpm", + [SMCA_MPRAS] =3D "mpras", [SMCA_NBIF] =3D "nbif", [SMCA_NBIO] =3D "nbio", [SMCA_PB] =3D "param_block", [SMCA_PCIE ... SMCA_PCIE_V2] =3D "pcie", + [SMCA_PCIE_PL] =3D "pcie_pl", [SMCA_PIE] =3D "pie", [SMCA_PSP ... SMCA_PSP_V2] =3D "psp", [SMCA_RESERVED] =3D "reserved", [SMCA_SATA] =3D "sata", [SMCA_SHUB] =3D "shub", [SMCA_SMU ... SMCA_SMU_V2] =3D "smu", + [SMCA_SSBDCI] =3D "ssbdci", =20 /* UMC v2 is separate because both of them can exist in a single system. = */ [SMCA_UMC] =3D "umc", @@ -162,7 +172,10 @@ EXPORT_SYMBOL_GPL(smca_get_bank_type); static const struct smca_hwid smca_hwid_mcatypes[] =3D { { SMCA_CS, HWID_MCATYPE(0x2E, 0x0) }, { SMCA_CS_V2, HWID_MCATYPE(0x2E, 0x2) }, + { SMCA_DACC_BE, HWID_MCATYPE(0x164, 0x0) }, + { SMCA_DACC_FE, HWID_MCATYPE(0x157, 0x0) }, { SMCA_DE, HWID_MCATYPE(0xB0, 0x3) }, + { SMCA_EDDR5CMN, HWID_MCATYPE(0x1E0, 0x0) }, { SMCA_EX, HWID_MCATYPE(0xB0, 0x5) }, { SMCA_FP, HWID_MCATYPE(0xB0, 0x6) }, { SMCA_GMI_PCS, HWID_MCATYPE(0x241, 0x0) }, @@ -174,12 +187,19 @@ static const struct smca_hwid smca_hwid_mcatypes[] = =3D { { SMCA_LS_V2, HWID_MCATYPE(0xB0, 0x10) }, { SMCA_MA_LLC, HWID_MCATYPE(0x2E, 0x4) }, { SMCA_MP5, HWID_MCATYPE(0x01, 0x2) }, + { SMCA_MPART, HWID_MCATYPE(0xFF, 0x2) }, + { SMCA_MPASP, HWID_MCATYPE(0xFD, 0x0) }, + { SMCA_MPASP_V2, HWID_MCATYPE(0xFD, 0x1) }, + { SMCA_MPDACC, HWID_MCATYPE(0xBE, 0x0) }, { SMCA_MPDMA, HWID_MCATYPE(0x01, 0x3) }, + { SMCA_MPM, HWID_MCATYPE(0xF9, 0x0) }, + { SMCA_MPRAS, HWID_MCATYPE(0x12, 0x0) }, { SMCA_NBIF, HWID_MCATYPE(0x6C, 0x0) }, { SMCA_NBIO, HWID_MCATYPE(0x18, 0x0) }, { SMCA_PB, HWID_MCATYPE(0x05, 0x0) }, { SMCA_PCIE, HWID_MCATYPE(0x46, 0x0) }, { SMCA_PCIE_V2, HWID_MCATYPE(0x46, 0x1) }, + { SMCA_PCIE_PL, HWID_MCATYPE(0x1E1, 0x0) }, { SMCA_PIE, HWID_MCATYPE(0x2E, 0x1) }, { SMCA_PSP, HWID_MCATYPE(0xFF, 0x0) }, { SMCA_PSP_V2, HWID_MCATYPE(0xFF, 0x1) }, @@ -188,6 +208,7 @@ static const struct smca_hwid smca_hwid_mcatypes[] =3D { { SMCA_SHUB, HWID_MCATYPE(0x80, 0x0) }, { SMCA_SMU, HWID_MCATYPE(0x01, 0x0) }, { SMCA_SMU_V2, HWID_MCATYPE(0x01, 0x1) }, + { SMCA_SSBDCI, HWID_MCATYPE(0x5C, 0x0) }, { SMCA_UMC, HWID_MCATYPE(0x96, 0x0) }, { SMCA_UMC_V2, HWID_MCATYPE(0x96, 0x1) }, { SMCA_USB, HWID_MCATYPE(0xAA, 0x0) }, diff --git a/drivers/edac/mce_amd.c b/drivers/edac/mce_amd.c index 54ad56f..bd252cb 100644 --- a/drivers/edac/mce_amd.c +++ b/drivers/edac/mce_amd.c @@ -690,7 +690,10 @@ static void decode_mc6_mce(struct mce *m) =20 static const char * const smca_long_names[] =3D { [SMCA_CS ... SMCA_CS_V2] =3D "Coherent Station", + [SMCA_DACC_BE] =3D "DACC Back-end Unit", + [SMCA_DACC_FE] =3D "DACC Front-end Unit", [SMCA_DE] =3D "Decode Unit", + [SMCA_EDDR5CMN] =3D "eDDR5 CMN Unit", [SMCA_EX] =3D "Execution Unit", [SMCA_FP] =3D "Floating Point Unit", [SMCA_GMI_PCS] =3D "Global Memory Interconnect PCS Unit", @@ -700,17 +703,24 @@ static const char * const smca_long_names[] =3D { [SMCA_L3_CACHE] =3D "L3 Cache", [SMCA_LS ... SMCA_LS_V2] =3D "Load Store Unit", [SMCA_MP5] =3D "Microprocessor 5 Unit", + [SMCA_MPART] =3D "MPART Unit", + [SMCA_MPASP ... SMCA_MPASP_V2] =3D "MPASP Unit", + [SMCA_MPDACC] =3D "MPDACC Unit", [SMCA_MPDMA] =3D "MPDMA Unit", + [SMCA_MPM] =3D "MPM Unit", + [SMCA_MPRAS] =3D "MPRAS Unit", [SMCA_NBIF] =3D "NBIF Unit", [SMCA_NBIO] =3D "Northbridge IO Unit", [SMCA_PB] =3D "Parameter Block", [SMCA_PCIE ... SMCA_PCIE_V2] =3D "PCI Express Unit", + [SMCA_PCIE_PL] =3D "PCIe Link Unit", [SMCA_PIE] =3D "Power, Interrupts, etc.", [SMCA_PSP ... SMCA_PSP_V2] =3D "Platform Security Processor", [SMCA_RESERVED] =3D "Reserved", [SMCA_SATA] =3D "SATA Unit", [SMCA_SHUB] =3D "System Hub Unit", [SMCA_SMU ... SMCA_SMU_V2] =3D "System Management Unit", + [SMCA_SSBDCI] =3D "Die to Die Interconnect Unit", =20 /* UMC v2 is separate because both of them can exist in a single system. = */ [SMCA_UMC] =3D "Unified Memory Controller",