From nobody Tue Apr 7 23:43:44 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6FACB3ECBCA; Wed, 11 Mar 2026 09:31:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773221503; cv=none; b=U/dopNBauDKXHx7NUKHyCxj1ZXbA3LjrSyAEcGEdbWRfyTvkKotX+hpIzWpwiu6EP/Zyoq0xYwzKLKvhafyhj97sydrdLdqlwWfWK4vxuP+lX8KQuGemw0DPVbUukHNf69uX0B/1F1EKDBxF/KdlW4HHag6Nv8r8FCq5wqScCTA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773221503; c=relaxed/simple; bh=CnSoB2kVzB6NU/p7S0Ar6I+vEOv1vW8012eZZSQzsnE=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=U4krFkCOx/Loz1RjH8yO3t3uBwZ1vUvHZuBE//6TbFPtceJKJKX/KcnsGFYszeo661jcb2hcszjz0aN8p0m2as101h+tOS8F3rH4hIwkkfxdlBrPRL2vFyw873VAzN7fyG9HQMwJ2ifHHxnRQ3ML1vPdSd8El4HRlmDFh3xYx4s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=4eUNJzJF; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=kAuhZ+G9; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="4eUNJzJF"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="kAuhZ+G9" Date: Wed, 11 Mar 2026 09:31:39 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1773221501; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=1mUdVnWB0Qy/1T8DHdG2eaeyAI6sNapiW7Bxm1uqjeI=; b=4eUNJzJFlDBozpXAjvPesig/MI0tG+jDL7Y4N/d5ztaHYXJlEFThirQfnzX+AhRUkyOUz5 Lk61P1Jnd7PXBfI+QS3TZ7RN9Yq2An0xPu5CkWKCljarQi/vtDRx21KdBuhRYQGvbZMRD1 2BpmWzKXlHRRaO99pToAL1KZBJ/iVffr5lo+hoe/k5xTeI9OycN/S5vpIecIiUcD+f7Jb1 qhJKiGt+KApfuEKfqgmqjG1eym+pIkssKdcFItoF1XqLpNUH+Rp3qgUT/mmkFDycQjetYA brNXkeqtwk6GFtlpdza9TPvK4VFra3rxDxg6BkQwHwR0OyrXKtGAuelXEVNMSA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1773221501; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=1mUdVnWB0Qy/1T8DHdG2eaeyAI6sNapiW7Bxm1uqjeI=; b=kAuhZ+G9IQPzn00/4fx6MxF2B5pIplq6ZBH6rUtaQyFKTb6iOaGBThWTJ8748ViIutPfPY fuF1YfrDSb+JdwDg== From: tip-bot2 for Thomas =?utf-8?q?Wei=C3=9Fschuh?= Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: timers/vdso] sparc64: vdso: Introduce vdso/processor.h Cc: thomas.weissschuh@linutronix.de, Thomas Gleixner , Andreas Larsson , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20260304-vdso-sparc64-generic-2-v6-9-d8eb3b0e1410@linutronix.de> References: <20260304-vdso-sparc64-generic-2-v6-9-d8eb3b0e1410@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <177322149982.1647592.13254661724612174536.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the timers/vdso branch of tip: Commit-ID: e13e3059dcc27b0b79603925e68200a148b2ef4e Gitweb: https://git.kernel.org/tip/e13e3059dcc27b0b79603925e68200a14= 8b2ef4e Author: Thomas Wei=C3=9Fschuh AuthorDate: Wed, 04 Mar 2026 08:49:06 +01:00 Committer: Thomas Gleixner CommitterDate: Wed, 11 Mar 2026 10:18:32 +01:00 sparc64: vdso: Introduce vdso/processor.h The generic vDSO library expects a vdso/processor.h with an definition of cpu_relax(). Split out cpu_relax() into this dedicated header. Signed-off-by: Thomas Wei=C3=9Fschuh Signed-off-by: Thomas Gleixner Tested-by: Andreas Larsson Reviewed-by: Andreas Larsson Acked-by: Andreas Larsson Link: https://patch.msgid.link/20260304-vdso-sparc64-generic-2-v6-9-d8eb3b0= e1410@linutronix.de --- arch/sparc/include/asm/processor.h | 3 ++- arch/sparc/include/asm/processor_32.h | 2 +- arch/sparc/include/asm/processor_64.h | 25 +--------------- arch/sparc/include/asm/vdso/processor.h | 41 ++++++++++++++++++++++++- 4 files changed, 44 insertions(+), 27 deletions(-) create mode 100644 arch/sparc/include/asm/vdso/processor.h diff --git a/arch/sparc/include/asm/processor.h b/arch/sparc/include/asm/pr= ocessor.h index 18295ea..e34de95 100644 --- a/arch/sparc/include/asm/processor.h +++ b/arch/sparc/include/asm/processor.h @@ -1,6 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0 */ #ifndef ___ASM_SPARC_PROCESSOR_H #define ___ASM_SPARC_PROCESSOR_H + +#include + #if defined(__sparc__) && defined(__arch64__) #include #else diff --git a/arch/sparc/include/asm/processor_32.h b/arch/sparc/include/asm= /processor_32.h index ba8b70f..a074d31 100644 --- a/arch/sparc/include/asm/processor_32.h +++ b/arch/sparc/include/asm/processor_32.h @@ -91,8 +91,6 @@ unsigned long __get_wchan(struct task_struct *); extern struct task_struct *last_task_used_math; int do_mathemu(struct pt_regs *regs, struct task_struct *fpt); =20 -#define cpu_relax() barrier() - extern void (*sparc_idle)(void); =20 #endif diff --git a/arch/sparc/include/asm/processor_64.h b/arch/sparc/include/asm= /processor_64.h index 3218594..4850704 100644 --- a/arch/sparc/include/asm/processor_64.h +++ b/arch/sparc/include/asm/processor_64.h @@ -182,31 +182,6 @@ unsigned long __get_wchan(struct task_struct *task); #define KSTK_EIP(tsk) (task_pt_regs(tsk)->tpc) #define KSTK_ESP(tsk) (task_pt_regs(tsk)->u_regs[UREG_FP]) =20 -/* Please see the commentary in asm/backoff.h for a description of - * what these instructions are doing and how they have been chosen. - * To make a long story short, we are trying to yield the current cpu - * strand during busy loops. - */ -#ifdef BUILD_VDSO -#define cpu_relax() asm volatile("\n99:\n\t" \ - "rd %%ccr, %%g0\n\t" \ - "rd %%ccr, %%g0\n\t" \ - "rd %%ccr, %%g0\n\t" \ - ::: "memory") -#else /* ! BUILD_VDSO */ -#define cpu_relax() asm volatile("\n99:\n\t" \ - "rd %%ccr, %%g0\n\t" \ - "rd %%ccr, %%g0\n\t" \ - "rd %%ccr, %%g0\n\t" \ - ".section .pause_3insn_patch,\"ax\"\n\t"\ - ".word 99b\n\t" \ - "wr %%g0, 128, %%asr27\n\t" \ - "nop\n\t" \ - "nop\n\t" \ - ".previous" \ - ::: "memory") -#endif - /* Prefetch support. This is tuned for UltraSPARC-III and later. * UltraSPARC-I will treat these as nops, and UltraSPARC-II has * a shallower prefetch queue than later chips. diff --git a/arch/sparc/include/asm/vdso/processor.h b/arch/sparc/include/a= sm/vdso/processor.h new file mode 100644 index 0000000..f7a9adc --- /dev/null +++ b/arch/sparc/include/asm/vdso/processor.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef _ASM_SPARC_VDSO_PROCESSOR_H +#define _ASM_SPARC_VDSO_PROCESSOR_H + +#include + +#if defined(__arch64__) + +/* Please see the commentary in asm/backoff.h for a description of + * what these instructions are doing and how they have been chosen. + * To make a long story short, we are trying to yield the current cpu + * strand during busy loops. + */ +#ifdef BUILD_VDSO +#define cpu_relax() asm volatile("\n99:\n\t" \ + "rd %%ccr, %%g0\n\t" \ + "rd %%ccr, %%g0\n\t" \ + "rd %%ccr, %%g0\n\t" \ + ::: "memory") +#else /* ! BUILD_VDSO */ +#define cpu_relax() asm volatile("\n99:\n\t" \ + "rd %%ccr, %%g0\n\t" \ + "rd %%ccr, %%g0\n\t" \ + "rd %%ccr, %%g0\n\t" \ + ".section .pause_3insn_patch,\"ax\"\n\t"\ + ".word 99b\n\t" \ + "wr %%g0, 128, %%asr27\n\t" \ + "nop\n\t" \ + "nop\n\t" \ + ".previous" \ + ::: "memory") +#endif /* BUILD_VDSO */ + +#else /* ! __arch64__ */ + +#define cpu_relax() barrier() + +#endif /* __arch64__ */ + +#endif /* _ASM_SPARC_VDSO_PROCESSOR_H */