From nobody Thu Apr 9 03:30:24 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E17843C6609; Wed, 11 Mar 2026 09:03:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773219837; cv=none; b=bfoSFZsdoE7iszRgBm+W96IT3PulM3+uqtw9FE0vQxF9iJ4D5webeM2R8mV8lhhpPZbsWS2MHYu816BB3oOKsIYaXl97dZJcXD8q5ATpEjCAiU4EWQQ4qd3aObvfUBz6CBeQ/+K9sSlFYOvjl7yU5KC5LXZGyUrIChf2JqtA9Xc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773219837; c=relaxed/simple; bh=n/SVyXn1CuiNwTmaPhUTmRAz1nzLV2XxEKsSINUzWns=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=sUQ/xHd2+HO5EvXBRkM14cclDn3LSxqhY/ZGTa666mLJIZSnbIdpx0Odhl4+XnSWE4JCT5zOaRrqnf+EgouymL16Iy5UIytt9lk6KfaPqvyo2LHRzLNZSNCxsYWb3PwClAy0dfp3LuUrVdQDzVa8KtC0VO83d/UNJupooVHCh0Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=PXF8PR4r; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=x8Jfls37; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="PXF8PR4r"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="x8Jfls37" Date: Wed, 11 Mar 2026 09:03:48 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1773219830; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=wzR+sIOycjSkttGPr+CnMTr0Jg6CHJTqJEOPusjf8ec=; b=PXF8PR4rix90PlTfwu0GRL5gqQWpBj3eHsK+1X5nP5nulnP+2mtxqzZ3vq87bZJFU7crR7 hZRQIllDvWHPTAv7iwZI/Vp46WSoJ9gGxy1KKhuiaeOey2w/FLVHjQlHZ4WUokC0TTUfcc LoiXHdqGsihXULSkHilZQEY4g/pR+MViqYB7aO4jOMhiqzr089fBtqtye30hpZCShhcRhG MBVuO/mbLu4/m25Gc9NtijH6rPjieyHsCJR7nxfgbpE0fhrO4Wi9U/igufcp74j7Jd0gov 1faP4RYCieH3gGDlUhWL+4vlYuojD9BRaCcc1/E8GaybrxYe40dZsReS5X37VA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1773219830; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=wzR+sIOycjSkttGPr+CnMTr0Jg6CHJTqJEOPusjf8ec=; b=x8Jfls37QaijXlO0PABqjgz6gH3rXlRJj8X6jheRHoKt8IQiniaxxDHai5plZNNpDtZt7J vDCAJizviqSXdiCQ== From: "tip-bot2 for Janne Grunau" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: irq/drivers] dt-bindings: interrupt-controller: apple,aic2: Add AICv3 Cc: Janne Grunau , Thomas Gleixner , "Rob Herring (Arm)" , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20260223-irq-apple-aic3-v3-1-2b7328076b8d@jannau.net> References: <20260223-irq-apple-aic3-v3-1-2b7328076b8d@jannau.net> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <177321982835.1647592.9725160392611752750.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the irq/drivers branch of tip: Commit-ID: 0db190e68b2388e367cd101f5d08048ed9b3c61b Gitweb: https://git.kernel.org/tip/0db190e68b2388e367cd101f5d08048ed= 9b3c61b Author: Janne Grunau AuthorDate: Mon, 23 Feb 2026 21:42:46 +01:00 Committer: Thomas Gleixner CommitterDate: Wed, 11 Mar 2026 09:59:28 +01:00 dt-bindings: interrupt-controller: apple,aic2: Add AICv3 AIC version 3 as found on the Apple M3 (t8122) is very similar to AICv2 in its base functionality. It can use the same device tree bindings as AICv2 so add it to the AICv2 bindings. This interrupt controller is used on all Apple SoCs starting with M3 up to at least M5. The only apparent difference is the increased IRQ config offset. Apple's device tree codes this new offset as property of the "aic" node but the value stayed constant for all SoCs with "aic,3". Since the SoC specific compatible "apple,t8122-aic3" will be only used in the driver this offset can remain a driver implementation detail. Signed-off-by: Janne Grunau Signed-off-by: Thomas Gleixner Reviewed-by: Rob Herring (Arm) Link: https://patch.msgid.link/20260223-irq-apple-aic3-v3-1-2b7328076b8d@ja= nnau.net --- Documentation/devicetree/bindings/interrupt-controller/apple,aic2.yaml | 3= 0 +++++++++++++++++++++--------- 1 file changed, 21 insertions(+), 9 deletions(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/apple,a= ic2.yaml b/Documentation/devicetree/bindings/interrupt-controller/apple,aic= 2.yaml index ee5a0df..d0d9a90 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/apple,aic2.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/apple,aic2.yaml @@ -4,10 +4,10 @@ $id: http://devicetree.org/schemas/interrupt-controller/apple,aic2.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# =20 -title: Apple Interrupt Controller 2 +title: Apple Interrupt Controller 2 and 3 =20 maintainers: - - Hector Martin + - Janne Grunau =20 description: | The Apple Interrupt Controller 2 is a simple interrupt controller presen= t on @@ -28,14 +28,24 @@ description: | which do not go through a discrete interrupt controller. It also handles FIQ-based Fast IPIs. =20 + The Apple Interrupt Controller 3 is in its base functionality very simil= ar to + the Apple Interrupt Controller 2 and uses the same device tree bindings.= It is + found on Apple ARM SoCs platforms starting with t8122 (M3). + properties: compatible: - items: - - enum: - - apple,t8112-aic - - apple,t6000-aic - - apple,t6020-aic - - const: apple,aic2 + oneOf: + - items: + - enum: + - apple,t6000-aic + - apple,t6020-aic + - apple,t8112-aic + - const: apple,aic2 + - items: + - enum: + - apple,t6030-aic3 + - const: apple,t8122-aic3 + - const: apple,t8122-aic3 =20 interrupt-controller: true =20 @@ -117,7 +127,9 @@ allOf: properties: compatible: contains: - const: apple,t8112-aic + enum: + - apple,t8112-aic + - apple,t8122-aic3 then: properties: '#interrupt-cells':