From nobody Thu Apr 9 03:29:47 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 652D83B2FF5; Wed, 11 Mar 2026 08:58:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773219505; cv=none; b=LGFuzuXv68qmk8govWMRFmdqbHeggZsv1YkZTcwhcwz5UNdbkabEn2+3llS2xtyhXyqFj/wIOUeG+R6nXWeeChYwA+f5PtJmPXI1YJ1cI4coiOMZP1b1cKQ/VcQYlBaSFja/VQxtyOMwE8dUP4ZFZX2BwN2EFRxOHKW2B4pQyio= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773219505; c=relaxed/simple; bh=nyIw25rpkleK6NgQO2pl2ai0HHDXwFdSG98FrHZ72Z0=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=BZ8F09VyVgni0slIRi3FHhW3+aCleAIsrlcebR97+TlviAnVxlU6M+359vZFe/l1iObbP+h3bkgt0OBHXO0JPqTS0qN3MW1hmxLZ1Mq7itrO76cZa6vZeIVviPQ88UybpAqzzGU1G+8uhNc4i3bLiT8uyKywpqSyVH+NfPvRNzg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=BvksBtFh; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=E2mIAsN9; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="BvksBtFh"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="E2mIAsN9" Date: Wed, 11 Mar 2026 08:58:18 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1773219500; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=cZRECgykEu2YBCmVJEAMADOc5QM7ubh221o88D2YmQo=; b=BvksBtFhi8KlsVg3uu72U8FaiatT/PYoFjzYLIvkxk2/zNAc5yWGhFp3/7c8wgIPVveHGm w7o4PsKo7dSrnBEvNeaTf5HMowPEzitDH5idzhFQaHvXL6lp9izEWlJCGc2Ej8iE4ag/j3 hSLROkndcoK3qqR2PQ3iSfv/c0eY68KtEbaWDVgSvYZgmV+CIump+HZdpnl2WWME3wmHLk lT4fZfOlltBrhXHI9UfzI0oTnCy07se0xIN/+LnVaH83aVJ/l0Qtpls5VFyhz19Hmj0gLp rie1odEHz7cXsQC/qazUCJY+QlxdDO2gXeq3gG2Kyfo16o8ZG1iwxdOo2nm9ag== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1773219500; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=cZRECgykEu2YBCmVJEAMADOc5QM7ubh221o88D2YmQo=; b=E2mIAsN9C16aa1gb0xZ1I/rpK+1LUeJSm5A6npaGpGqtVo8VFBXo6/Kp6nNzyo8E+L808Q eeWbvLXwgvuPgfDQ== From: "tip-bot2 for Ciprian Marian Costea" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: irq/drivers] irqchip/imx-irqsteer: Add NXP S32N79 support Cc: Larisa Grigore , Ciprian Marian Costea , Thomas Gleixner , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20260311081154.381881-4-ciprianmarian.costea@oss.nxp.com> References: <20260311081154.381881-4-ciprianmarian.costea@oss.nxp.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <177321949857.1647592.3058656994957164896.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the irq/drivers branch of tip: Commit-ID: 5e72917802dd65ad1ff57f2158a9d221b4fddf0b Gitweb: https://git.kernel.org/tip/5e72917802dd65ad1ff57f2158a9d221b= 4fddf0b Author: Ciprian Marian Costea AuthorDate: Wed, 11 Mar 2026 09:11:52 +01:00 Committer: Thomas Gleixner CommitterDate: Wed, 11 Mar 2026 09:55:26 +01:00 irqchip/imx-irqsteer: Add NXP S32N79 support Add support for the interrupt steering controller found in NXP S32N79 series automotive SoCs. The S32N79 IRQ_STEER variant differs from the i.MX version by not implementing the CHANCTRL register. To handle this hardware difference, introduce a device type data structure with quirks field. The IRQSTEER_QUIRK_NO_CHANCTRL quirk skips CHANCTRL register access for S32N79 variants. The interrupt routing functionality and register layout are otherwise identical between the two variants. Co-developed-by: Larisa Grigore Signed-off-by: Larisa Grigore Signed-off-by: Ciprian Marian Costea Signed-off-by: Thomas Gleixner Link: https://patch.msgid.link/20260311081154.381881-4-ciprianmarian.costea= @oss.nxp.com --- drivers/irqchip/Kconfig | 6 +-- drivers/irqchip/irq-imx-irqsteer.c | 53 +++++++++++++++++++++-------- 2 files changed, 43 insertions(+), 16 deletions(-) diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index dc26eff..2feecfb 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -544,11 +544,11 @@ config CSKY_APB_INTC =20 config IMX_IRQSTEER bool "i.MX IRQSTEER support" - depends on ARCH_MXC || COMPILE_TEST - default ARCH_MXC + depends on ARCH_MXC || ARCH_S32 || COMPILE_TEST + default y if ARCH_MXC || ARCH_S32 select IRQ_DOMAIN help - Support for the i.MX IRQSTEER interrupt multiplexer/remapper. + Support for the i.MX and S32 IRQSTEER interrupt multiplexer/remapper. =20 config IMX_INTMUX bool "i.MX INTMUX support" if COMPILE_TEST diff --git a/drivers/irqchip/irq-imx-irqsteer.c b/drivers/irqchip/irq-imx-i= rqsteer.c index 4682ce5..87b07f5 100644 --- a/drivers/irqchip/irq-imx-irqsteer.c +++ b/drivers/irqchip/irq-imx-irqsteer.c @@ -26,19 +26,38 @@ =20 #define CHAN_MAX_OUTPUT_INT 0xF =20 +/* SoC does not implement the CHANCTRL register */ +#define IRQSTEER_QUIRK_NO_CHANCTRL BIT(0) + +struct irqsteer_devtype_data { + u32 quirks; +}; + struct irqsteer_data { - void __iomem *regs; - struct clk *ipg_clk; - int irq[CHAN_MAX_OUTPUT_INT]; - int irq_count; - raw_spinlock_t lock; - int reg_num; - int channel; - struct irq_domain *domain; - u32 *saved_reg; - struct device *dev; + void __iomem *regs; + struct clk *ipg_clk; + int irq[CHAN_MAX_OUTPUT_INT]; + int irq_count; + raw_spinlock_t lock; + int reg_num; + int channel; + struct irq_domain *domain; + u32 *saved_reg; + struct device *dev; + const struct irqsteer_devtype_data *devtype_data; +}; + +static const struct irqsteer_devtype_data imx_data =3D { }; + +static const struct irqsteer_devtype_data s32n79_data =3D { + .quirks =3D IRQSTEER_QUIRK_NO_CHANCTRL, }; =20 +static bool irqsteer_has_chanctrl(const struct irqsteer_devtype_data *data) +{ + return !(data->quirks & IRQSTEER_QUIRK_NO_CHANCTRL); +} + static int imx_irqsteer_get_reg_index(struct irqsteer_data *data, unsigned long irqnum) { @@ -188,6 +207,10 @@ static int imx_irqsteer_probe(struct platform_device *= pdev) if (ret) return ret; =20 + data->devtype_data =3D device_get_match_data(&pdev->dev); + if (!data->devtype_data) + return dev_err_probe(&pdev->dev, -ENODEV, "failed to match device data\n= "); + /* * There is one output irq for each group of 64 inputs. * One register bit map can represent 32 input interrupts. @@ -210,7 +233,8 @@ static int imx_irqsteer_probe(struct platform_device *p= dev) } =20 /* steer all IRQs into configured channel */ - writel_relaxed(BIT(data->channel), data->regs + CHANCTRL); + if (irqsteer_has_chanctrl(data->devtype_data)) + writel_relaxed(BIT(data->channel), data->regs + CHANCTRL); =20 data->domain =3D irq_domain_create_linear(dev_fwnode(&pdev->dev), data->r= eg_num * 32, &imx_irqsteer_domain_ops, data); @@ -279,7 +303,9 @@ static void imx_irqsteer_restore_regs(struct irqsteer_d= ata *data) { int i; =20 - writel_relaxed(BIT(data->channel), data->regs + CHANCTRL); + if (irqsteer_has_chanctrl(data->devtype_data)) + writel_relaxed(BIT(data->channel), data->regs + CHANCTRL); + for (i =3D 0; i < data->reg_num; i++) writel_relaxed(data->saved_reg[i], data->regs + CHANMASK(i, data->reg_num)); @@ -319,7 +345,8 @@ static const struct dev_pm_ops imx_irqsteer_pm_ops =3D { }; =20 static const struct of_device_id imx_irqsteer_dt_ids[] =3D { - { .compatible =3D "fsl,imx-irqsteer", }, + { .compatible =3D "fsl,imx-irqsteer", .data =3D &imx_data }, + { .compatible =3D "nxp,s32n79-irqsteer", .data =3D &s32n79_data }, {}, }; =20