From nobody Wed Apr 8 03:09:21 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ECD093D47C2; Tue, 10 Mar 2026 17:37:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773164262; cv=none; b=mutk67BpMDXEAJa7vC7EWB3Zi4b361aAudjVl7fn77Q3FAc+cuKCYXlt186VWuyKqFpiyY1D4UAKDnER5DLMHBakGw0UvgZDs91UlgN+hfBwuFSvmsmjrC2T5/MIeZInwaA2Yg07zOuIHq6OhXxg6VMtJ80V1SPNY5lb9ns4m7Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773164262; c=relaxed/simple; bh=8KvRwiWLlurt59rhtDtb59mui5yNEyPyJX791URwRQI=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=cAyTOTtpVOVckRpFimYqMgrgUAySSOjfx/BrWkL6n6NHywN6Jzl/9xNPTs28UYS5Q1xafOOGW4rE8ZM3Ilm/GlAl0wI+8BXd7UI/si5+B7tPEYJm5m5nhfg4DgapiuP4y5+01V7Xs3/4/z7s1V7Zw0/dmHwpIXTIJv4ZGe+Sgq0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=yQJalAyZ; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=Z+3Q5jxD; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="yQJalAyZ"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="Z+3Q5jxD" Date: Tue, 10 Mar 2026 17:37:38 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1773164259; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=sxD/Zv4gXRQ+lpN4m6C2F49Vlw3oCWngIUYaZNmi0x0=; b=yQJalAyZqJ443RnYJRgCwuFgudSbV8IeH4pL9KhWCq9adEZRZ5lJVsij43njhJWZt0ttrS H36ctUpRtms7FRT8MpFhxFuNW+HnQ3hjB4DIxJpWGIbdVO5k/3zcUtVHX6JOCqfsutZaTJ J5Kgf8QPgkAxjM3v9Pbocvc5roztakC4AAHT4cEt1MAlJFxTH+2zjpsZGMquA2HSj4NB5C CFGIjj8Hnv23WnGHxl6pEpoSJPBHFKKZXWVn/l2fPzspoN1k98DodNTFPBeom7IHhQmkb+ oZqvQ4hwjy0B1o3Vw7e7ByytS7QTtGMY4H3N5WbinFseKMHUChBhEkUXYKP0tg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1773164259; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=sxD/Zv4gXRQ+lpN4m6C2F49Vlw3oCWngIUYaZNmi0x0=; b=Z+3Q5jxD1bQ7/qyNaJyPSwKMK9op0ujCWEGxyDd0EmuVU8Dv5415BXPmr0NQ/3NkEaXz+r IkkoeYSltEZqAUAw== From: "tip-bot2 for Lad Prabhakar" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: irq/drivers] irqchip/renesas-rzv2h: Replace single irq_chip with per-region irq_chip instances Cc: Lad Prabhakar , Thomas Gleixner , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20260304113317.129339-6-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20260304113317.129339-6-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <177316425821.1647592.16014233352268926710.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the irq/drivers branch of tip: Commit-ID: f3ebae6dc025d0e45e9240ed85f9909a5a91e03c Gitweb: https://git.kernel.org/tip/f3ebae6dc025d0e45e9240ed85f9909a5= a91e03c Author: Lad Prabhakar AuthorDate: Wed, 04 Mar 2026 11:33:15=20 Committer: Thomas Gleixner CommitterDate: Tue, 10 Mar 2026 18:34:52 +01:00 irqchip/renesas-rzv2h: Replace single irq_chip with per-region irq_chip ins= tances Replace the single rzv2h_icu_chip and its dispatcher callbacks with dedicated irq_chip instances for each interrupt region: NMI, IRQ, and TINT. Move the irqd_is_level_type() check ahead of the scoped_guard in rzv2h_icu_tint_eoi() and rzv2h_icu_irq_eoi() to avoid acquiring the spinlock unnecessarily for level-type interrupts. Drop the ICU_TINT_START guard from rzv2h_tint_irq_endisable() since it is now only reachable via the TINT chip path. [ tglx: Convert to hwirq_within() ] Signed-off-by: Lad Prabhakar Signed-off-by: Thomas Gleixner Link: https://patch.msgid.link/20260304113317.129339-6-prabhakar.mahadev-la= d.rj@bp.renesas.com --- drivers/irqchip/irq-renesas-rzv2h.c | 174 ++++++++++++++++----------- 1 file changed, 104 insertions(+), 70 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-rene= sas-rzv2h.c index 7ebc0f9..a90107d 100644 --- a/drivers/irqchip/irq-renesas-rzv2h.c +++ b/drivers/irqchip/irq-renesas-rzv2h.c @@ -169,32 +169,47 @@ static inline struct rzv2h_icu_priv *irq_data_to_priv= (struct irq_data *data) return data->domain->host_data; } =20 -static void rzv2h_icu_eoi(struct irq_data *d) +static void rzv2h_icu_tint_eoi(struct irq_data *d) { struct rzv2h_icu_priv *priv =3D irq_data_to_priv(d); unsigned int hw_irq =3D irqd_to_hwirq(d); unsigned int tintirq_nr; u32 bit; =20 - scoped_guard(raw_spinlock, &priv->lock) { - if (hw_irq >=3D ICU_TINT_START) { - tintirq_nr =3D hw_irq - ICU_TINT_START; - bit =3D BIT(tintirq_nr); - if (!irqd_is_level_type(d)) - writel_relaxed(bit, priv->base + priv->info->t_offs + ICU_TSCLR); - } else if (hw_irq >=3D ICU_IRQ_START) { - tintirq_nr =3D hw_irq - ICU_IRQ_START; - bit =3D BIT(tintirq_nr); - if (!irqd_is_level_type(d)) - writel_relaxed(bit, priv->base + ICU_ISCLR); - } else { - writel_relaxed(ICU_NSCLR_NCLR, priv->base + ICU_NSCLR); - } + if (!irqd_is_level_type(d)) { + tintirq_nr =3D hw_irq - ICU_TINT_START; + bit =3D BIT(tintirq_nr); + writel_relaxed(bit, priv->base + priv->info->t_offs + ICU_TSCLR); + } + + irq_chip_eoi_parent(d); +} + +static void rzv2h_icu_irq_eoi(struct irq_data *d) +{ + struct rzv2h_icu_priv *priv =3D irq_data_to_priv(d); + unsigned int hw_irq =3D irqd_to_hwirq(d); + unsigned int tintirq_nr; + u32 bit; + + if (!irqd_is_level_type(d)) { + tintirq_nr =3D hw_irq - ICU_IRQ_START; + bit =3D BIT(tintirq_nr); + writel_relaxed(bit, priv->base + ICU_ISCLR); } =20 irq_chip_eoi_parent(d); } =20 +static void rzv2h_icu_nmi_eoi(struct irq_data *d) +{ + struct rzv2h_icu_priv *priv =3D irq_data_to_priv(d); + + writel_relaxed(ICU_NSCLR_NCLR, priv->base + ICU_NSCLR); + + irq_chip_eoi_parent(d); +} + static void rzv2h_tint_irq_endisable(struct irq_data *d, bool enable) { struct rzv2h_icu_priv *priv =3D irq_data_to_priv(d); @@ -202,9 +217,6 @@ static void rzv2h_tint_irq_endisable(struct irq_data *d= , bool enable) u32 tint_nr, tssel_n, k, tssr; u8 nr_tint; =20 - if (hw_irq < ICU_TINT_START) - return; - tint_nr =3D hw_irq - ICU_TINT_START; nr_tint =3D 32 / priv->info->field_width; k =3D tint_nr / nr_tint; @@ -227,13 +239,13 @@ static void rzv2h_tint_irq_endisable(struct irq_data = *d, bool enable) writel_relaxed(BIT(tint_nr), priv->base + priv->info->t_offs + ICU_TSCLR); } =20 -static void rzv2h_icu_irq_disable(struct irq_data *d) +static void rzv2h_icu_tint_disable(struct irq_data *d) { irq_chip_disable_parent(d); rzv2h_tint_irq_endisable(d, false); } =20 -static void rzv2h_icu_irq_enable(struct irq_data *d) +static void rzv2h_icu_tint_enable(struct irq_data *d) { rzv2h_tint_irq_endisable(d, true); irq_chip_enable_parent(d); @@ -259,7 +271,7 @@ static int rzv2h_nmi_set_type(struct irq_data *d, unsig= ned int type) =20 writel_relaxed(sense, priv->base + ICU_NITSR); =20 - return 0; + return irq_chip_set_type_parent(d, IRQ_TYPE_LEVEL_HIGH); } =20 static void rzv2h_clear_irq_int(struct rzv2h_icu_priv *priv, unsigned int = hwirq) @@ -309,14 +321,15 @@ static int rzv2h_irq_set_type(struct irq_data *d, uns= igned int type) return -EINVAL; } =20 - guard(raw_spinlock)(&priv->lock); - iitsr =3D readl_relaxed(priv->base + ICU_IITSR); - iitsr &=3D ~ICU_IITSR_IITSEL_MASK(irq_nr); - iitsr |=3D ICU_IITSR_IITSEL_PREP(sense, irq_nr); - rzv2h_clear_irq_int(priv, hwirq); - writel_relaxed(iitsr, priv->base + ICU_IITSR); + scoped_guard(raw_spinlock, &priv->lock) { + iitsr =3D readl_relaxed(priv->base + ICU_IITSR); + iitsr &=3D ~ICU_IITSR_IITSEL_MASK(irq_nr); + iitsr |=3D ICU_IITSR_IITSEL_PREP(sense, irq_nr); + rzv2h_clear_irq_int(priv, hwirq); + writel_relaxed(iitsr, priv->base + ICU_IITSR); + } =20 - return 0; + return irq_chip_set_type_parent(d, IRQ_TYPE_LEVEL_HIGH); } =20 static void rzv2h_clear_tint_int(struct rzv2h_icu_priv *priv, unsigned int= hwirq) @@ -391,48 +404,30 @@ static int rzv2h_tint_set_type(struct irq_data *d, un= signed int type) titsr_k =3D ICU_TITSR_K(tint_nr); titsel_n =3D ICU_TITSR_TITSEL_N(tint_nr); =20 - guard(raw_spinlock)(&priv->lock); - - tssr =3D readl_relaxed(priv->base + priv->info->t_offs + ICU_TSSR(tssr_k)= ); - titsr =3D readl_relaxed(priv->base + priv->info->t_offs + ICU_TITSR(titsr= _k)); - - tssr_cur =3D field_get(ICU_TSSR_TSSEL_MASK(tssel_n, priv->info->field_wid= th), tssr); - titsr_cur =3D field_get(ICU_TITSR_TITSEL_MASK(titsel_n), titsr); - if (tssr_cur =3D=3D tint && titsr_cur =3D=3D sense) - return 0; - - tssr &=3D ~(ICU_TSSR_TSSEL_MASK(tssel_n, priv->info->field_width) | tien); - tssr |=3D ICU_TSSR_TSSEL_PREP(tint, tssel_n, priv->info->field_width); - - writel_relaxed(tssr, priv->base + priv->info->t_offs + ICU_TSSR(tssr_k)); - - titsr &=3D ~ICU_TITSR_TITSEL_MASK(titsel_n); - titsr |=3D ICU_TITSR_TITSEL_PREP(sense, titsel_n); + scoped_guard(raw_spinlock, &priv->lock) { + tssr =3D readl_relaxed(priv->base + priv->info->t_offs + ICU_TSSR(tssr_k= )); + titsr =3D readl_relaxed(priv->base + priv->info->t_offs + ICU_TITSR(tits= r_k)); =20 - writel_relaxed(titsr, priv->base + priv->info->t_offs + ICU_TITSR(titsr_k= )); + tssr_cur =3D field_get(ICU_TSSR_TSSEL_MASK(tssel_n, priv->info->field_wi= dth), tssr); + titsr_cur =3D field_get(ICU_TITSR_TITSEL_MASK(titsel_n), titsr); + if (tssr_cur =3D=3D tint && titsr_cur =3D=3D sense) + goto set_parent_type; =20 - rzv2h_clear_tint_int(priv, hwirq); + tssr &=3D ~(ICU_TSSR_TSSEL_MASK(tssel_n, priv->info->field_width) | tien= ); + tssr |=3D ICU_TSSR_TSSEL_PREP(tint, tssel_n, priv->info->field_width); =20 - writel_relaxed(tssr | tien, priv->base + priv->info->t_offs + ICU_TSSR(ts= sr_k)); + writel_relaxed(tssr, priv->base + priv->info->t_offs + ICU_TSSR(tssr_k)); =20 - return 0; -} + titsr &=3D ~ICU_TITSR_TITSEL_MASK(titsel_n); + titsr |=3D ICU_TITSR_TITSEL_PREP(sense, titsel_n); =20 -static int rzv2h_icu_set_type(struct irq_data *d, unsigned int type) -{ - unsigned int hw_irq =3D irqd_to_hwirq(d); - int ret; - - if (hw_irq >=3D ICU_TINT_START) - ret =3D rzv2h_tint_set_type(d, type); - else if (hw_irq >=3D ICU_IRQ_START) - ret =3D rzv2h_irq_set_type(d, type); - else - ret =3D rzv2h_nmi_set_type(d, type); + writel_relaxed(titsr, priv->base + priv->info->t_offs + ICU_TITSR(titsr_= k)); =20 - if (ret) - return ret; + rzv2h_clear_tint_int(priv, hwirq); =20 + writel_relaxed(tssr | tien, priv->base + priv->info->t_offs + ICU_TSSR(t= ssr_k)); + } +set_parent_type: return irq_chip_set_type_parent(d, IRQ_TYPE_LEVEL_HIGH); } =20 @@ -474,17 +469,51 @@ static struct syscore rzv2h_irqc_syscore =3D { .ops =3D &rzv2h_irqc_syscore_ops, }; =20 -static const struct irq_chip rzv2h_icu_chip =3D { +static const struct irq_chip rzv2h_icu_tint_chip =3D { + .name =3D "rzv2h-icu", + .irq_eoi =3D rzv2h_icu_tint_eoi, + .irq_mask =3D irq_chip_mask_parent, + .irq_unmask =3D irq_chip_unmask_parent, + .irq_disable =3D rzv2h_icu_tint_disable, + .irq_enable =3D rzv2h_icu_tint_enable, + .irq_get_irqchip_state =3D irq_chip_get_parent_state, + .irq_set_irqchip_state =3D irq_chip_set_parent_state, + .irq_retrigger =3D irq_chip_retrigger_hierarchy, + .irq_set_type =3D rzv2h_tint_set_type, + .irq_set_affinity =3D irq_chip_set_affinity_parent, + .flags =3D IRQCHIP_MASK_ON_SUSPEND | + IRQCHIP_SET_TYPE_MASKED | + IRQCHIP_SKIP_SET_WAKE, +}; + +static const struct irq_chip rzv2h_icu_irq_chip =3D { + .name =3D "rzv2h-icu", + .irq_eoi =3D rzv2h_icu_irq_eoi, + .irq_mask =3D irq_chip_mask_parent, + .irq_unmask =3D irq_chip_unmask_parent, + .irq_disable =3D irq_chip_disable_parent, + .irq_enable =3D irq_chip_enable_parent, + .irq_get_irqchip_state =3D irq_chip_get_parent_state, + .irq_set_irqchip_state =3D irq_chip_set_parent_state, + .irq_retrigger =3D irq_chip_retrigger_hierarchy, + .irq_set_type =3D rzv2h_irq_set_type, + .irq_set_affinity =3D irq_chip_set_affinity_parent, + .flags =3D IRQCHIP_MASK_ON_SUSPEND | + IRQCHIP_SET_TYPE_MASKED | + IRQCHIP_SKIP_SET_WAKE, +}; + +static const struct irq_chip rzv2h_icu_nmi_chip =3D { .name =3D "rzv2h-icu", - .irq_eoi =3D rzv2h_icu_eoi, + .irq_eoi =3D rzv2h_icu_nmi_eoi, .irq_mask =3D irq_chip_mask_parent, .irq_unmask =3D irq_chip_unmask_parent, - .irq_disable =3D rzv2h_icu_irq_disable, - .irq_enable =3D rzv2h_icu_irq_enable, + .irq_disable =3D irq_chip_disable_parent, + .irq_enable =3D irq_chip_enable_parent, .irq_get_irqchip_state =3D irq_chip_get_parent_state, .irq_set_irqchip_state =3D irq_chip_set_parent_state, .irq_retrigger =3D irq_chip_retrigger_hierarchy, - .irq_set_type =3D rzv2h_icu_set_type, + .irq_set_type =3D rzv2h_nmi_set_type, .irq_set_affinity =3D irq_chip_set_affinity_parent, .flags =3D IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SET_TYPE_MASKED | @@ -497,6 +526,7 @@ static int rzv2h_icu_alloc(struct irq_domain *domain, u= nsigned int virq, unsigne void *arg) { struct rzv2h_icu_priv *priv =3D domain->host_data; + const struct irq_chip *chip; unsigned long tint =3D 0; irq_hw_number_t hwirq; unsigned int type; @@ -518,13 +548,17 @@ static int rzv2h_icu_alloc(struct irq_domain *domain,= unsigned int virq, unsigne =20 if (!hwirq_within(hwirq, ICU_TINT)) return -EINVAL; + chip =3D &rzv2h_icu_tint_chip; + } else if (hwirq_within(hwirq, ICU_IRQ)) { + chip =3D &rzv2h_icu_irq_chip; + } else { + chip =3D &rzv2h_icu_nmi_chip; } =20 if (hwirq > (ICU_NUM_IRQ - 1)) return -EINVAL; =20 - ret =3D irq_domain_set_hwirq_and_chip(domain, virq, hwirq, &rzv2h_icu_chi= p, - (void *)(uintptr_t)tint); + ret =3D irq_domain_set_hwirq_and_chip(domain, virq, hwirq, chip, (void *)= (uintptr_t)tint); if (ret) return ret; =20