From nobody Wed Apr 8 02:51:48 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D3A8B3D16FB; Tue, 10 Mar 2026 17:37:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773164261; cv=none; b=tAmpCIkeLU05D2gylwupx6bTodlssCGr58J/WvIMGfsYuc3f1FAXVLqCmenheHo7eJ0dTPIz86IsKpgLN1yStyJVwulKmEUZo0oYzrzVPSvrmPdIRWmlzZ+STU+jvB5iyBCGskjyKOCbrI1UIABTwG8PS9gd2D4bF1/YDEUn2XI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773164261; c=relaxed/simple; bh=2M/bEstI9zixNIWOUfg3B/4fEFXd5Eb0bO2q5dYfVBY=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=k8R4Ref0cDMc39mai++ZnoJYAYkHbfl1dTqQ8hUmtZgneynhEDtJknfFd8UX1zlfzqBcHs6wHjprtRqtPXLcVKzE7USsUxqdSl+hb1QzNWKfJnUY/JDIazN/XtImTu15/IT7FxRlmvXBtc/jEe4uMbL9I9h+pUvqDfuoPWX5JaU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=OgmcCAKj; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=qxJyWvvO; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="OgmcCAKj"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="qxJyWvvO" Date: Tue, 10 Mar 2026 17:37:37 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1773164258; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=x0sUnoOHC4HY8oJ/E3QpExq180XJnoiLbyWpb0Gt98c=; b=OgmcCAKjFcSZFNn1YjvlKDMN+z4SKE4+nY2vCNk+27egRwJK9lUYN4vokvod1HlcSiJk5A lcEaUfIS2JUIWWdDSs/Fh8egG+8yiXlo6pRxjbx4vtdgcbfXNli8lTdrn7d2REHk/iBEvt Ac32XSn9ioMSBYOmm9WzlJQ+iAjFPcBv20InlOgjr0tblDh234/bU9I6zBX07w5S1T2ykj i1Do0PZCLULs+k9I1zkIFsyO5BfbSHAaI/Gv/dFBsyEgnC/Llgeshn9VGBb6fkYQ7gxpUr 842MeH9/Sz6pZMMDDKYWc4+iSoMrLHsejtgf5qCM5PKN9oIceCigbVRWYu8xyA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1773164258; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=x0sUnoOHC4HY8oJ/E3QpExq180XJnoiLbyWpb0Gt98c=; b=qxJyWvvOud2l0ONmORGyPN6/zjcuZEA5srG4DRjh6wmhKSiIoIPl/7vNgF2nk5NizJB1WH 9fV2dnIJpD4ibaAA== From: "tip-bot2 for Lad Prabhakar" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: irq/drivers] irqchip/renesas-rzv2h: Add CA55 software interrupt support Cc: Lad Prabhakar , Thomas Gleixner , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20260304113317.129339-7-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20260304113317.129339-7-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <177316425710.1647592.10816295257333868693.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the irq/drivers branch of tip: Commit-ID: 61adc4813d67990f6f9c20ab8c4a57fb3d969322 Gitweb: https://git.kernel.org/tip/61adc4813d67990f6f9c20ab8c4a57fb3= d969322 Author: Lad Prabhakar AuthorDate: Wed, 04 Mar 2026 11:33:16=20 Committer: Thomas Gleixner CommitterDate: Tue, 10 Mar 2026 18:34:52 +01:00 irqchip/renesas-rzv2h: Add CA55 software interrupt support The RZ/V2H ICU exposes four software-triggerable interrupts targeting the CA55 cores (int-ca55-0 to int-ca55-3). Add support for these interrupts to enable IRQ injection via the generic IRQ injection framework. Add a dedicated rzv2h_icu_swint_chip irq_chip for the CA55 region and implement rzv2h_icu_irq_set_irqchip_state() to handle software interrupt injection. [ tglx: Convert to hwirq_within() ] Signed-off-by: Lad Prabhakar Signed-off-by: Thomas Gleixner Link: https://patch.msgid.link/20260304113317.129339-7-prabhakar.mahadev-la= d.rj@bp.renesas.com --- drivers/irqchip/irq-renesas-rzv2h.c | 95 +++++++++++++++++++++++++++- 1 file changed, 94 insertions(+), 1 deletion(-) diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-rene= sas-rzv2h.c index a90107d..b10f77c 100644 --- a/drivers/irqchip/irq-renesas-rzv2h.c +++ b/drivers/irqchip/irq-renesas-rzv2h.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -29,7 +30,10 @@ #define ICU_TINT_START (ICU_IRQ_LAST + 1) #define ICU_TINT_COUNT 32 #define ICU_TINT_LAST (ICU_TINT_START + ICU_TINT_COUNT - 1) -#define ICU_NUM_IRQ (ICU_TINT_LAST + 1) +#define ICU_CA55_INT_START (ICU_TINT_LAST + 1) +#define ICU_CA55_INT_COUNT 4 +#define ICU_CA55_INT_LAST (ICU_CA55_INT_START + ICU_CA55_INT_COUNT - 1) +#define ICU_NUM_IRQ (ICU_CA55_INT_LAST + 1) =20 /* Registers */ #define ICU_NSCNT 0x00 @@ -42,6 +46,7 @@ #define ICU_TSCLR 0x24 #define ICU_TITSR(k) (0x28 + (k) * 4) #define ICU_TSSR(k) (0x30 + (k) * 4) +#define ICU_SWINT 0x130 #define ICU_DMkSELy(k, y) (0x420 + (k) * 0x20 + (y) * 4) #define ICU_DMACKSELk(k) (0x500 + (k) * 4) =20 @@ -431,6 +436,27 @@ set_parent_type: return irq_chip_set_type_parent(d, IRQ_TYPE_LEVEL_HIGH); } =20 +static int rzv2h_icu_swint_set_irqchip_state(struct irq_data *d, enum irqc= hip_irq_state which, + bool state) +{ + unsigned int hwirq =3D irqd_to_hwirq(d); + struct rzv2h_icu_priv *priv; + unsigned int bit; + + if (which !=3D IRQCHIP_STATE_PENDING) + return irq_chip_set_parent_state(d, which, state); + + if (!state) + return 0; + + priv =3D irq_data_to_priv(d); + bit =3D BIT(hwirq - ICU_CA55_INT_START); + + /* Trigger the software interrupt */ + writel_relaxed(bit, priv->base + ICU_SWINT); + return 0; +} + static int rzv2h_irqc_irq_suspend(void *data) { struct rzv2h_irqc_reg_cache *cache =3D &rzv2h_icu_data->cache; @@ -520,6 +546,23 @@ static const struct irq_chip rzv2h_icu_nmi_chip =3D { IRQCHIP_SKIP_SET_WAKE, }; =20 +static const struct irq_chip rzv2h_icu_swint_chip =3D { + .name =3D "rzv2h-icu", + .irq_eoi =3D irq_chip_eoi_parent, + .irq_mask =3D irq_chip_mask_parent, + .irq_unmask =3D irq_chip_unmask_parent, + .irq_disable =3D irq_chip_disable_parent, + .irq_enable =3D irq_chip_enable_parent, + .irq_get_irqchip_state =3D irq_chip_get_parent_state, + .irq_set_irqchip_state =3D rzv2h_icu_swint_set_irqchip_state, + .irq_retrigger =3D irq_chip_retrigger_hierarchy, + .irq_set_type =3D irq_chip_set_type_parent, + .irq_set_affinity =3D irq_chip_set_affinity_parent, + .flags =3D IRQCHIP_MASK_ON_SUSPEND | + IRQCHIP_SET_TYPE_MASKED | + IRQCHIP_SKIP_SET_WAKE, +}; + #define hwirq_within(hwirq, which) ((hwirq) >=3D which##_START && (hwirq) = <=3D which##_LAST) =20 static int rzv2h_icu_alloc(struct irq_domain *domain, unsigned int virq, u= nsigned int nr_irqs, @@ -551,6 +594,8 @@ static int rzv2h_icu_alloc(struct irq_domain *domain, u= nsigned int virq, unsigne chip =3D &rzv2h_icu_tint_chip; } else if (hwirq_within(hwirq, ICU_IRQ)) { chip =3D &rzv2h_icu_irq_chip; + } else if (hwirq_within(hwirq, ICU_CA55_INT)) { + chip =3D &rzv2h_icu_swint_chip; } else { chip =3D &rzv2h_icu_nmi_chip; } @@ -588,6 +633,50 @@ static int rzv2h_icu_parse_interrupts(struct rzv2h_icu= _priv *priv, struct device return 0; } =20 +static irqreturn_t rzv2h_icu_swint_irq(int irq, void *data) +{ + u8 cpu =3D *(u8 *)data; + + pr_info("SWINT interrupt for CA55 core %u\n", cpu); + return IRQ_HANDLED; +} + +static int rzv2h_icu_setup_irqs(struct platform_device *pdev, struct irq_d= omain *irq_domain) +{ + bool irq_inject =3D IS_ENABLED(CONFIG_GENERIC_IRQ_INJECTION); + static const char * const rzv2h_swint_names[] =3D { + "int-ca55-0", "int-ca55-1", + "int-ca55-2", "int-ca55-3", + }; + static const u8 swint_idx[] =3D { 0, 1, 2, 3 }; + struct device *dev =3D &pdev->dev; + struct irq_fwspec fwspec; + unsigned int i, virq; + int ret; + + for (i =3D 0; i < ICU_CA55_INT_COUNT && irq_inject; i++) { + fwspec.fwnode =3D irq_domain->fwnode; + fwspec.param_count =3D 2; + fwspec.param[0] =3D ICU_CA55_INT_START + i; + fwspec.param[1] =3D IRQ_TYPE_EDGE_RISING; + + virq =3D irq_create_fwspec_mapping(&fwspec); + if (!virq) { + return dev_err_probe(dev, -EINVAL, "failed to create IRQ mapping for %s= \n", + rzv2h_swint_names[i]); + } + + ret =3D devm_request_irq(dev, virq, rzv2h_icu_swint_irq, 0, dev_name(dev= ), + (void *)&swint_idx[i]); + if (ret) { + return dev_err_probe(dev, ret, "Failed to request %s IRQ\n", + rzv2h_swint_names[i]); + } + } + + return 0; +} + static int rzv2h_icu_probe_common(struct platform_device *pdev, struct dev= ice_node *parent, const struct rzv2h_hw_info *hw_info) { @@ -642,6 +731,10 @@ static int rzv2h_icu_probe_common(struct platform_devi= ce *pdev, struct device_no =20 register_syscore(&rzv2h_irqc_syscore); =20 + ret =3D rzv2h_icu_setup_irqs(pdev, irq_domain); + if (ret) + goto pm_put; + /* * coccicheck complains about a missing put_device call before returning,= but it's a false * positive. We still need dev after successfully returning from this fun= ction.