From nobody Wed Apr 8 02:52:34 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8F8593859D5; Tue, 10 Mar 2026 17:37:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773164260; cv=none; b=IGbap9mQcQOEL/j3JD/M2KL1ErqpVU4+qTUFvm+yS1A7af4xwV22LgwYs1p/7sg8Q1GJP058VcsnlT3r24Yr1jeG6uUWnqhIcQ1g/3RUDqOj/s0IQO6QixZylR2ylIZIU66OWdpCZuJAZ+w1+tT4zcMFogEqZonISjmVieObTpQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773164260; c=relaxed/simple; bh=WIl+cb1EWbJjZ/d7UUlqCpy2MgdDTIqb1UcKZU7o3h0=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=lfJNCnyU6lR3QcPQYUF+b/7UhTO5ogU4oImg5C+06X4y9/q5izUfWf66pMMftldrJ0TIbyeErkeOjHQMoWennKh5YOac9uwNTUcZ/xg42Tb+d6P2GRgEE+v/6BvGvbsjmR3yyS8CIKDHWil5sCzxsE5xluRlxD5TDTpeBBsxi6E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=lfjzgCGI; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=Su5TSeJv; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="lfjzgCGI"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="Su5TSeJv" Date: Tue, 10 Mar 2026 17:37:35 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1773164257; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=URhyIG+au996JHg5bHu2v9VUhi5/qi3RHNVedvbeKDs=; b=lfjzgCGI4oyRzL7tbqqLsAmgT1EozCwOnB42mWOXYcxQuj8A/MIfkxRz9uZ4G3ir/YHmOr dZ2gyiMvhjkf1F0KAwFr2P40Ne/eLBqJYDxD/puX9nquv/DgkAVElNdkkG4gQ4S9KwU2hq 55bmEKbqDVCxw9Oxmu1FxWn/G/eagQVlGD2ceNokxAGZ13b03Wuqel5Qm09AD+UjaopOHF XUXvhDNjhWg7Bmn+Ff7K8jt0gVfJcFvXgAMrtf6bhIEpO963KWDucbY5vDA46Gz/M+eFhK n6ar80WIWe4MwRxzrGR5LAhNuSbcfYhUH8jzycZn6jazfjtd14Gr0mQHpFJwqA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1773164257; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=URhyIG+au996JHg5bHu2v9VUhi5/qi3RHNVedvbeKDs=; b=Su5TSeJvjXiIziHbryT/eEd7btaKpfSalaFah3TlxS1JhxZcR+kIO3PZH6B9I2wRbD5qlP nA0M/yyWRMWd6OCQ== From: "tip-bot2 for Lad Prabhakar" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: irq/drivers] irqchip/renesas-rzv2h: Handle ICU error IRQ and add SWPE trigger Cc: Lad Prabhakar , Thomas Gleixner , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20260304113317.129339-8-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20260304113317.129339-8-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <177316425594.1647592.3943274246228642505.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the irq/drivers branch of tip: Commit-ID: 7585a27644f338b3e764ceeda4be10e7047331a7 Gitweb: https://git.kernel.org/tip/7585a27644f338b3e764ceeda4be10e70= 47331a7 Author: Lad Prabhakar AuthorDate: Wed, 04 Mar 2026 11:33:17=20 Committer: Thomas Gleixner CommitterDate: Tue, 10 Mar 2026 18:34:52 +01:00 irqchip/renesas-rzv2h: Handle ICU error IRQ and add SWPE trigger Handle the RZ/V2H ICU error interrupt to help diagnose latched bus, ECC RAM, and CA55/IP error conditions. Support error injection via ICU_SWPE to allow testing the pseudo error error interrupts. Account for SoC differences in ECC RAM error register coverage so the handler only iterates over valid ECC status/clear banks, and route the RZ/V2N compatible to a probe path with the correct ECC range while keeping the existing RZ/V2H and RZ/G3E handling. [ tglx: Convert to hwirq_within() and upgrade to pr_warn() for those errors= ] Signed-off-by: Lad Prabhakar Signed-off-by: Thomas Gleixner Link: https://patch.msgid.link/20260304113317.129339-8-prabhakar.mahadev-la= d.rj@bp.renesas.com --- drivers/irqchip/irq-renesas-rzv2h.c | 163 ++++++++++++++++++++++++++- 1 file changed, 161 insertions(+), 2 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-rene= sas-rzv2h.c index b10f77c..ce79059 100644 --- a/drivers/irqchip/irq-renesas-rzv2h.c +++ b/drivers/irqchip/irq-renesas-rzv2h.c @@ -33,7 +33,10 @@ #define ICU_CA55_INT_START (ICU_TINT_LAST + 1) #define ICU_CA55_INT_COUNT 4 #define ICU_CA55_INT_LAST (ICU_CA55_INT_START + ICU_CA55_INT_COUNT - 1) -#define ICU_NUM_IRQ (ICU_CA55_INT_LAST + 1) +#define ICU_ERR_INT_START (ICU_CA55_INT_LAST + 1) +#define ICU_ERR_INT_COUNT 1 +#define ICU_ERR_INT_LAST (ICU_ERR_INT_START + ICU_ERR_INT_COUNT - 1) +#define ICU_NUM_IRQ (ICU_ERR_INT_LAST + 1) =20 /* Registers */ #define ICU_NSCNT 0x00 @@ -46,7 +49,15 @@ #define ICU_TSCLR 0x24 #define ICU_TITSR(k) (0x28 + (k) * 4) #define ICU_TSSR(k) (0x30 + (k) * 4) +#define ICU_BEISR(k) (0x70 + (k) * 4) +#define ICU_BECLR(k) (0x80 + (k) * 4) +#define ICU_EREISR(k) (0x90 + (k) * 4) +#define ICU_ERCLR(k) (0xE0 + (k) * 4) #define ICU_SWINT 0x130 +#define ICU_ERINTA55CTL(k) (0x338 + (k) * 4) +#define ICU_ERINTA55CRL(k) (0x348 + (k) * 4) +#define ICU_ERINTA55MSK(k) (0x358 + (k) * 4) +#define ICU_SWPE 0x370 #define ICU_DMkSELy(k, y) (0x420 + (k) * 0x20 + (y) * 4) #define ICU_DMACKSELk(k) (0x500 + (k) * 4) =20 @@ -97,6 +108,10 @@ #define ICU_RZG3E_TSSEL_MAX_VAL 0x8c #define ICU_RZV2H_TSSEL_MAX_VAL 0x55 =20 +#define ICU_SWPE_NUM 16 +#define ICU_NUM_BE 4 +#define ICU_NUM_A55ERR 4 + /** * struct rzv2h_irqc_reg_cache - registers cache (necessary for suspend/re= sume) * @nitsr: ICU_NITSR register @@ -115,12 +130,16 @@ struct rzv2h_irqc_reg_cache { * @t_offs: TINT offset * @max_tssel: TSSEL max value * @field_width: TSSR field width + * @ecc_start: Start index of ECC RAM interrupts + * @ecc_end: End index of ECC RAM interrupts */ struct rzv2h_hw_info { const u8 *tssel_lut; u16 t_offs; u8 max_tssel; u8 field_width; + u8 ecc_start; + u8 ecc_end; }; =20 /* DMAC */ @@ -454,6 +473,36 @@ static int rzv2h_icu_swint_set_irqchip_state(struct ir= q_data *d, enum irqchip_ir =20 /* Trigger the software interrupt */ writel_relaxed(bit, priv->base + ICU_SWINT); + + return 0; +} + +static int rzv2h_icu_swpe_set_irqchip_state(struct irq_data *d, enum irqch= ip_irq_state which, + bool state) +{ + struct rzv2h_icu_priv *priv; + unsigned int bit; + static u8 swpe; + + if (which !=3D IRQCHIP_STATE_PENDING) + return irq_chip_set_parent_state(d, which, state); + + if (!state) + return 0; + + priv =3D irq_data_to_priv(d); + + bit =3D BIT(swpe); + /* + * SWPE has 16 bits; the bit position is rotated on each trigger + * and wraps around once all bits have been used. + */ + if (++swpe >=3D ICU_SWPE_NUM) + swpe =3D 0; + + /* Trigger the pseudo error interrupt */ + writel_relaxed(bit, priv->base + ICU_SWPE); + return 0; } =20 @@ -563,6 +612,23 @@ static const struct irq_chip rzv2h_icu_swint_chip =3D { IRQCHIP_SKIP_SET_WAKE, }; =20 +static const struct irq_chip rzv2h_icu_swpe_err_chip =3D { + .name =3D "rzv2h-icu", + .irq_eoi =3D irq_chip_eoi_parent, + .irq_mask =3D irq_chip_mask_parent, + .irq_unmask =3D irq_chip_unmask_parent, + .irq_disable =3D irq_chip_disable_parent, + .irq_enable =3D irq_chip_enable_parent, + .irq_get_irqchip_state =3D irq_chip_get_parent_state, + .irq_set_irqchip_state =3D rzv2h_icu_swpe_set_irqchip_state, + .irq_retrigger =3D irq_chip_retrigger_hierarchy, + .irq_set_type =3D irq_chip_set_type_parent, + .irq_set_affinity =3D irq_chip_set_affinity_parent, + .flags =3D IRQCHIP_MASK_ON_SUSPEND | + IRQCHIP_SET_TYPE_MASKED | + IRQCHIP_SKIP_SET_WAKE, +}; + #define hwirq_within(hwirq, which) ((hwirq) >=3D which##_START && (hwirq) = <=3D which##_LAST) =20 static int rzv2h_icu_alloc(struct irq_domain *domain, unsigned int virq, u= nsigned int nr_irqs, @@ -596,6 +662,8 @@ static int rzv2h_icu_alloc(struct irq_domain *domain, u= nsigned int virq, unsigne chip =3D &rzv2h_icu_irq_chip; } else if (hwirq_within(hwirq, ICU_CA55_INT)) { chip =3D &rzv2h_icu_swint_chip; + } else if (hwirq_within(hwirq, ICU_ERR_INT)) { + chip =3D &rzv2h_icu_swpe_err_chip; } else { chip =3D &rzv2h_icu_nmi_chip; } @@ -633,6 +701,48 @@ static int rzv2h_icu_parse_interrupts(struct rzv2h_icu= _priv *priv, struct device return 0; } =20 +static irqreturn_t rzv2h_icu_error_irq(int irq, void *data) +{ + struct rzv2h_icu_priv *priv =3D data; + const struct rzv2h_hw_info *hw_info =3D priv->info; + void __iomem *base =3D priv->base; + unsigned int k; + u32 st; + + /* 1) Bus errors (BEISR0..3) */ + for (k =3D 0; k < ICU_NUM_BE; k++) { + st =3D readl(base + ICU_BEISR(k)); + if (!st) + continue; + + writel_relaxed(st, base + ICU_BECLR(k)); + pr_warn("rzv2h-icu: BUS error k=3D%u status=3D0x%08x\n", k, st); + } + + /* 2) ECC RAM errors (EREISR0..X) */ + for (k =3D hw_info->ecc_start; k <=3D hw_info->ecc_end; k++) { + st =3D readl(base + ICU_EREISR(k)); + if (!st) + continue; + + writel_relaxed(st, base + ICU_ERCLR(k)); + pr_warn("rzv2h-icu: ECC error k=3D%u status=3D0x%08x\n", k, st); + } + + /* 3) IP/CA55 error interrupt status (ERINTA55CTL0..3) */ + for (k =3D 0; k < ICU_NUM_A55ERR; k++) { + st =3D readl(base + ICU_ERINTA55CTL(k)); + if (!st) + continue; + + /* there is no relation with status bits so clear all the interrupts */ + writel_relaxed(0xffffffff, base + ICU_ERINTA55CRL(k)); + pr_warn("rzv2h-icu: IP/CA55 error k=3D%u status=3D0x%08x\n", k, st); + } + + return IRQ_HANDLED; +} + static irqreturn_t rzv2h_icu_swint_irq(int irq, void *data) { u8 cpu =3D *(u8 *)data; @@ -643,12 +753,15 @@ static irqreturn_t rzv2h_icu_swint_irq(int irq, void = *data) =20 static int rzv2h_icu_setup_irqs(struct platform_device *pdev, struct irq_d= omain *irq_domain) { + const struct rzv2h_hw_info *hw_info =3D rzv2h_icu_data->info; bool irq_inject =3D IS_ENABLED(CONFIG_GENERIC_IRQ_INJECTION); static const char * const rzv2h_swint_names[] =3D { "int-ca55-0", "int-ca55-1", "int-ca55-2", "int-ca55-3", }; + static const char *icu_err =3D "icu-error-ca55"; static const u8 swint_idx[] =3D { 0, 1, 2, 3 }; + void __iomem *base =3D rzv2h_icu_data->base; struct device *dev =3D &pdev->dev; struct irq_fwspec fwspec; unsigned int i, virq; @@ -674,6 +787,35 @@ static int rzv2h_icu_setup_irqs(struct platform_device= *pdev, struct irq_domain=20 } } =20 + /* Unmask and clear all IP/CA55 error interrupts */ + for (i =3D 0; i < ICU_NUM_A55ERR; i++) { + writel_relaxed(0xffffff, base + ICU_ERINTA55CRL(i)); + writel_relaxed(0x0, base + ICU_ERINTA55MSK(i)); + } + + /* Clear all Bus errors */ + for (i =3D 0; i < ICU_NUM_BE; i++) + writel_relaxed(0xffffffff, base + ICU_BECLR(i)); + + /* Clear all ECCRAM errors */ + for (i =3D hw_info->ecc_start; i <=3D hw_info->ecc_end; i++) + writel_relaxed(0xffffffff, base + ICU_ERCLR(i)); + + fwspec.fwnode =3D irq_domain->fwnode; + fwspec.param_count =3D 2; + fwspec.param[0] =3D ICU_ERR_INT_START; + fwspec.param[1] =3D IRQ_TYPE_LEVEL_HIGH; + + virq =3D irq_create_fwspec_mapping(&fwspec); + if (!virq) { + return dev_err_probe(dev, -EINVAL, "failed to create IRQ mapping for %s\= n", + icu_err); + } + + ret =3D devm_request_irq(dev, virq, rzv2h_icu_error_irq, 0, dev_name(dev)= , rzv2h_icu_data); + if (ret) + return dev_err_probe(dev, ret, "Failed to request %s IRQ\n", icu_err); + return 0; } =20 @@ -778,12 +920,24 @@ static const struct rzv2h_hw_info rzg3e_hw_params =3D= { .t_offs =3D ICU_RZG3E_TINT_OFFSET, .max_tssel =3D ICU_RZG3E_TSSEL_MAX_VAL, .field_width =3D 16, + .ecc_start =3D 1, + .ecc_end =3D 4, +}; + +static const struct rzv2h_hw_info rzv2n_hw_params =3D { + .t_offs =3D 0, + .max_tssel =3D ICU_RZV2H_TSSEL_MAX_VAL, + .field_width =3D 8, + .ecc_start =3D 0, + .ecc_end =3D 2, }; =20 static const struct rzv2h_hw_info rzv2h_hw_params =3D { .t_offs =3D 0, .max_tssel =3D ICU_RZV2H_TSSEL_MAX_VAL, .field_width =3D 8, + .ecc_start =3D 0, + .ecc_end =3D 11, }; =20 static int rzg3e_icu_probe(struct platform_device *pdev, struct device_nod= e *parent) @@ -791,6 +945,11 @@ static int rzg3e_icu_probe(struct platform_device *pde= v, struct device_node *par return rzv2h_icu_probe_common(pdev, parent, &rzg3e_hw_params); } =20 +static int rzv2n_icu_probe(struct platform_device *pdev, struct device_nod= e *parent) +{ + return rzv2h_icu_probe_common(pdev, parent, &rzv2n_hw_params); +} + static int rzv2h_icu_probe(struct platform_device *pdev, struct device_nod= e *parent) { return rzv2h_icu_probe_common(pdev, parent, &rzv2h_hw_params); @@ -798,7 +957,7 @@ static int rzv2h_icu_probe(struct platform_device *pdev= , struct device_node *par =20 IRQCHIP_PLATFORM_DRIVER_BEGIN(rzv2h_icu) IRQCHIP_MATCH("renesas,r9a09g047-icu", rzg3e_icu_probe) -IRQCHIP_MATCH("renesas,r9a09g056-icu", rzv2h_icu_probe) +IRQCHIP_MATCH("renesas,r9a09g056-icu", rzv2n_icu_probe) IRQCHIP_MATCH("renesas,r9a09g057-icu", rzv2h_icu_probe) IRQCHIP_PLATFORM_DRIVER_END(rzv2h_icu) MODULE_AUTHOR("Fabrizio Castro ");