From nobody Mon Apr 13 21:02:13 2026 Received: from mail-m1973183.qiye.163.com (mail-m1973183.qiye.163.com [220.197.31.83]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9DFB839F185 for ; Wed, 4 Mar 2026 10:18:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.31.83 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772619533; cv=none; b=E1N88/Ji3RsXCmrM78CmJLPIcZTNxISEiiwZH6UIR1lAI7Si3KSnm8cMC/Spm6HVvtnqVJbSTcKVUfaJrcHUsKGcTNVph3ohs8XXt+I7vYfHRF5ER6rsF4rwzeUj/SSovdqj5QpDLee2eC53RPiG5VwLNC6t7mbARrlabRPEAqY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772619533; c=relaxed/simple; bh=nrHqE2jSPcsvPm42hp6GCntkfNbbLwoTT1ASfcVb/L0=; h=From:To:Cc:Subject:Date:Message-Id; b=Q3ItDSzDYIewpAhbDoTi6eSFWWPso9piAq6HksUGc1ftFyXk4IRCmG57Uz4a+pzUgJ41mYUCGrBQMMLep7z11cEA++qKCtkH89kKuLsWmv4Ttl8S15Wk+2tsXVCXWnMjpVFXeGmjJN+uvHDKjnIkmYBRbXTWB82u+S0/0VGAWOw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com; spf=pass smtp.mailfrom=rock-chips.com; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b=kwKv2jYS; arc=none smtp.client-ip=220.197.31.83 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b="kwKv2jYS" Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.qiye.163.com (Hmail) with ESMTP id 35ba2940f; Wed, 4 Mar 2026 18:13:38 +0800 (GMT+08:00) From: Shawn Lin To: Vinod Koul Cc: linux-rockchip@lists.infradead.org, linux-phy@lists.infradead.org, Heiko Stuebner , Neil Armstrong , linux-kernel@vger.kernel.org, Shawn Lin Subject: [PATCH] phy: rockchip: naneng-combphy: configure SSC for PCIe on rk3588 and rk3576 Date: Wed, 4 Mar 2026 18:13:31 +0800 Message-Id: <1772619211-99875-1-git-send-email-shawn.lin@rock-chips.com> X-Mailer: git-send-email 2.7.4 X-HM-Tid: 0a9cb856bc0109cckunm4782c6fd1211b72 X-HM-MType: 1 X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFDSUNOT01LS0k3V1ktWUFJV1kPCRoVCBIfWUFZQkIeSFZLTxodGR0fHh5LQkJWFRQJFh oXVRMBExYaEhckFA4PWVdZGBILWUFZTkNVSUlVTFVKSk9ZV1kWGg8SFR0UWUFZT0tIVUpLSU9PT0 hVSktLVUpCS0tZBg++ DKIM-Signature: a=rsa-sha256; b=kwKv2jYSfjbf+NU2SoNUU2ne4Nx44AmIPW0MdGdAPBvjOJYqNIKZZOyrLbsCtRMS0OgHdntdJ493eEPULPEnEc1s54oYvkiG24j0vkcmlRiki/b9IgYtl+20d/Iv2yGLFUdc1V8Gc4dFebNyQsX9+2NOlnIrUwzLFKuzx3c2ctI=; s=default; c=relaxed/relaxed; d=rock-chips.com; v=1; bh=tUOMhFui9GpdBqGsKp6MZutaSK0/qQb/Gl9iLt1soAo=; h=date:mime-version:subject:message-id:from; Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add a dedicated function rk_combphy_cfg_ssc_for_pcie() to configure Spread Spectrum Clocking (SSC) for the PCIe PHY on compatible platforms. The function first checks the device tree node's compatible string. Currently, SSC tuning is specifically implemented and applied only for "rockchip,rk3588-naneng-combphy" and "rockchip,rk3576-naneng-combphy". The correct SSC configuration for these platforms involves: 1. Enabling SSC via the RK3568_PHYREG8_SSC_EN bit. 2. Setting the PLL SSC module control via the newly defined RK3568_PHYREG33_PLL_SSC_CTRL bit. 3. For PCIe phys with a 24MHz reference clock, additional PLL loop divider and signal adjustment values are programmed to optimiz performance. This SSC configuration is intended to improve EMI characteristics or meet specific clock tolerance requirements for PCIe interfaces on these SoCs. Signed-off-by: Shawn Lin --- drivers/phy/rockchip/phy-rockchip-naneng-combphy.c | 93 +++++++++++++-----= ---- 1 file changed, 55 insertions(+), 38 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/p= hy/rockchip/phy-rockchip-naneng-combphy.c index b60d6bf..aa09d71 100644 --- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c +++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c @@ -121,6 +121,7 @@ #define RK3568_PHYREG32_SSC_OFFSET_500PPM 1 =20 #define RK3568_PHYREG33 0x80 +#define RK3568_PHYREG33_PLL_SSC_CTRL BIT(5) #define RK3568_PHYREG33_PLL_KVCO_MASK GENMASK(4, 2) #define RK3568_PHYREG33_PLL_KVCO_SHIFT 2 #define RK3568_PHYREG33_PLL_KVCO_VALUE 2 @@ -964,6 +965,56 @@ static const struct rockchip_combphy_cfg rk3568_combph= y_cfgs =3D { .combphy_cfg =3D rk3568_combphy_cfg, }; =20 +static void rk_combphy_cfg_ssc_for_pcie(struct rockchip_combphy_priv *priv= , unsigned long rate) +{ + struct device_node *np =3D priv->dev->of_node; + u32 val; + + /* Some SoCs' combphys share the same PCIe SSC tuning result */ + if (!of_device_is_compatible(np, "rockchip,rk3588-naneng-combphy") || + !of_device_is_compatible(np, "rockchip,rk3576-naneng-combphy")) { + dev_warn(priv->dev, "Incompatible platform\n"); + return; + } + + val =3D readl(priv->mmio + RK3568_PHYREG8); + val |=3D RK3568_PHYREG8_SSC_EN; + writel(val, priv->mmio + RK3568_PHYREG8); + + /* PLL control SSC module period should be set */ + val =3D readl(priv->mmio + RK3568_PHYREG33); + val |=3D RK3568_PHYREG33_PLL_SSC_CTRL; + writel(val, priv->mmio + RK3568_PHYREG33); + + if (priv->type =3D=3D PHY_TYPE_PCIE && rate =3D=3D REF_CLOCK_24MHz) { + /* Set PLL loop divider */ + writel(0x00, priv->mmio + RK3576_PHYREG17); + writel(RK3568_PHYREG18_PLL_LOOP, priv->mmio + RK3568_PHYREG18); + + /* Set up rx_pck invert and rx msb to disable */ + writel(0x00, priv->mmio + RK3588_PHYREG27); + + /* + * Set up SU adjust signal: + * su_trim[7:0], PLL KVCO adjust bits[2:0] to min + * su_trim[15:8], PLL LPF R1 adujst bits[9:7]=3D3'b101 + * su_trim[23:16], CKRCV adjust + * su_trim[31:24], CKDRV adjust + */ + writel(0x90, priv->mmio + RK3568_PHYREG11); + writel(0x02, priv->mmio + RK3568_PHYREG12); + writel(0x08, priv->mmio + RK3568_PHYREG13); + writel(0x57, priv->mmio + RK3568_PHYREG14); + writel(0x40, priv->mmio + RK3568_PHYREG15); + + writel(RK3568_PHYREG16_SSC_CNT_VALUE, priv->mmio + RK3568_PHYREG16); + + val =3D FIELD_PREP(RK3568_PHYREG33_PLL_KVCO_MASK, + RK3576_PHYREG33_PLL_KVCO_VALUE); + writel(val, priv->mmio + RK3568_PHYREG33); + } +} + static int rk3576_combphy_cfg(struct rockchip_combphy_priv *priv) { const struct rockchip_combphy_grfcfg *cfg =3D priv->cfg->grfcfg; @@ -1156,39 +1207,8 @@ static int rk3576_combphy_cfg(struct rockchip_combph= y_priv *priv) } } =20 - if (priv->enable_ssc) { - val =3D readl(priv->mmio + RK3568_PHYREG8); - val |=3D RK3568_PHYREG8_SSC_EN; - writel(val, priv->mmio + RK3568_PHYREG8); - - if (priv->type =3D=3D PHY_TYPE_PCIE && rate =3D=3D REF_CLOCK_24MHz) { - /* Set PLL loop divider */ - writel(0x00, priv->mmio + RK3576_PHYREG17); - writel(RK3568_PHYREG18_PLL_LOOP, priv->mmio + RK3568_PHYREG18); - - /* Set up rx_pck invert and rx msb to disable */ - writel(0x00, priv->mmio + RK3588_PHYREG27); - - /* - * Set up SU adjust signal: - * su_trim[7:0], PLL KVCO adjust bits[2:0] to min - * su_trim[15:8], PLL LPF R1 adujst bits[9:7]=3D3'b101 - * su_trim[23:16], CKRCV adjust - * su_trim[31:24], CKDRV adjust - */ - writel(0x90, priv->mmio + RK3568_PHYREG11); - writel(0x02, priv->mmio + RK3568_PHYREG12); - writel(0x08, priv->mmio + RK3568_PHYREG13); - writel(0x57, priv->mmio + RK3568_PHYREG14); - writel(0x40, priv->mmio + RK3568_PHYREG15); - - writel(RK3568_PHYREG16_SSC_CNT_VALUE, priv->mmio + RK3568_PHYREG16); - - val =3D FIELD_PREP(RK3568_PHYREG33_PLL_KVCO_MASK, - RK3576_PHYREG33_PLL_KVCO_VALUE); - writel(val, priv->mmio + RK3568_PHYREG33); - } - } + if (priv->enable_ssc) + rk_combphy_cfg_ssc_for_pcie(priv, rate); =20 return 0; } @@ -1371,11 +1391,8 @@ static int rk3588_combphy_cfg(struct rockchip_combph= y_priv *priv) } } =20 - if (priv->enable_ssc) { - val =3D readl(priv->mmio + RK3568_PHYREG8); - val |=3D RK3568_PHYREG8_SSC_EN; - writel(val, priv->mmio + RK3568_PHYREG8); - } + if (priv->enable_ssc) + rk_combphy_cfg_ssc_for_pcie(priv, rate); =20 return 0; } --=20 2.7.4