From nobody Thu Apr 2 18:47:54 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EF59528D8FD; Tue, 17 Feb 2026 10:02:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771322578; cv=none; b=svLZ78w0UWtaTYBHTBhe/dTkN1fPriaDbpVHtZ4seOYPxSx9Eh8AWHnUAe0JEq97tqk1JiOfQsrPL8yM9Vses0R4qvoiKVsr8w4gbad4INU6tKHNd4yVAt27tUT2mN4MJN3yCPhlKNFnVVeAWYjnjbI/teQXr9Hj/Anzp9YZStc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771322578; c=relaxed/simple; bh=1nvNECm0m3yS4Ex03pByxsNNtLBWuCruIQixaI19bxk=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=CLQhh+i9uSBHNcbOWXHUy0WbLnEVvXBRw1bPVliGwvS6Z6pBr7mIHI0xeciQqAZ/JjcdaTzEKm70KrS5hbbr3LzZaeJohxisFR9hjQgRyIeWAF3PcX7am6hvpySrzy34LvzeO0Jbfwn5UXrx8SeSW2VP7qvIKVVcmCYVh0s1qe0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=xRJzTsSn; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=q9WgXhCK; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="xRJzTsSn"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="q9WgXhCK" Date: Tue, 17 Feb 2026 10:02:54 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1771322575; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=8jRDrOOvcDCpip3jrpVtvUK6yidrYwLmHTnygBtmKek=; b=xRJzTsSnfcqJNq7NCx7jKVDpAJ/z8ZLfpXLkHu+0yqqjYrGbCZSbMI5SQpUuFumm+rBkqU jhftby2dR8D/YCy3DOo5g3KXRM3cG1xYDziMGbanmVIjLpogZVNxZ+7G5rzvFyUzV+0DpU KTRth3DwAQxCnxSt3Ug4uH5WBguSvBmGeA13lq61FZGrlqxqmYXNefh/htmYdXjCg0Kt/I 2h1yMUyF0kZU8EPMZEPeqEUIVfGxLhu7JVoBfI3TcNUIhiu+e5TQIVZFdwE70xGf14iXrO kmGyeTcFKHAkDclpBICHz6C/tVap31V3w/C76AAe/FY6R4DnAQliccYrLIdxYA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1771322575; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=8jRDrOOvcDCpip3jrpVtvUK6yidrYwLmHTnygBtmKek=; b=q9WgXhCK5JhhA7SdqnlCBbT9P/QPZ9G7n8o5Df1ETlMcb4Rm8HbNKXfXFNwjjLTJ5d7nTj LM0K25VUMoNgjADA== From: "tip-bot2 for Nam Cao" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: irq/urgent] irqchip/sifive-plic: Fix frozen interrupt due to affinity setting Cc: Nam Cao , Thomas Gleixner , x86@kernel.org, linux-kernel@vger.kernel.org, maz@kernel.org In-Reply-To: <20260212114125.3148067-1-namcao@linutronix.de> References: <20260212114125.3148067-1-namcao@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <177132257426.542.987275771549324608.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the irq/urgent branch of tip: Commit-ID: 1072020685f4b81f6efad3b412cdae0bd62bb043 Gitweb: https://git.kernel.org/tip/1072020685f4b81f6efad3b412cdae0bd= 62bb043 Author: Nam Cao AuthorDate: Thu, 12 Feb 2026 12:41:25 +01:00 Committer: Thomas Gleixner CommitterDate: Tue, 17 Feb 2026 11:00:43 +01:00 irqchip/sifive-plic: Fix frozen interrupt due to affinity setting PLIC ignores interrupt completion message for disabled interrupt, explained by the specification: The PLIC signals it has completed executing an interrupt handler by writing the interrupt ID it received from the claim to the claim/complete register. The PLIC does not check whether the completion ID is the same as the last claim ID for that target. If the completion ID does not match an interrupt source that is currently enabled for the target, the completion is silently ignored. This caused problems in the past, because an interrupt can be disabled while still being handled and plic_irq_eoi() had no effect. That was fixed by checking if the interrupt is disabled, and if so enable it, before sending the completion message. That check is done with irqd_irq_disabled(). However, that is not sufficient because the enable bit for the handling hart can be zero despite irqd_irq_disabled(d) being false. This can happen when affinity setting is changed while a hart is still handling the interrupt. This problem is easily reproducible by dumping a large file to uart (which generates lots of interrupts) and at the same time keep changing the uart interrupt's affinity setting. The uart port becomes frozen almost instantaneously. Fix this by checking PLIC's enable bit instead of irqd_irq_disabled(). Fixes: cc9f04f9a84f ("irqchip/sifive-plic: Implement irq_set_affinity() for= SMP host") Signed-off-by: Nam Cao Signed-off-by: Thomas Gleixner Link: https://patch.msgid.link/20260212114125.3148067-1-namcao@linutronix.de --- drivers/irqchip/irq-sifive-plic.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive= -plic.c index 60fd8f9..7005887 100644 --- a/drivers/irqchip/irq-sifive-plic.c +++ b/drivers/irqchip/irq-sifive-plic.c @@ -172,8 +172,13 @@ static void plic_irq_disable(struct irq_data *d) static void plic_irq_eoi(struct irq_data *d) { struct plic_handler *handler =3D this_cpu_ptr(&plic_handlers); + u32 __iomem *reg; + bool enabled; + + reg =3D handler->enable_base + (d->hwirq / 32) * sizeof(u32); + enabled =3D readl(reg) & BIT(d->hwirq % 32); =20 - if (unlikely(irqd_irq_disabled(d))) { + if (unlikely(!enabled)) { plic_toggle(handler, d->hwirq, 1); writel(d->hwirq, handler->hart_base + CONTEXT_CLAIM); plic_toggle(handler, d->hwirq, 0);