From nobody Mon Feb 9 18:45:12 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CF25837106C for ; Mon, 9 Feb 2026 13:06:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770642412; cv=none; b=ewC2qPsA0WBSS6Fc1y4n3lawai9/gUCwf2Fnhwo6WcPxfmZ0/aPHPghlaTrhjIRosBquUZkBiVSW0QjKPRZxH1kGz5v76WIFpCMAO2ijlogZ+eInrBAIKTFqr4M/aE8D1QdJhGkFdcDzwlBTmYnG/mOx84N3n4B3rzGctQoKd+w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770642412; c=relaxed/simple; bh=51pHOe05040U7aJHOUJ5jMhlFSlZkEf1pU7B6muoA2U=; h=Date:From:To:Cc:Subject:References:Message-ID:Content-Type: MIME-Version; b=PA1xRygD3gNv0rBv4TQyemfUx78o3aQRofGdzQQGbuWcqpN8C2pMNe28pPJqYOU0Ij5ECL7NSmtb8+sizrtE9JYadTCaZQWyAM5RlTzSSddWbP5xvj6V/byMeBn+0HAjXIgeOk7cjKHpx5TsWuldp8PS2PYmHZYOprKUIDko354= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=MmbCUTQb; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="MmbCUTQb" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 48F56C16AAE; Mon, 9 Feb 2026 13:06:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1770642412; bh=51pHOe05040U7aJHOUJ5jMhlFSlZkEf1pU7B6muoA2U=; h=Date:From:To:Cc:Subject:References:From; b=MmbCUTQb9jlbl4Auf+M503zLZVYOMH0JeN8OjhYcmS1pcP/le9wx2jlmqdcffaIj6 DYHlMD4U858+Cu38SS0srNsbC3dk8gdG5EmRlQPd2KTLP8NRXSqUUYLFn/OfZcJUeU eSZAspnxtNyXru2hzCGGRwrx9V9s1yxZKjd/c6oIjuwuZidxDmD5gQCn2pyT8aOb+H vx6EZ1Okf72uJbZ0/zEAYxGOBAgBfwyRgwbeMzZDK8et6NP8Z64JJrOd2bMQreC4dS ojriSqvAZ96gNR/5qbv2DO2czIsp5adCi7CJ/lC4GtH0zeqDI7EDlxYH8eQwJSVSTO 2+z9yCi+i2zsg== Date: Mon, 09 Feb 2026 14:06:50 +0100 From: Thomas Gleixner To: Linus Torvalds Cc: linux-kernel@vger.kernel.org, x86@kernel.org Subject: [GIT pull] x86/irq for v7.0-rc1 References: <177064216682.108186.17056273147252170162.tglx@xen13> Message-ID: <177064217732.108186.3597304893805990404.tglx@xen13> Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Linus, please pull the latest x86/irq branch from: git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git x86-irq-2026-0= 2-09 up to: d441e38a2c87: x86/irq_remapping: Sanitize posted_msi_supported() Trivial cleanups for the posted MSI interrupt handling Thanks, tglx ------------------> Thomas Gleixner (2): x86/irq: Cleanup posted MSI code x86/irq_remapping: Sanitize posted_msi_supported() arch/x86/include/asm/irq_remapping.h | 5 +++-- arch/x86/kernel/irq.c | 31 +++++++++++++------------------ drivers/iommu/intel/irq_remapping.c | 4 ++-- 3 files changed, 18 insertions(+), 22 deletions(-) diff --git a/arch/x86/include/asm/irq_remapping.h b/arch/x86/include/asm/ir= q_remapping.h index 4e55d1755846..37b94f484ef3 100644 --- a/arch/x86/include/asm/irq_remapping.h +++ b/arch/x86/include/asm/irq_remapping.h @@ -67,9 +67,10 @@ static inline struct irq_domain *arch_get_ir_parent_doma= in(void) =20 extern bool enable_posted_msi; =20 -static inline bool posted_msi_supported(void) +static inline bool posted_msi_enabled(void) { - return enable_posted_msi && irq_remapping_cap(IRQ_POSTING_CAP); + return IS_ENABLED(CONFIG_X86_POSTED_MSI) && + enable_posted_msi && irq_remapping_cap(IRQ_POSTING_CAP); } =20 #else /* CONFIG_IRQ_REMAP */ diff --git a/arch/x86/kernel/irq.c b/arch/x86/kernel/irq.c index b2fe6181960c..d817febfd4bc 100644 --- a/arch/x86/kernel/irq.c +++ b/arch/x86/kernel/irq.c @@ -401,11 +401,9 @@ static DEFINE_PER_CPU_CACHE_HOT(bool, posted_msi_handl= er_active); =20 void intel_posted_msi_init(void) { - u32 destination; - u32 apic_id; + u32 destination, apic_id; =20 this_cpu_write(posted_msi_pi_desc.nv, POSTED_MSI_NOTIFICATION_VECTOR); - /* * APIC destination ID is stored in bit 8:15 while in XAPIC mode. * VT-d spec. CH 9.11 @@ -449,8 +447,8 @@ static __always_inline bool handle_pending_pir(unsigned= long *pir, struct pt_reg } =20 /* - * Performance data shows that 3 is good enough to harvest 90+% of the ben= efit - * on high IRQ rate workload. + * Performance data shows that 3 is good enough to harvest 90+% of the + * benefit on high interrupt rate workloads. */ #define MAX_POSTED_MSI_COALESCING_LOOP 3 =20 @@ -460,11 +458,8 @@ static __always_inline bool handle_pending_pir(unsigne= d long *pir, struct pt_reg */ DEFINE_IDTENTRY_SYSVEC(sysvec_posted_msi_notification) { + struct pi_desc *pid =3D this_cpu_ptr(&posted_msi_pi_desc); struct pt_regs *old_regs =3D set_irq_regs(regs); - struct pi_desc *pid; - int i =3D 0; - - pid =3D this_cpu_ptr(&posted_msi_pi_desc); =20 /* Mark the handler active for intel_ack_posted_msi_irq() */ __this_cpu_write(posted_msi_handler_active, true); @@ -472,25 +467,25 @@ DEFINE_IDTENTRY_SYSVEC(sysvec_posted_msi_notification) irq_enter(); =20 /* - * Max coalescing count includes the extra round of handle_pending_pir - * after clearing the outstanding notification bit. Hence, at most - * MAX_POSTED_MSI_COALESCING_LOOP - 1 loops are executed here. + * Loop only MAX_POSTED_MSI_COALESCING_LOOP - 1 times here to take + * the final handle_pending_pir() invocation after clearing the + * outstanding notification bit into account. */ - while (++i < MAX_POSTED_MSI_COALESCING_LOOP) { + for (int i =3D 1; i < MAX_POSTED_MSI_COALESCING_LOOP; i++) { if (!handle_pending_pir(pid->pir, regs)) break; } =20 /* - * Clear outstanding notification bit to allow new IRQ notifications, - * do this last to maximize the window of interrupt coalescing. + * Clear the outstanding notification bit to rearm the notification + * mechanism. */ pi_clear_on(pid); =20 /* - * There could be a race of PI notification and the clearing of ON bit, - * process PIR bits one last time such that handling the new interrupts - * are not delayed until the next IRQ. + * Clearing the ON bit can race with a notification. Process the + * PIR bits one last time so that handling the new interrupts is + * not delayed until the next notification happens. */ handle_pending_pir(pid->pir, regs); =20 diff --git a/drivers/iommu/intel/irq_remapping.c b/drivers/iommu/intel/irq_= remapping.c index 8bcbfe3d9c72..ecb591e98565 100644 --- a/drivers/iommu/intel/irq_remapping.c +++ b/drivers/iommu/intel/irq_remapping.c @@ -1368,7 +1368,7 @@ static void intel_irq_remapping_prepare_irte(struct i= ntel_ir_data *data, break; case X86_IRQ_ALLOC_TYPE_PCI_MSI: case X86_IRQ_ALLOC_TYPE_PCI_MSIX: - if (posted_msi_supported()) { + if (posted_msi_enabled()) { prepare_irte_posted(irte); data->irq_2_iommu.posted_msi =3D 1; } @@ -1460,7 +1460,7 @@ static int intel_irq_remapping_alloc(struct irq_domai= n *domain, =20 irq_data->hwirq =3D (index << 16) + i; irq_data->chip_data =3D ird; - if (posted_msi_supported() && + if (posted_msi_enabled() && ((info->type =3D=3D X86_IRQ_ALLOC_TYPE_PCI_MSI) || (info->type =3D=3D X86_IRQ_ALLOC_TYPE_PCI_MSIX))) irq_data->chip =3D &intel_ir_chip_post_msi;