From nobody Mon Feb 9 20:13:04 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0E211372B38 for ; Mon, 9 Feb 2026 13:06:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770642400; cv=none; b=l4Qu04KZ+w4RoMAcHqKkQXmpY/OMNqwoWM3XwLWP4iXDQ0hXEi6q7J+tfKzE7aVIprHsYtwFBKMCTUSt3D225LKfC4PSGrPU9X7AMr9+t0bK9efWoM7MOQbnTw8Ys/P//0FTrWHBV2/su4lBmYWR86c5wQIhp7FY34h6y5y/mvo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770642400; c=relaxed/simple; bh=hUxPB89LcIoDnZB1a8F2XrnuOsCRtuxgAVeWIKfI2Kw=; h=Date:From:To:Cc:Subject:References:Message-ID:Content-Type: MIME-Version; b=rt8Jep65YmHV3Kr23R01KazZk/eXGDUvzT4fHG7icjkrBihU60DELVxNlyaliUcKTyXCRY8sOWf1lCP+L1BAQwH9GGf8nAzZEYnRNMAz8FRXoBBhJbz7DEUnWG/KBRC/Ok6UAfEem3rXU6zKPw3j5jqOLEqKpT4eS02eHZl3RqA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ZqqX7+K7; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ZqqX7+K7" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 4BBF8C116C6; Mon, 9 Feb 2026 13:06:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1770642399; bh=hUxPB89LcIoDnZB1a8F2XrnuOsCRtuxgAVeWIKfI2Kw=; h=Date:From:To:Cc:Subject:References:From; b=ZqqX7+K7ZlxfkXc45PwLhqWnAz7PtAdNOA6D6G9olvBsIbr5zo0HTaqqFZZmp/9Sv tcl/WdwhT8AKttfCcoPNCRxdQ+BrcT7blvISROpTDeI56bb4uD8HLTlVU4xpTaYpV2 OLJ+J2V6tWW3tl2Wna8cNjmInySI4Rbv7BlBADuVcwSzDHGcFnrXXxTkNg8WlejGMi fYF2laU/lGM19BZT9m1FcmYXHlQdzvSWfGjO1wkaIDXSnydqisWpuJR2RmnlRmJHBh BU8MztKhPbGt5KGy+9o4l3hzssOvdWXYYrfUjBuARSWv6k9kma3X6L34ghtMTQDQwE nvSvlpu4GQ2PQ== Date: Mon, 09 Feb 2026 14:06:37 +0100 From: Thomas Gleixner To: Linus Torvalds Cc: linux-kernel@vger.kernel.org, x86@kernel.org Subject: [GIT pull] timers/clocksource for v7.0-rc1 References: <177064216682.108186.17056273147252170162.tglx@xen13> Message-ID: <177064217290.108186.9544658499954933403.tglx@xen13> Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Linus, please pull the latest timers/clocksource branch from: git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git timers-clockso= urce-2026-02-09 up to: 7eaf8e32de5f: Merge tag 'timers-v7.0' of git://git.kernel.org/pub/s= cm/linux/kernel/git/daniel.lezcano/linux into timers/clocksource Updates for clockevent/clocksource drivers: A rather small set of boring cleanups, fixes and improvements. Thanks, tglx ------------------> Bartosz Golaszewski (1): clocksource/drivers/timer-integrator-ap: Add missing Kconfig dependen= cy on OF Marc Zyngier (1): clocksource/drivers/mips-gic-timer: Move GIC timer to request_percpu_= irq() Niklas S=C3=B6derlund (1): clocksource/drivers/sh_tmu: Always leave device running after probe Soham Metha (1): clocksource/drivers/armada-370-xp: Fix dead link to timer binding Stephen Eta Zhou (1): clocksource/drivers/timer-sp804: Fix an Oops when read_current_timer = is called on ARM32 platforms where the SP804 is not registered as the sched= _clock. drivers/clocksource/Kconfig | 1 + drivers/clocksource/mips-gic-timer.c | 10 ++-------- drivers/clocksource/sh_tmu.c | 18 ------------------ drivers/clocksource/timer-armada-370-xp.c | 2 +- drivers/clocksource/timer-sp804.c | 14 +++++++++----- 5 files changed, 13 insertions(+), 32 deletions(-) diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index aa59e5b13351..fd9112706545 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -254,6 +254,7 @@ config KEYSTONE_TIMER =20 config INTEGRATOR_AP_TIMER bool "Integrator-AP timer driver" if COMPILE_TEST + depends on OF select CLKSRC_MMIO help Enables support for the Integrator-AP timer. diff --git a/drivers/clocksource/mips-gic-timer.c b/drivers/clocksource/mip= s-gic-timer.c index abb685a080a5..1501c7db9a8e 100644 --- a/drivers/clocksource/mips-gic-timer.c +++ b/drivers/clocksource/mips-gic-timer.c @@ -77,13 +77,6 @@ static irqreturn_t gic_compare_interrupt(int irq, void *= dev_id) return IRQ_HANDLED; } =20 -static struct irqaction gic_compare_irqaction =3D { - .handler =3D gic_compare_interrupt, - .percpu_dev_id =3D &gic_clockevent_device, - .flags =3D IRQF_PERCPU | IRQF_TIMER, - .name =3D "timer", -}; - static void gic_clockevent_cpu_init(unsigned int cpu, struct clock_event_device *cd) { @@ -152,7 +145,8 @@ static int gic_clockevent_init(void) if (!gic_frequency) return -ENXIO; =20 - ret =3D setup_percpu_irq(gic_timer_irq, &gic_compare_irqaction); + ret =3D request_percpu_irq(gic_timer_irq, gic_compare_interrupt, + "timer", &gic_clockevent_device); if (ret < 0) { pr_err("IRQ %d setup failed (%d)\n", gic_timer_irq, ret); return ret; diff --git a/drivers/clocksource/sh_tmu.c b/drivers/clocksource/sh_tmu.c index beffff81c00f..3fc6ed9b5630 100644 --- a/drivers/clocksource/sh_tmu.c +++ b/drivers/clocksource/sh_tmu.c @@ -143,16 +143,6 @@ static void sh_tmu_start_stop_ch(struct sh_tmu_channel= *ch, int start) =20 static int __sh_tmu_enable(struct sh_tmu_channel *ch) { - int ret; - - /* enable clock */ - ret =3D clk_enable(ch->tmu->clk); - if (ret) { - dev_err(&ch->tmu->pdev->dev, "ch%u: cannot enable clock\n", - ch->index); - return ret; - } - /* make sure channel is disabled */ sh_tmu_start_stop_ch(ch, 0); =20 @@ -174,7 +164,6 @@ static int sh_tmu_enable(struct sh_tmu_channel *ch) if (ch->enable_count++ > 0) return 0; =20 - pm_runtime_get_sync(&ch->tmu->pdev->dev); dev_pm_syscore_device(&ch->tmu->pdev->dev, true); =20 return __sh_tmu_enable(ch); @@ -187,9 +176,6 @@ static void __sh_tmu_disable(struct sh_tmu_channel *ch) =20 /* disable interrupts in TMU block */ sh_tmu_write(ch, TCR, TCR_TPSC_CLK4); - - /* stop clock */ - clk_disable(ch->tmu->clk); } =20 static void sh_tmu_disable(struct sh_tmu_channel *ch) @@ -203,7 +189,6 @@ static void sh_tmu_disable(struct sh_tmu_channel *ch) __sh_tmu_disable(ch); =20 dev_pm_syscore_device(&ch->tmu->pdev->dev, false); - pm_runtime_put(&ch->tmu->pdev->dev); } =20 static void sh_tmu_set_next(struct sh_tmu_channel *ch, unsigned long delta, @@ -552,7 +537,6 @@ static int sh_tmu_setup(struct sh_tmu_device *tmu, stru= ct platform_device *pdev) goto err_clk_unprepare; =20 tmu->rate =3D clk_get_rate(tmu->clk) / 4; - clk_disable(tmu->clk); =20 /* Map the memory resource. */ ret =3D sh_tmu_map_memory(tmu); @@ -626,8 +610,6 @@ static int sh_tmu_probe(struct platform_device *pdev) out: if (tmu->has_clockevent || tmu->has_clocksource) pm_runtime_irq_safe(&pdev->dev); - else - pm_runtime_idle(&pdev->dev); =20 return 0; } diff --git a/drivers/clocksource/timer-armada-370-xp.c b/drivers/clocksourc= e/timer-armada-370-xp.c index f2b4cc40db93..a405a084cf72 100644 --- a/drivers/clocksource/timer-armada-370-xp.c +++ b/drivers/clocksource/timer-armada-370-xp.c @@ -22,7 +22,7 @@ * doing otherwise leads to using a clocksource whose frequency varies * when doing cpufreq frequency changes. * - * See Documentation/devicetree/bindings/timer/marvell,armada-370-xp-timer= .txt + * See Documentation/devicetree/bindings/timer/marvell,armada-370-timer.ya= ml */ =20 #include diff --git a/drivers/clocksource/timer-sp804.c b/drivers/clocksource/timer-= sp804.c index e82a95ea4724..d69858427359 100644 --- a/drivers/clocksource/timer-sp804.c +++ b/drivers/clocksource/timer-sp804.c @@ -106,21 +106,25 @@ static u64 notrace sp804_read(void) return ~readl_relaxed(sched_clkevt->value); } =20 +/* Register delay timer backed by the hardware counter */ #ifdef CONFIG_ARM static struct delay_timer delay; +static struct sp804_clkevt *delay_clkevt; + static unsigned long sp804_read_delay_timer_read(void) { - return sp804_read(); + return ~readl_relaxed(delay_clkevt->value); } =20 -static void sp804_register_delay_timer(int freq) +static void sp804_register_delay_timer(struct sp804_clkevt *clk, int freq) { + delay_clkevt =3D clk; delay.freq =3D freq; delay.read_current_timer =3D sp804_read_delay_timer_read; register_current_timer_delay(&delay); } #else -static inline void sp804_register_delay_timer(int freq) {} +static inline void sp804_register_delay_timer(struct sp804_clkevt *clk, in= t freq) {} #endif =20 static int __init sp804_clocksource_and_sched_clock_init(void __iomem *bas= e, @@ -135,8 +139,6 @@ static int __init sp804_clocksource_and_sched_clock_ini= t(void __iomem *base, if (rate < 0) return -EINVAL; =20 - sp804_register_delay_timer(rate); - clkevt =3D sp804_clkevt_get(base); =20 writel(0, clkevt->ctrl); @@ -152,6 +154,8 @@ static int __init sp804_clocksource_and_sched_clock_ini= t(void __iomem *base, clocksource_mmio_init(clkevt->value, name, rate, 200, 32, clocksource_mmio_readl_down); =20 + sp804_register_delay_timer(clkevt, rate); + if (use_sched_clock) { sched_clkevt =3D clkevt; sched_clock_register(sp804_read, 32, rate);