From nobody Mon Feb 9 01:34:56 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E94933D412E; Wed, 4 Feb 2026 10:20:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770200450; cv=none; b=sMNoDtHlJFNUFILLiZDPzUCCenZSwL7bxPOsY4PWUZtNx+EWaIL/QTlfMQSGcSzC3eOsususHYoqqdisxscmhkZjm2dwy2Yj1Ry9qRBqKU6DiBYrZTI7SolIYTwXLMXGPdlAoGOujjMoWS+5kCtfAqxrymvjyW4Ym3ECwEgVts8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770200450; c=relaxed/simple; bh=I06696zq2Yh55JLChck134cxivi/wGS1uJowHvU5V6Y=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=TQbRHPB38KHGHrYxoSz8zioNVpWY5BWMCOotfYg9bIV4voKNon0mBPX/fqNj7YKqHsQxUm0usNMkM5IALG4IPwihtTaeze5uMOq4dqkvBfkorejA5tAt+89DU8farRbJ4kYtGA+EzDFgVHk3UEn3fIEgzNqmZy1SPRW5YQTUCLI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=LN3IX7WT; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=s+plRuLU; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="LN3IX7WT"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="s+plRuLU" Date: Wed, 04 Feb 2026 10:20:46 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1770200448; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=EIxJ4p2UNRO/kKqc+c+NrJdpQTtF9mTMGvmsXdKi/uA=; b=LN3IX7WTX/7wXmhjMs7+rEG7KcwEvDniJRnoqMwJ6RzsDq2QCWenVtxhbeomORxxQGKWtI lbbz/PRLPCZCVNi1a/1O1t7GqaHjd3eqOVHdGUg3gzLOWDVJCMUYfnCGogDVzG8Wa4ayjB NIS6HfzZjvJGWIGdmdMzjGHjebSWSv6wJlualj9HOe865ZNgW+f/8T4YgX4QHn8lkynLCU tYKGaF1rnBoQyxHIZdffzSmxdCeyvYPMnFBcsNFdX6k8AeFb7SznjqMPKVUwjExkZGpDcy rEi4vN7Dr00W3t5Q2py0MHrDMfzU8w4B3sQMb1HvBKmTCHFStdJO8erqnWjhFw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1770200448; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=EIxJ4p2UNRO/kKqc+c+NrJdpQTtF9mTMGvmsXdKi/uA=; b=s+plRuLUK7UuDU2u3FPUI0jBc712IlblXnB64TWRUkhSE2MyZXMyG790MPxYzIlvMyuoCB cKZDOLf8zYvduzDA== From: "tip-bot2 for Yangyu Chen" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: irq/drivers] dt-bindings: interrupt-controller: sifive,plic: Clarify the riscv,ndev meaning in PLIC Cc: Yangyu Chen , Thomas Gleixner , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <177020044678.2495410.7909430195430121858.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the irq/drivers branch of tip: Commit-ID: 889588d750506d86ba16ae3b968b5ffc5937d5f8 Gitweb: https://git.kernel.org/tip/889588d750506d86ba16ae3b968b5ffc5= 937d5f8 Author: Yangyu Chen AuthorDate: Wed, 04 Feb 2026 01:21:48 +08:00 Committer: Thomas Gleixner CommitterDate: Wed, 04 Feb 2026 11:13:58 +01:00 dt-bindings: interrupt-controller: sifive,plic: Clarify the riscv,ndev mean= ing in PLIC In PLIC, interrupt source 0 is reserved and should not be used. Therefore, the valid interrupt sources are from 1 to riscv,ndev inclusive. Update the documentation to clarify this point. [ tglx: Fixup subject prefix ] Signed-off-by: Yangyu Chen Signed-off-by: Thomas Gleixner Link: https://patch.msgid.link/tencent_720A4669773B1EE15EC720869C35C2F0490A= @qq.com --- Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.y= aml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,= plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/si= five,plic-1.0.0.yaml index 388fc2c..e026722 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.= 0.0.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.= 0.0.yaml @@ -108,7 +108,9 @@ properties: riscv,ndev: $ref: /schemas/types.yaml#/definitions/uint32 description: - Specifies how many external interrupts are supported by this control= ler. + Specifies how many external (device) interrupts are supported by this + controller. Note that source 0 is reserved in PLIC, so the valid + interrupt sources are 1 to riscv,ndev inclusive. =20 clocks: true =20