From nobody Sun Feb 8 22:22:04 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B260126ED25; Sat, 31 Jan 2026 00:18:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769818702; cv=none; b=LB2Nvy92J7oQI8JX4WnmIce8Wgprfb94K5wOXn9YNvpz8yA9W8JXxwLtqcogxOYQw94pPx8VQmG+SlvE5kkQylBZHt+tsmzjhfcCSp7Y2ugg41wAH+xM+Hey4ZSFiK/A/9i0oXNZM2jlTTnZNRYcNAefJ9QSj4+JMRmfKoK5gFg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769818702; c=relaxed/simple; bh=yD3DRAWI88uLdPsLY0ccQ50SnXpLCQYi4Ibh/pIL7Vo=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=QXjzRX6D4k4q0hpYUdpgaxttt0yqtFBgqxS5Zp1WiBEU5sleNfobqoJw5Tgf/Iop8bhLatlR3knGRfMe1rS6ScsnSBS2EMy0vigSYh94K7h2mhLcXxi5oGdTZRW8wR6qU1HPmQByummlj+tfK7Xuy/PAqqzTNlGsQQx64CKUwlM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=3or3TYVi; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=TieKVLxD; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="3or3TYVi"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="TieKVLxD" Date: Sat, 31 Jan 2026 00:18:14 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1769818696; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=mlHC5Oc/wPfJ31HEj1ju7nH9g6ibBIbC1zhAHaSBltU=; b=3or3TYVicrO0EErAd8LbHUod53MYP+U9DcFLX5HS1f71/gH4fuLjtCjlp/N3EfrCj/s52/ Eq0OyT3O56R9Rz8/LhNP+CqAXYqVqAu7STZt1rF6lHL3PhxYs/yB4LTI+IVPDYn1sDmTpn iQCkyildTiWqon4QpWTB9xRdAos1IkqW4RtDT70MgOwnXMcBx5lE1ziZ1hCxe1crihTjHC CofRs00Dd9H8uPhhAU5kDze6LH3p17rn6J6+ALrgGFL1eEb1P1ujDALqd6rH0YMuEm9ovt qf24CztAdNwf62XsBt8pHpsiegEQ2l8MIImi76hY9/SFEQGrT8p2Lw9MvXxiyg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1769818696; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=mlHC5Oc/wPfJ31HEj1ju7nH9g6ibBIbC1zhAHaSBltU=; b=TieKVLxDFry2I7eQ2ZirgZg2/j3QMYO14gnjk5OkvEIt8hx5YOY56VaelO+nFoOyISsqJR ExoD2DevqKlo8JCA== From: "tip-bot2 for Vivian Wang" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: irq/msi] ALSA: hda/intel: Make MSI address limit based on the device DMA limit Cc: Vivian Wang , Thomas Gleixner , Takashi Iwai , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20260129-pci-msi-addr-mask-v4-4-70da998f2750@iscas.ac.cn> References: <20260129-pci-msi-addr-mask-v4-4-70da998f2750@iscas.ac.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <176981869456.2495410.17840609442257116657.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the irq/msi branch of tip: Commit-ID: cb9b6f9d2be6bda1b0117b147df40f982ce06888 Gitweb: https://git.kernel.org/tip/cb9b6f9d2be6bda1b0117b147df40f982= ce06888 Author: Vivian Wang AuthorDate: Thu, 29 Jan 2026 09:56:09 +08:00 Committer: Thomas Gleixner CommitterDate: Sat, 31 Jan 2026 01:11:48 +01:00 ALSA: hda/intel: Make MSI address limit based on the device DMA limit The hda/intel driver restricts the MSI message address for devices which do not advertise full 64-bit DMA address space support to 32-bit due to the former restrictions of the PCI/MSI code which only allowed either 32-bit or a full 64-bit address range. This does not work on platforms which have a MSI doorbell address above the 32-bit boundary but do not support the full 64 bit address range. The PCI/MSI core converted this binary decision to a DMA_BIT_MASK() based decision, which allows to describe the device limitations precisely. Convert the driver to provide the exact DMA address limitations to the PCI/MSI core. That allows devices which do not support the full 64-bit address space to work on platforms which have a MSI doorbell address above the 32-bit limit as long as it is within the hardware's addressable range. [ tglx: Massage changelog ] Signed-off-by: Vivian Wang Signed-off-by: Thomas Gleixner Acked-by: Takashi Iwai Link: https://patch.msgid.link/20260129-pci-msi-addr-mask-v4-4-70da998f2750= @iscas.ac.cn --- sound/hda/controllers/intel.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/sound/hda/controllers/intel.c b/sound/hda/controllers/intel.c index c9542eb..a44de23 100644 --- a/sound/hda/controllers/intel.c +++ b/sound/hda/controllers/intel.c @@ -1903,11 +1903,6 @@ static int azx_first_init(struct azx *chip) chip->gts_present =3D true; #endif =20 - if (chip->msi && chip->driver_caps & AZX_DCAPS_NO_MSI64) { - dev_dbg(card->dev, "Disabling 64bit MSI\n"); - pci->msi_addr_mask =3D DMA_BIT_MASK(32); - } - pci_set_master(pci); =20 gcap =3D azx_readw(chip, GCAP); @@ -1958,6 +1953,11 @@ static int azx_first_init(struct azx *chip) dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(32)); dma_set_max_seg_size(&pci->dev, UINT_MAX); =20 + if (chip->msi && chip->driver_caps & AZX_DCAPS_NO_MSI64) { + dev_dbg(card->dev, "Restricting MSI to %u-bit\n", dma_bits); + pci->msi_addr_mask =3D DMA_BIT_MASK(dma_bits); + } + /* read number of streams from GCAP register instead of using * hardcoded value */