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Tue, 13 Jan 2026 23:48:20 -0800 From: Tariq Toukan To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , , , , Gal Pressman , William Tu , Subject: [PATCH net-next V2 1/4] net/mlx5e: Move async ICOSQ lock into ICOSQ struct Date: Wed, 14 Jan 2026 09:46:37 +0200 Message-ID: <1768376800-1607672-2-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1768376800-1607672-1-git-send-email-tariqt@nvidia.com> References: <1768376800-1607672-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH3PEPF0000000A:EE_|CH3PR12MB9316:EE_ X-MS-Office365-Filtering-Correlation-Id: ac57712e-a7a9-4bde-2d59-08de5341523b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|7416014|376014|36860700013|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?Do3xe4LrOFCi1uYv8iXwKSjHOHfEgCmZKBPLAhfCTP914o+y6Mgi1W0xbLA8?= =?us-ascii?Q?RuGdmbixeOmXCrUAXe7wwTFC1PpkaGaQYCPrLEOcq4uNyId652Vl7A5I+PXR?= =?us-ascii?Q?HzaNcHDSdJbU/mKZaw71CoQliZGPrivz8Uti+wC8SqHqtJb87q/o4U5fKQtp?= =?us-ascii?Q?EJTq68ItacVlvepi6c4C693+SGwNUKQL+43HdFVQd5DTeJBogr135tXIKwrg?= =?us-ascii?Q?m+hhD1/lyZWUZRL28DoRQNemSgwcRHYb1VcMsGBIQKdXr36XPb2ARCh3oK8A?= =?us-ascii?Q?l7Ew42YNrO/JIXYsbHV2XrKiyCRWchjCPXUWjT9EvYHjcbRM+h6W14Pb4Mfs?= =?us-ascii?Q?rDxJ2iShf8IqB+VehnsXQemT761qriOYhSdfTeaV0Japt0tVs20cGCrXqpr2?= =?us-ascii?Q?Z/w3gdor50wjk1b5WpZwD5rtkUczTOxUepYoBcFMxQcA1W9YbdZHeDCFkov2?= =?us-ascii?Q?Z6+UhGVwgnWsUOmtdpO6sF28994jy3+d/KTdifX/i54fDph3Rblrym0CT/vZ?= =?us-ascii?Q?129JvcMmBG8Qe0YMWe4+lO4SOVZlUiO++5Zsf+RNPpKKJ8rEHAPwV9nTL9+D?= =?us-ascii?Q?MyDvWDKoeYChiEioWHcUIaZG6XjqpydIqMElMnG+1qrDEZCbx/iO7+9hPDkC?= =?us-ascii?Q?C7QtZwfpR3topElmnVXgVqKCZTjVy7x5Z+z9zj9oGFbaEp3tge2nvEdFiSeh?= =?us-ascii?Q?Xjv4neNukgABp/so0UU0eujayXHr57JkZGRiDkEEqy1tcnZuQXQSpZdExxLn?= =?us-ascii?Q?pb0dMzHyltDV9ft1ZZxvx2XwILWrYyCKvBLZqBUnvWTbbyd7SnCzRmy6TqU5?= =?us-ascii?Q?+dXcat/kjWekVOdblc/0uNqam+ntXD+sVi34VZRjU4DPgYP3HQTBzjJ/Zq/j?= =?us-ascii?Q?+Vh4jsXZNnc/WTzHQfhcs8NDLvM3hKWIYtEPliiKX2BBjx0IDXqdc8h3iQlB?= =?us-ascii?Q?SN+euD/Km4Ah8h2Py9UUVA0PTKOpMkgHhcDgCgx0Rsjigj3n8QPcnqXAl8FO?= =?us-ascii?Q?mRcnnWCBZInxmVcnMqJ1HP+BqwWkenZJyQDVpcDQ1ai4dQEKxAPx9onFc9SX?= =?us-ascii?Q?2JllVZV9uFAFDQd3HTGzz2ksaMvwXSTwthjMiuMKyrhQNp2dYtPG3freoKXx?= =?us-ascii?Q?19TEhhUDFeC5Cif0H0kPSEmXYwRMj7EE9RgVrhbVRoqZXGpZ9fSf2oVeUUSu?= =?us-ascii?Q?p6uLOHXlGNhPLQMdgY3I4WZndBD4vcVGCfysGPgrEM5IIxPV+5oWKUTWlvNr?= =?us-ascii?Q?qUbwgkJNWQrn37bpY9CpfsmCIY1KvkMEKpGpgjCrHDXUV3BExPxChV1wMLfD?= =?us-ascii?Q?ahHi0GMSrg+hgkTSCPuRxOr1ZzH0Xu/fa0glPMZ2FcGx6DLrecYjCSoqmqDN?= =?us-ascii?Q?zvCdmOuja3Qr6KGU83cWiJUzwFAsbsCKSj9OfQwDvDpoVqH8gweKKv0STNk7?= =?us-ascii?Q?4y/WjpEz6tQ6MQ2EuF9C/p+1K08BqituYccykXRdKMw2+im/vieyTTXWZtq+?= =?us-ascii?Q?C9HL7xxMGXk5eI3rK95K7bqk6F2j4jnHPNy2fa1frviFOxjCmJb/Fmk3O+C1?= =?us-ascii?Q?ikHVLPm0UAAqQ9EFH+I=3D?= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(7416014)(376014)(36860700013)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Jan 2026 07:48:34.9542 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ac57712e-a7a9-4bde-2d59-08de5341523b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH3PEPF0000000A.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB9316 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: William Tu Move the async_icosq spinlock from the mlx5e_channel structure into the mlx5e_icosq structure itself for better encapsulation and for later patch to also use it for other icosq use cases. Changes: - Add spinlock_t lock field to struct mlx5e_icosq - Remove async_icosq_lock field from struct mlx5e_channel - Initialize the new lock in mlx5e_open_icosq() - Update all lock usage in ktls_rx.c and en_main.c to use sq->lock instead of c->async_icosq_lock Signed-off-by: William Tu Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/en.h | 4 ++-- .../mellanox/mlx5/core/en_accel/ktls_rx.c | 18 +++++++++--------- .../net/ethernet/mellanox/mlx5/core/en_main.c | 12 +++++++----- 3 files changed, 18 insertions(+), 16 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en.h b/drivers/net/eth= ernet/mellanox/mlx5/core/en.h index 262dc032e276..ebd3b90e17fd 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en.h @@ -545,6 +545,8 @@ struct mlx5e_icosq { u32 sqn; u16 reserved_room; unsigned long state; + /* icosq can be accessed from any CPU - the spinlock protects it. */ + spinlock_t lock; struct mlx5e_ktls_resync_resp *ktls_resync; =20 /* control path */ @@ -777,8 +779,6 @@ struct mlx5e_channel { =20 /* Async ICOSQ */ struct mlx5e_icosq async_icosq; - /* async_icosq can be accessed from any CPU - the spinlock protects it. */ - spinlock_t async_icosq_lock; =20 /* data path - accessed per napi poll */ const struct cpumask *aff_mask; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ktls_rx.c b/d= rivers/net/ethernet/mellanox/mlx5/core/en_accel/ktls_rx.c index da2d1eb52c13..8bc8231f521f 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ktls_rx.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ktls_rx.c @@ -203,7 +203,7 @@ static int post_rx_param_wqes(struct mlx5e_channel *c, =20 err =3D 0; sq =3D &c->async_icosq; - spin_lock_bh(&c->async_icosq_lock); + spin_lock_bh(&sq->lock); =20 cseg =3D post_static_params(sq, priv_rx); if (IS_ERR(cseg)) @@ -214,7 +214,7 @@ static int post_rx_param_wqes(struct mlx5e_channel *c, =20 mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, cseg); unlock: - spin_unlock_bh(&c->async_icosq_lock); + spin_unlock_bh(&sq->lock); =20 return err; =20 @@ -277,10 +277,10 @@ resync_post_get_progress_params(struct mlx5e_icosq *s= q, =20 buf->priv_rx =3D priv_rx; =20 - spin_lock_bh(&sq->channel->async_icosq_lock); + spin_lock_bh(&sq->lock); =20 if (unlikely(!mlx5e_icosq_can_post_wqe(sq, MLX5E_KTLS_GET_PROGRESS_WQEBBS= ))) { - spin_unlock_bh(&sq->channel->async_icosq_lock); + spin_unlock_bh(&sq->lock); err =3D -ENOSPC; goto err_dma_unmap; } @@ -311,7 +311,7 @@ resync_post_get_progress_params(struct mlx5e_icosq *sq, icosq_fill_wi(sq, pi, &wi); sq->pc++; mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, cseg); - spin_unlock_bh(&sq->channel->async_icosq_lock); + spin_unlock_bh(&sq->lock); =20 return 0; =20 @@ -413,9 +413,9 @@ static void resync_handle_seq_match(struct mlx5e_ktls_o= ffload_context_rx *priv_r return; =20 if (!napi_if_scheduled_mark_missed(&c->napi)) { - spin_lock_bh(&c->async_icosq_lock); + spin_lock_bh(&sq->lock); mlx5e_trigger_irq(sq); - spin_unlock_bh(&c->async_icosq_lock); + spin_unlock_bh(&sq->lock); } } =20 @@ -772,7 +772,7 @@ bool mlx5e_ktls_rx_handle_resync_list(struct mlx5e_chan= nel *c, int budget) clear_bit(MLX5E_SQ_STATE_PENDING_TLS_RX_RESYNC, &sq->state); spin_unlock(&ktls_resync->lock); =20 - spin_lock(&c->async_icosq_lock); + spin_lock(&sq->lock); for (j =3D 0; j < i; j++) { struct mlx5_wqe_ctrl_seg *cseg; =20 @@ -791,7 +791,7 @@ bool mlx5e_ktls_rx_handle_resync_list(struct mlx5e_chan= nel *c, int budget) } if (db_cseg) mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, db_cseg); - spin_unlock(&c->async_icosq_lock); + spin_unlock(&sq->lock); =20 priv_rx->rq_stats->tls_resync_res_ok +=3D j; =20 diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/en_main.c index 3ac47df83ac8..e666d9cc1817 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c @@ -2075,6 +2075,8 @@ static int mlx5e_open_icosq(struct mlx5e_channel *c, = struct mlx5e_params *params if (err) goto err_free_icosq; =20 + spin_lock_init(&sq->lock); + if (param->is_tls) { sq->ktls_resync =3D mlx5e_ktls_rx_resync_create_resp_list(); if (IS_ERR(sq->ktls_resync)) { @@ -2630,8 +2632,6 @@ static int mlx5e_open_queues(struct mlx5e_channel *c, if (err) goto err_close_rx_cq; =20 - spin_lock_init(&c->async_icosq_lock); - err =3D mlx5e_open_icosq(c, params, &cparam->async_icosq, &c->async_icosq, mlx5e_async_icosq_err_cqe_work); if (err) @@ -2750,9 +2750,11 @@ static int mlx5e_channel_stats_alloc(struct mlx5e_pr= iv *priv, int ix, int cpu) =20 void mlx5e_trigger_napi_icosq(struct mlx5e_channel *c) { - spin_lock_bh(&c->async_icosq_lock); - mlx5e_trigger_irq(&c->async_icosq); - spin_unlock_bh(&c->async_icosq_lock); + struct mlx5e_icosq *async_icosq =3D &c->async_icosq; + + spin_lock_bh(&async_icosq->lock); + mlx5e_trigger_irq(async_icosq); + spin_unlock_bh(&async_icosq->lock); } =20 void mlx5e_trigger_napi_sched(struct napi_struct *napi) --=20 2.31.1