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Tue, 13 Jan 2026 23:48:20 -0800 From: Tariq Toukan To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , , , , Gal Pressman , William Tu , Subject: [PATCH net-next V2 1/4] net/mlx5e: Move async ICOSQ lock into ICOSQ struct Date: Wed, 14 Jan 2026 09:46:37 +0200 Message-ID: <1768376800-1607672-2-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1768376800-1607672-1-git-send-email-tariqt@nvidia.com> References: <1768376800-1607672-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH3PEPF0000000A:EE_|CH3PR12MB9316:EE_ X-MS-Office365-Filtering-Correlation-Id: ac57712e-a7a9-4bde-2d59-08de5341523b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|7416014|376014|36860700013|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?Do3xe4LrOFCi1uYv8iXwKSjHOHfEgCmZKBPLAhfCTP914o+y6Mgi1W0xbLA8?= =?us-ascii?Q?RuGdmbixeOmXCrUAXe7wwTFC1PpkaGaQYCPrLEOcq4uNyId652Vl7A5I+PXR?= =?us-ascii?Q?HzaNcHDSdJbU/mKZaw71CoQliZGPrivz8Uti+wC8SqHqtJb87q/o4U5fKQtp?= =?us-ascii?Q?EJTq68ItacVlvepi6c4C693+SGwNUKQL+43HdFVQd5DTeJBogr135tXIKwrg?= =?us-ascii?Q?m+hhD1/lyZWUZRL28DoRQNemSgwcRHYb1VcMsGBIQKdXr36XPb2ARCh3oK8A?= =?us-ascii?Q?l7Ew42YNrO/JIXYsbHV2XrKiyCRWchjCPXUWjT9EvYHjcbRM+h6W14Pb4Mfs?= =?us-ascii?Q?rDxJ2iShf8IqB+VehnsXQemT761qriOYhSdfTeaV0Japt0tVs20cGCrXqpr2?= =?us-ascii?Q?Z/w3gdor50wjk1b5WpZwD5rtkUczTOxUepYoBcFMxQcA1W9YbdZHeDCFkov2?= =?us-ascii?Q?Z6+UhGVwgnWsUOmtdpO6sF28994jy3+d/KTdifX/i54fDph3Rblrym0CT/vZ?= =?us-ascii?Q?129JvcMmBG8Qe0YMWe4+lO4SOVZlUiO++5Zsf+RNPpKKJ8rEHAPwV9nTL9+D?= =?us-ascii?Q?MyDvWDKoeYChiEioWHcUIaZG6XjqpydIqMElMnG+1qrDEZCbx/iO7+9hPDkC?= =?us-ascii?Q?C7QtZwfpR3topElmnVXgVqKCZTjVy7x5Z+z9zj9oGFbaEp3tge2nvEdFiSeh?= =?us-ascii?Q?Xjv4neNukgABp/so0UU0eujayXHr57JkZGRiDkEEqy1tcnZuQXQSpZdExxLn?= =?us-ascii?Q?pb0dMzHyltDV9ft1ZZxvx2XwILWrYyCKvBLZqBUnvWTbbyd7SnCzRmy6TqU5?= =?us-ascii?Q?+dXcat/kjWekVOdblc/0uNqam+ntXD+sVi34VZRjU4DPgYP3HQTBzjJ/Zq/j?= =?us-ascii?Q?+Vh4jsXZNnc/WTzHQfhcs8NDLvM3hKWIYtEPliiKX2BBjx0IDXqdc8h3iQlB?= =?us-ascii?Q?SN+euD/Km4Ah8h2Py9UUVA0PTKOpMkgHhcDgCgx0Rsjigj3n8QPcnqXAl8FO?= =?us-ascii?Q?mRcnnWCBZInxmVcnMqJ1HP+BqwWkenZJyQDVpcDQ1ai4dQEKxAPx9onFc9SX?= =?us-ascii?Q?2JllVZV9uFAFDQd3HTGzz2ksaMvwXSTwthjMiuMKyrhQNp2dYtPG3freoKXx?= =?us-ascii?Q?19TEhhUDFeC5Cif0H0kPSEmXYwRMj7EE9RgVrhbVRoqZXGpZ9fSf2oVeUUSu?= =?us-ascii?Q?p6uLOHXlGNhPLQMdgY3I4WZndBD4vcVGCfysGPgrEM5IIxPV+5oWKUTWlvNr?= =?us-ascii?Q?qUbwgkJNWQrn37bpY9CpfsmCIY1KvkMEKpGpgjCrHDXUV3BExPxChV1wMLfD?= =?us-ascii?Q?ahHi0GMSrg+hgkTSCPuRxOr1ZzH0Xu/fa0glPMZ2FcGx6DLrecYjCSoqmqDN?= =?us-ascii?Q?zvCdmOuja3Qr6KGU83cWiJUzwFAsbsCKSj9OfQwDvDpoVqH8gweKKv0STNk7?= =?us-ascii?Q?4y/WjpEz6tQ6MQ2EuF9C/p+1K08BqituYccykXRdKMw2+im/vieyTTXWZtq+?= =?us-ascii?Q?C9HL7xxMGXk5eI3rK95K7bqk6F2j4jnHPNy2fa1frviFOxjCmJb/Fmk3O+C1?= =?us-ascii?Q?ikHVLPm0UAAqQ9EFH+I=3D?= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(7416014)(376014)(36860700013)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Jan 2026 07:48:34.9542 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ac57712e-a7a9-4bde-2d59-08de5341523b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH3PEPF0000000A.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB9316 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: William Tu Move the async_icosq spinlock from the mlx5e_channel structure into the mlx5e_icosq structure itself for better encapsulation and for later patch to also use it for other icosq use cases. Changes: - Add spinlock_t lock field to struct mlx5e_icosq - Remove async_icosq_lock field from struct mlx5e_channel - Initialize the new lock in mlx5e_open_icosq() - Update all lock usage in ktls_rx.c and en_main.c to use sq->lock instead of c->async_icosq_lock Signed-off-by: William Tu Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/en.h | 4 ++-- .../mellanox/mlx5/core/en_accel/ktls_rx.c | 18 +++++++++--------- .../net/ethernet/mellanox/mlx5/core/en_main.c | 12 +++++++----- 3 files changed, 18 insertions(+), 16 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en.h b/drivers/net/eth= ernet/mellanox/mlx5/core/en.h index 262dc032e276..ebd3b90e17fd 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en.h @@ -545,6 +545,8 @@ struct mlx5e_icosq { u32 sqn; u16 reserved_room; unsigned long state; + /* icosq can be accessed from any CPU - the spinlock protects it. */ + spinlock_t lock; struct mlx5e_ktls_resync_resp *ktls_resync; =20 /* control path */ @@ -777,8 +779,6 @@ struct mlx5e_channel { =20 /* Async ICOSQ */ struct mlx5e_icosq async_icosq; - /* async_icosq can be accessed from any CPU - the spinlock protects it. */ - spinlock_t async_icosq_lock; =20 /* data path - accessed per napi poll */ const struct cpumask *aff_mask; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ktls_rx.c b/d= rivers/net/ethernet/mellanox/mlx5/core/en_accel/ktls_rx.c index da2d1eb52c13..8bc8231f521f 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ktls_rx.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ktls_rx.c @@ -203,7 +203,7 @@ static int post_rx_param_wqes(struct mlx5e_channel *c, =20 err =3D 0; sq =3D &c->async_icosq; - spin_lock_bh(&c->async_icosq_lock); + spin_lock_bh(&sq->lock); =20 cseg =3D post_static_params(sq, priv_rx); if (IS_ERR(cseg)) @@ -214,7 +214,7 @@ static int post_rx_param_wqes(struct mlx5e_channel *c, =20 mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, cseg); unlock: - spin_unlock_bh(&c->async_icosq_lock); + spin_unlock_bh(&sq->lock); =20 return err; =20 @@ -277,10 +277,10 @@ resync_post_get_progress_params(struct mlx5e_icosq *s= q, =20 buf->priv_rx =3D priv_rx; =20 - spin_lock_bh(&sq->channel->async_icosq_lock); + spin_lock_bh(&sq->lock); =20 if (unlikely(!mlx5e_icosq_can_post_wqe(sq, MLX5E_KTLS_GET_PROGRESS_WQEBBS= ))) { - spin_unlock_bh(&sq->channel->async_icosq_lock); + spin_unlock_bh(&sq->lock); err =3D -ENOSPC; goto err_dma_unmap; } @@ -311,7 +311,7 @@ resync_post_get_progress_params(struct mlx5e_icosq *sq, icosq_fill_wi(sq, pi, &wi); sq->pc++; mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, cseg); - spin_unlock_bh(&sq->channel->async_icosq_lock); + spin_unlock_bh(&sq->lock); =20 return 0; =20 @@ -413,9 +413,9 @@ static void resync_handle_seq_match(struct mlx5e_ktls_o= ffload_context_rx *priv_r return; =20 if (!napi_if_scheduled_mark_missed(&c->napi)) { - spin_lock_bh(&c->async_icosq_lock); + spin_lock_bh(&sq->lock); mlx5e_trigger_irq(sq); - spin_unlock_bh(&c->async_icosq_lock); + spin_unlock_bh(&sq->lock); } } =20 @@ -772,7 +772,7 @@ bool mlx5e_ktls_rx_handle_resync_list(struct mlx5e_chan= nel *c, int budget) clear_bit(MLX5E_SQ_STATE_PENDING_TLS_RX_RESYNC, &sq->state); spin_unlock(&ktls_resync->lock); =20 - spin_lock(&c->async_icosq_lock); + spin_lock(&sq->lock); for (j =3D 0; j < i; j++) { struct mlx5_wqe_ctrl_seg *cseg; =20 @@ -791,7 +791,7 @@ bool mlx5e_ktls_rx_handle_resync_list(struct mlx5e_chan= nel *c, int budget) } if (db_cseg) mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, db_cseg); - spin_unlock(&c->async_icosq_lock); + spin_unlock(&sq->lock); =20 priv_rx->rq_stats->tls_resync_res_ok +=3D j; =20 diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/en_main.c index 3ac47df83ac8..e666d9cc1817 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c @@ -2075,6 +2075,8 @@ static int mlx5e_open_icosq(struct mlx5e_channel *c, = struct mlx5e_params *params if (err) goto err_free_icosq; =20 + spin_lock_init(&sq->lock); + if (param->is_tls) { sq->ktls_resync =3D mlx5e_ktls_rx_resync_create_resp_list(); if (IS_ERR(sq->ktls_resync)) { @@ -2630,8 +2632,6 @@ static int mlx5e_open_queues(struct mlx5e_channel *c, if (err) goto err_close_rx_cq; =20 - spin_lock_init(&c->async_icosq_lock); - err =3D mlx5e_open_icosq(c, params, &cparam->async_icosq, &c->async_icosq, mlx5e_async_icosq_err_cqe_work); if (err) @@ -2750,9 +2750,11 @@ static int mlx5e_channel_stats_alloc(struct mlx5e_pr= iv *priv, int ix, int cpu) =20 void mlx5e_trigger_napi_icosq(struct mlx5e_channel *c) { - spin_lock_bh(&c->async_icosq_lock); - mlx5e_trigger_irq(&c->async_icosq); - spin_unlock_bh(&c->async_icosq_lock); + struct mlx5e_icosq *async_icosq =3D &c->async_icosq; + + spin_lock_bh(&async_icosq->lock); + mlx5e_trigger_irq(async_icosq); + spin_unlock_bh(&async_icosq->lock); } =20 void mlx5e_trigger_napi_sched(struct napi_struct *napi) --=20 2.31.1 From nobody Sun Feb 8 02:56:25 2026 Received: from SN4PR0501CU005.outbound.protection.outlook.com (mail-southcentralusazon11011014.outbound.protection.outlook.com [40.93.194.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0C43037998F; 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Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , , , , Gal Pressman , William Tu , Subject: [PATCH net-next V2 2/4] net/mlx5e: Use regular ICOSQ for triggering NAPI Date: Wed, 14 Jan 2026 09:46:38 +0200 Message-ID: <1768376800-1607672-3-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1768376800-1607672-1-git-send-email-tariqt@nvidia.com> References: <1768376800-1607672-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF000015C9:EE_|MN0PR12MB5930:EE_ X-MS-Office365-Filtering-Correlation-Id: 47b783f4-18df-41d6-c5ef-08de53415656 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|82310400026|36860700013|1800799024|376014; X-Microsoft-Antispam-Message-Info: =?utf-8?B?OGFLbklsZHlEcGtOZ0lxd0V5UHRabVZKbjZ6ZzN4SzRnVkt5eUcxclUwaVIw?= =?utf-8?B?V3NTWXFMUjZORnBXWC8rOCtUcG5pZS9SUEtaeDdydGVCak8yUWNKZWpGTDlO?= =?utf-8?B?QTMxYTZ0cTN0TERiT21nQmdoWGFqOEdpWVo2NzA2NHBQbXRtaFV0VTluMDJz?= =?utf-8?B?YldSeS9VZ1RsNzdKclNjU1UwSWUwZTdhQTNjK1dOMUtZcFNZZllTVS8yMnZS?= =?utf-8?B?ZmJqRjJ3enJZOXZFSWtYcnBidVpkcFVuUWg5S1lZWFdSUnRXZ1JiU3RrUDBk?= =?utf-8?B?a3RpdW1yVVpuc0Z4aUUzUjFCc3drUUdPZmd0b2d3ZnJ5L2xldzUvZkloOUFP?= =?utf-8?B?OGtRMG5mZmJWZ3BrbHVxQVBHVW9PSWNaczlpTWZULzdZazUwZ245Q3ZuS3BF?= =?utf-8?B?S2FTUDUrUE1BWWwxVmwzWElSRG5hOWNJakc2TUxjeGcxWDZTTThmU0RtYkJU?= =?utf-8?B?Ni9lYTl6Um9VN1l0MFgraVE2TEZ2YXZlZzFTVE9md3RoeW4wMmxVUUtheDBY?= =?utf-8?B?QnFvdWRCdFRaSjNoMmpTUisvdTMvUjdNZlJtTFVxdVMyYldXcnhlTnlZMnhU?= =?utf-8?B?ZkFaQnFHSlRkeDJVQktSaWZWSHNNNU9mWDcrTkwwNUFRelAvdEthYUloOUFl?= =?utf-8?B?UDFRZUlTRTUwaEEzZnRiU2FWZmNBdGtvSHJHMnBBV0RKQk43R0N3SUk2ZWR1?= =?utf-8?B?a0pJenJNM2ZMejBVQVF2amh2TjBSYUU5UWp6dmRVdEVBQ0hxRzJCdzAxVEZW?= =?utf-8?B?QWY3dWVkN0NlUHV3NTI0NEpSTlJ0WTBGMVc3aXczVGc1NlFLY25oK0xtaUJG?= =?utf-8?B?UFppbnZPVENaL0FRSTdjQ1R3UjdTYjlyYTl3cU9qNFFEU1FwU3FNSkhHb0Zh?= =?utf-8?B?VXZTb3NwbktmaElUOGlKUWNjeWNpTW5WOE1mSnl1Nng0aGkySERjSVlvRVQ3?= =?utf-8?B?VkQyMURyNi96bUdjbEp6eFA2bFg4a2VROXBkRkN5cjlJSEJ0SnhtUHB2dm50?= =?utf-8?B?ZklvYXNGS2NTLyt3RHByNjdrQjJqSTZqVk4vRVd5OWpRajJ6Z0hCb3UyNDAv?= =?utf-8?B?dU5CMHFram5HNXQ5NURLejRUdDdaajN4WkovTmI3WUl5dTlyZkRRYkQ0azZz?= =?utf-8?B?OU00RjRFSkVUOFFBL3Z1Z2JzeXVrZTdxSjRKYms3d2hiZHRvVy9Ta0dURFEw?= =?utf-8?B?a2JQTlhsNTRJQ1UzM0tCK0k5dVJjOGVtT0N1amxRY0I2cEVWUzJDMUJ1TitY?= =?utf-8?B?dU9xeWpkR3VZMkJIS05venJYUEtEd3pCamFFVHMvVjNtNnFDZk5WcFVQeDA3?= =?utf-8?B?a1QvMkp1bTFrdGhNR0ZneU4yRWUzT2RnV25CK2g0c3ZtUDQ5N094K1NqZ3p4?= =?utf-8?B?UUlQOXM2TFhZZlVScGlRMDdmR1BPK3JBUXdQMzdkeHdrN0YremhxZTFwR21j?= =?utf-8?B?ZUE0a2g3YjZJbUFWenBoUUp0QUR0YlY4REFhSlJpcU8rbVJXbisrR1hHS2p1?= =?utf-8?B?YUh1ZkpraU5hVlhXaFMwRzUzelJ5SlN6U2t3bmVBMWg3UXB4TExNZE5BRE8z?= =?utf-8?B?eWdBMW5ySVJUU2IvZlRiRkluWWNWSWpxZklQNXJMUThIZTVXUUV5T04yOWUw?= =?utf-8?B?d2FXOXY3dzlRR2Y5RXgwZTFLNFdldnoyYzJIQ2l2U2o5Ly9vbnQxTVRVMnRJ?= =?utf-8?B?b3lQOWNrb3BDWnh0TmJzc05CWWJjZnNjR0JzMVRSa0Z5QnhFRGRCNkhkSVB2?= =?utf-8?B?NnRhRDJIWWQwS01uOUZLNjBvQkJNeTJ6aHlUczZnbU1ETnBySG9DbityRCt5?= =?utf-8?B?Sm42YVhZYVZDS0QvN3ZJQW9LNkYrYTc2R0NDRFdYZFQzRjlrUXhaZUJuOE9t?= =?utf-8?B?c1lIampDMjI0NmU4MmRwZ1l4SkxzM2tZVFdLdHF5cVVjQUlPT3R5YTRnRUw3?= =?utf-8?B?aDdzODZqL3BZMjBJS3RSZlBMZ1BMQWgwUDdXS1JqZEtCOHEvbk9FYWR1aUlD?= =?utf-8?B?TjRDaWY5VnNUd1ZISFo3QUI0eVVVaHRWWkRnZEVtS1RvWXVyYXBWVEVTUzlr?= =?utf-8?B?SloyemZYSGhGUnpFUHNESUJvT01Zb200ZDVsNWpzZEZBNG5rSWYrZGJ3V3FK?= =?utf-8?Q?HCIg=3D?= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(7416014)(82310400026)(36860700013)(1800799024)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Jan 2026 07:48:41.8449 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 47b783f4-18df-41d6-c5ef-08de53415656 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF000015C9.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB5930 From: William Tu Before the cited commit, ICOSQ is used to post NOP WQE to trigger hardware interrupt and start NAPI, but this mechanism suffers from a race condition: mlx5e_alloc_rx_mpwqe may post UMR WQEs to ICOSQ _before_ NOP WQE is posted. The cited commit fixes the issue by replacing ICOSQ with async ICOSQ, as a new way to post the NOP WQE to trigger the hardware interrupt and NAPI. The patch changes it back by replacing async ICOSQ with regular ICOSQ, for the purpose of saving memory in later patches, and solves the issue by adding a new SQ state, MLX5E_SQ_STATE_LOCK_NEEDED for syncing the start of NAPI. What it does: - Switch trigger path from async ICOSQ to regular ICOSQ to reduce need for async SQ. - Introduce MLX5E_SQ_STATE_LOCK_NEEDED and mlx5e_icosq_sync_lock(), unlock() to prevent the race where UMR WQEs could be posted before the NOP WQE used to trigger NAPI. - Use synchronize_net() once per trigger cycle to quiesce in-flight softirqs before serializing the NOP WQE and any UMR postings via the ICOSQ lock. - Wrap ICOSQ UMR posting in en_rx.c and xsk/rx.c with the new conditional lock. The conditional locking approach is critical for performance: always locking would impose unnecessary overhead. Synchronization is not needed between regular NAPI cycles once the channel is activated and running. The lock is only required to protect against the race during channel activation=E2=80=94specifically, when the very first NOP WQE is posted to t= rigger NAPI. After that initial trigger, normal NAPI polling handles subsequent work without contention. The MLX5E_SQ_STATE_LOCK_NEEDED flag ensures we pay the synchronization cost only when necessary. Signed-off-by: William Tu Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/en.h | 21 ++++++++++++++++++- .../mellanox/mlx5/core/en/reporter_tx.c | 1 + .../ethernet/mellanox/mlx5/core/en/xsk/rx.c | 3 +++ .../net/ethernet/mellanox/mlx5/core/en_main.c | 13 ++++++++---- .../net/ethernet/mellanox/mlx5/core/en_rx.c | 4 ++++ 5 files changed, 37 insertions(+), 5 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en.h b/drivers/net/eth= ernet/mellanox/mlx5/core/en.h index ebd3b90e17fd..83cfa3983855 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en.h @@ -388,6 +388,7 @@ enum { MLX5E_SQ_STATE_DIM, MLX5E_SQ_STATE_PENDING_XSK_TX, MLX5E_SQ_STATE_PENDING_TLS_RX_RESYNC, + MLX5E_SQ_STATE_LOCK_NEEDED, MLX5E_NUM_SQ_STATES, /* Must be kept last */ }; =20 @@ -545,7 +546,10 @@ struct mlx5e_icosq { u32 sqn; u16 reserved_room; unsigned long state; - /* icosq can be accessed from any CPU - the spinlock protects it. */ + /* icosq can be accessed from any CPU and from different contexts + * (NAPI softirq or process/workqueue). Always use spin_lock_bh for + * simplicity and correctness across all contexts. + */ spinlock_t lock; struct mlx5e_ktls_resync_resp *ktls_resync; =20 @@ -801,6 +805,21 @@ struct mlx5e_channel { struct dim_cq_moder tx_cq_moder; }; =20 +static inline bool mlx5e_icosq_sync_lock(struct mlx5e_icosq *sq) +{ + if (likely(!test_bit(MLX5E_SQ_STATE_LOCK_NEEDED, &sq->state))) + return false; + + spin_lock_bh(&sq->lock); + return true; +} + +static inline void mlx5e_icosq_sync_unlock(struct mlx5e_icosq *sq, bool lo= cked) +{ + if (unlikely(locked)) + spin_unlock_bh(&sq->lock); +} + struct mlx5e_ptp; =20 struct mlx5e_channels { diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/reporter_tx.c b/dri= vers/net/ethernet/mellanox/mlx5/core/en/reporter_tx.c index 9e2cf191ed30..4adc1adf9897 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/reporter_tx.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/reporter_tx.c @@ -15,6 +15,7 @@ static const char * const sq_sw_state_type_name[] =3D { [MLX5E_SQ_STATE_DIM] =3D "dim", [MLX5E_SQ_STATE_PENDING_XSK_TX] =3D "pending_xsk_tx", [MLX5E_SQ_STATE_PENDING_TLS_RX_RESYNC] =3D "pending_tls_rx_resync", + [MLX5E_SQ_STATE_LOCK_NEEDED] =3D "lock_needed", }; =20 static int mlx5e_wait_for_sq_flush(struct mlx5e_txqsq *sq) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/xsk/rx.c b/drivers/= net/ethernet/mellanox/mlx5/core/en/xsk/rx.c index 2b05536d564a..4f984f6a2cb9 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/xsk/rx.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/xsk/rx.c @@ -23,6 +23,7 @@ int mlx5e_xsk_alloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix) struct mlx5_wq_cyc *wq =3D &icosq->wq; struct mlx5e_umr_wqe *umr_wqe; struct xdp_buff **xsk_buffs; + bool sync_locked; int batch, i; u32 offset; /* 17-bit value with MTT. */ u16 pi; @@ -47,6 +48,7 @@ int mlx5e_xsk_alloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix) goto err_reuse_batch; } =20 + sync_locked =3D mlx5e_icosq_sync_lock(icosq); pi =3D mlx5e_icosq_get_next_pi(icosq, rq->mpwqe.umr_wqebbs); umr_wqe =3D mlx5_wq_cyc_get_wqe(wq, pi); memcpy(umr_wqe, &rq->mpwqe.umr_wqe, sizeof(struct mlx5e_umr_wqe)); @@ -143,6 +145,7 @@ int mlx5e_xsk_alloc_rx_mpwqe(struct mlx5e_rq *rq, u16 i= x) }; =20 icosq->pc +=3D rq->mpwqe.umr_wqebbs; + mlx5e_icosq_sync_unlock(icosq, sync_locked); =20 icosq->doorbell_cseg =3D &umr_wqe->hdr.ctrl; =20 diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/en_main.c index e666d9cc1817..fdbcc22b6c61 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c @@ -2750,11 +2750,16 @@ static int mlx5e_channel_stats_alloc(struct mlx5e_p= riv *priv, int ix, int cpu) =20 void mlx5e_trigger_napi_icosq(struct mlx5e_channel *c) { - struct mlx5e_icosq *async_icosq =3D &c->async_icosq; + bool locked; =20 - spin_lock_bh(&async_icosq->lock); - mlx5e_trigger_irq(async_icosq); - spin_unlock_bh(&async_icosq->lock); + if (!test_and_set_bit(MLX5E_SQ_STATE_LOCK_NEEDED, &c->icosq.state)) + synchronize_net(); + + locked =3D mlx5e_icosq_sync_lock(&c->icosq); + mlx5e_trigger_irq(&c->icosq); + mlx5e_icosq_sync_unlock(&c->icosq, locked); + + clear_bit(MLX5E_SQ_STATE_LOCK_NEEDED, &c->icosq.state); } =20 void mlx5e_trigger_napi_sched(struct napi_struct *napi) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c b/drivers/net/= ethernet/mellanox/mlx5/core/en_rx.c index 1f6930c77437..1fc3720d2201 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c @@ -778,6 +778,7 @@ static int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, u1= 6 ix) struct mlx5_wq_cyc *wq =3D &sq->wq; struct mlx5e_umr_wqe *umr_wqe; u32 offset; /* 17-bit value with MTT. */ + bool sync_locked; u16 pi; int err; int i; @@ -788,6 +789,7 @@ static int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, u1= 6 ix) goto err; } =20 + sync_locked =3D mlx5e_icosq_sync_lock(sq); pi =3D mlx5e_icosq_get_next_pi(sq, rq->mpwqe.umr_wqebbs); umr_wqe =3D mlx5_wq_cyc_get_wqe(wq, pi); memcpy(umr_wqe, &rq->mpwqe.umr_wqe, sizeof(struct mlx5e_umr_wqe)); @@ -835,12 +837,14 @@ static int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, = u16 ix) }; =20 sq->pc +=3D rq->mpwqe.umr_wqebbs; + mlx5e_icosq_sync_unlock(sq, sync_locked); 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ICO (Internal Communication Operations) is for driver to communicate with the HW, and it's not used for traffic. Currently mlx5 driver has sync and async ICO send queues. The async ICOSQ means that it's not necessarily under NAPI context protection. The patch is in preparation for the later patch to detect its usage and enable it when necessary. Signed-off-by: William Tu Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/en.h | 2 +- .../ethernet/mellanox/mlx5/core/en/xsk/tx.c | 6 +- .../mellanox/mlx5/core/en_accel/ktls_rx.c | 8 +-- .../mellanox/mlx5/core/en_accel/ktls_txrx.h | 3 +- .../net/ethernet/mellanox/mlx5/core/en_main.c | 67 ++++++++++++++----- .../net/ethernet/mellanox/mlx5/core/en_txrx.c | 7 +- 6 files changed, 65 insertions(+), 28 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en.h b/drivers/net/eth= ernet/mellanox/mlx5/core/en.h index 83cfa3983855..a7076b26fd5c 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en.h @@ -782,7 +782,7 @@ struct mlx5e_channel { struct mlx5e_xdpsq xsksq; =20 /* Async ICOSQ */ - struct mlx5e_icosq async_icosq; + struct mlx5e_icosq *async_icosq; =20 /* data path - accessed per napi poll */ const struct cpumask *aff_mask; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/xsk/tx.c b/drivers/= net/ethernet/mellanox/mlx5/core/en/xsk/tx.c index a59199ed590d..9e33156fac8a 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/xsk/tx.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/xsk/tx.c @@ -26,10 +26,12 @@ int mlx5e_xsk_wakeup(struct net_device *dev, u32 qid, u= 32 flags) * active and not polled by NAPI. Return 0, because the upcoming * activate will trigger the IRQ for us. */ - if (unlikely(!test_bit(MLX5E_SQ_STATE_ENABLED, &c->async_icosq.state))) + if (unlikely(!test_bit(MLX5E_SQ_STATE_ENABLED, + &c->async_icosq->state))) return 0; =20 - if (test_and_set_bit(MLX5E_SQ_STATE_PENDING_XSK_TX, &c->async_icosq.stat= e)) + if (test_and_set_bit(MLX5E_SQ_STATE_PENDING_XSK_TX, + &c->async_icosq->state)) return 0; =20 mlx5e_trigger_napi_icosq(c); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ktls_rx.c b/d= rivers/net/ethernet/mellanox/mlx5/core/en_accel/ktls_rx.c index 8bc8231f521f..5d8fe252799e 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ktls_rx.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ktls_rx.c @@ -202,7 +202,7 @@ static int post_rx_param_wqes(struct mlx5e_channel *c, int err; =20 err =3D 0; - sq =3D &c->async_icosq; + sq =3D c->async_icosq; spin_lock_bh(&sq->lock); =20 cseg =3D post_static_params(sq, priv_rx); @@ -344,7 +344,7 @@ static void resync_handle_work(struct work_struct *work) } =20 c =3D resync->priv->channels.c[priv_rx->rxq]; - sq =3D &c->async_icosq; + sq =3D c->async_icosq; =20 if (resync_post_get_progress_params(sq, priv_rx)) { priv_rx->rq_stats->tls_resync_req_skip++; @@ -371,7 +371,7 @@ static void resync_handle_seq_match(struct mlx5e_ktls_o= ffload_context_rx *priv_r struct mlx5e_icosq *sq; bool trigger_poll; =20 - sq =3D &c->async_icosq; + sq =3D c->async_icosq; ktls_resync =3D sq->ktls_resync; trigger_poll =3D false; =20 @@ -753,7 +753,7 @@ bool mlx5e_ktls_rx_handle_resync_list(struct mlx5e_chan= nel *c, int budget) LIST_HEAD(local_list); int i, j; =20 - sq =3D &c->async_icosq; + sq =3D c->async_icosq; =20 if (unlikely(!test_bit(MLX5E_SQ_STATE_ENABLED, &sq->state))) return false; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ktls_txrx.h b= /drivers/net/ethernet/mellanox/mlx5/core/en_accel/ktls_txrx.h index cb08799769ee..4022c7e78a2e 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ktls_txrx.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ktls_txrx.h @@ -50,7 +50,8 @@ bool mlx5e_ktls_rx_handle_resync_list(struct mlx5e_channe= l *c, int budget); static inline bool mlx5e_ktls_rx_pending_resync_list(struct mlx5e_channel *c, int budget) { - return budget && test_bit(MLX5E_SQ_STATE_PENDING_TLS_RX_RESYNC, &c->async= _icosq.state); + return budget && test_bit(MLX5E_SQ_STATE_PENDING_TLS_RX_RESYNC, + &c->async_icosq->state); } =20 static inline void diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/en_main.c index fdbcc22b6c61..aa4ff3963b86 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c @@ -2589,6 +2589,47 @@ static int mlx5e_open_rxq_rq(struct mlx5e_channel *c= , struct mlx5e_params *param return mlx5e_open_rq(params, rq_params, NULL, cpu_to_node(c->cpu), q_coun= ter, &c->rq); } =20 +static struct mlx5e_icosq * +mlx5e_open_async_icosq(struct mlx5e_channel *c, + struct mlx5e_params *params, + struct mlx5e_channel_param *cparam, + struct mlx5e_create_cq_param *ccp) +{ + struct dim_cq_moder icocq_moder =3D {0, 0}; + struct mlx5e_icosq *async_icosq; + int err; + + async_icosq =3D kvzalloc_node(sizeof(*async_icosq), GFP_KERNEL, + cpu_to_node(c->cpu)); + if (!async_icosq) + return ERR_PTR(-ENOMEM); + + err =3D mlx5e_open_cq(c->mdev, icocq_moder, &cparam->async_icosq.cqp, ccp, + &async_icosq->cq); + if (err) + goto err_free_async_icosq; + + err =3D mlx5e_open_icosq(c, params, &cparam->async_icosq, async_icosq, + mlx5e_async_icosq_err_cqe_work); + if (err) + goto err_close_async_icosq_cq; + + return async_icosq; + +err_close_async_icosq_cq: + mlx5e_close_cq(&async_icosq->cq); +err_free_async_icosq: + kvfree(async_icosq); + return ERR_PTR(err); +} + +static void mlx5e_close_async_icosq(struct mlx5e_icosq *async_icosq) +{ + mlx5e_close_icosq(async_icosq); + mlx5e_close_cq(&async_icosq->cq); + kvfree(async_icosq); +} + static int mlx5e_open_queues(struct mlx5e_channel *c, struct mlx5e_params *params, struct mlx5e_channel_param *cparam) @@ -2600,15 +2641,10 @@ static int mlx5e_open_queues(struct mlx5e_channel *= c, =20 mlx5e_build_create_cq_param(&ccp, c); =20 - err =3D mlx5e_open_cq(c->mdev, icocq_moder, &cparam->async_icosq.cqp, &cc= p, - &c->async_icosq.cq); - if (err) - return err; - err =3D mlx5e_open_cq(c->mdev, icocq_moder, &cparam->icosq.cqp, &ccp, &c->icosq.cq); if (err) - goto err_close_async_icosq_cq; + return err; =20 err =3D mlx5e_open_tx_cqs(c, params, &ccp, cparam); if (err) @@ -2632,10 +2668,11 @@ static int mlx5e_open_queues(struct mlx5e_channel *= c, if (err) goto err_close_rx_cq; =20 - err =3D mlx5e_open_icosq(c, params, &cparam->async_icosq, &c->async_icosq, - mlx5e_async_icosq_err_cqe_work); - if (err) + c->async_icosq =3D mlx5e_open_async_icosq(c, params, cparam, &ccp); + if (IS_ERR(c->async_icosq)) { + err =3D PTR_ERR(c->async_icosq); goto err_close_rq_xdpsq_cq; + } =20 mutex_init(&c->icosq_recovery_lock); =20 @@ -2671,7 +2708,7 @@ static int mlx5e_open_queues(struct mlx5e_channel *c, mlx5e_close_icosq(&c->icosq); =20 err_close_async_icosq: - mlx5e_close_icosq(&c->async_icosq); + mlx5e_close_async_icosq(c->async_icosq); =20 err_close_rq_xdpsq_cq: if (c->xdp) @@ -2690,9 +2727,6 @@ static int mlx5e_open_queues(struct mlx5e_channel *c, err_close_icosq_cq: mlx5e_close_cq(&c->icosq.cq); =20 -err_close_async_icosq_cq: - mlx5e_close_cq(&c->async_icosq.cq); - return err; } =20 @@ -2706,7 +2740,7 @@ static void mlx5e_close_queues(struct mlx5e_channel *= c) mlx5e_close_sqs(c); mlx5e_close_icosq(&c->icosq); mutex_destroy(&c->icosq_recovery_lock); - mlx5e_close_icosq(&c->async_icosq); + mlx5e_close_async_icosq(c->async_icosq); if (c->xdp) mlx5e_close_cq(&c->rq_xdpsq.cq); mlx5e_close_cq(&c->rq.cq); @@ -2714,7 +2748,6 @@ static void mlx5e_close_queues(struct mlx5e_channel *= c) mlx5e_close_xdpredirect_sq(c->xdpsq); mlx5e_close_tx_cqs(c); mlx5e_close_cq(&c->icosq.cq); - mlx5e_close_cq(&c->async_icosq.cq); } =20 static u8 mlx5e_enumerate_lag_port(struct mlx5_core_dev *mdev, int ix) @@ -2879,7 +2912,7 @@ static void mlx5e_activate_channel(struct mlx5e_chann= el *c) for (tc =3D 0; tc < c->num_tc; tc++) mlx5e_activate_txqsq(&c->sq[tc]); mlx5e_activate_icosq(&c->icosq); - mlx5e_activate_icosq(&c->async_icosq); + mlx5e_activate_icosq(c->async_icosq); =20 if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state)) mlx5e_activate_xsk(c); @@ -2900,7 +2933,7 @@ static void mlx5e_deactivate_channel(struct mlx5e_cha= nnel *c) else mlx5e_deactivate_rq(&c->rq); =20 - mlx5e_deactivate_icosq(&c->async_icosq); + mlx5e_deactivate_icosq(c->async_icosq); mlx5e_deactivate_icosq(&c->icosq); for (tc =3D 0; tc < c->num_tc; tc++) mlx5e_deactivate_txqsq(&c->sq[tc]); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_txrx.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/en_txrx.c index 76108299ea57..57c54265dbda 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_txrx.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_txrx.c @@ -180,11 +180,12 @@ int mlx5e_napi_poll(struct napi_struct *napi, int bud= get) busy |=3D work_done =3D=3D budget; =20 mlx5e_poll_ico_cq(&c->icosq.cq); - if (mlx5e_poll_ico_cq(&c->async_icosq.cq)) + if (mlx5e_poll_ico_cq(&c->async_icosq->cq)) /* Don't clear the flag if nothing was polled to prevent * queueing more WQEs and overflowing the async ICOSQ. */ - clear_bit(MLX5E_SQ_STATE_PENDING_XSK_TX, &c->async_icosq.state); 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Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , , , , Gal Pressman , William Tu , Subject: [PATCH net-next V2 4/4] net/mlx5e: Conditionally create async ICOSQ Date: Wed, 14 Jan 2026 09:46:40 +0200 Message-ID: <1768376800-1607672-5-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1768376800-1607672-1-git-send-email-tariqt@nvidia.com> References: <1768376800-1607672-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF000015C8:EE_|MW4PR12MB7264:EE_ X-MS-Office365-Filtering-Correlation-Id: ebedcd9b-6962-430f-c605-08de53415b96 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|36860700013|7416014|376014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?779yIG/IYqCsYGbwBYc5uSxYWFsYF57WvmnYEcgLaWnwdWO4YbzsnjYUaDTw?= =?us-ascii?Q?K3Lu1GBLHUKlLLAADqL/Un0pfm2ck6yZ5uREvyHrCH0CftgwIMnpnaqOdMWP?= =?us-ascii?Q?HrN3+ULOf7E8gGYbV2GA9ICm3+tNsql7m0o6XdjY54UtruNcjZSa6K5yLJQq?= =?us-ascii?Q?tGaljgCHbKft4HYtZzLxAty8I0/uVve2KNO9UGu+KSY/KvweM3JQex9+W1ru?= =?us-ascii?Q?N9Nxh7bl+Q0sdXr3DvbLMhfdjc5LH4htHeMBOpoH8pm6tlP64/R5adtM6NuU?= =?us-ascii?Q?qce1fcM5236w8/2U1F3hPQ7YNhldf+c/CSAQ/32mTvajI1gW5b8yzPfqvtNW?= =?us-ascii?Q?X5BGlPeSOQ7TGrWa06l5pFxbe4u18Up+eKxQ5FCXillLpjhd1ZgXx5iS6Y7b?= =?us-ascii?Q?Z7WrWv/F6P+5SmjeWckHOWQrQy8xbSb9X6NCpGYAbLx/2atQsKzI70HYIyG8?= =?us-ascii?Q?IPEgJuQQI3OVOhLpilMatEGA6Z0gwZdHI+TyuFq9iZjM91ZqBm1X8QTrGHfc?= =?us-ascii?Q?AQENjxlP8sUsb4ZBiDYQsv5HE5qh10k/HddBIkqvhGRUJedS2lhdDazpejzy?= =?us-ascii?Q?Y/I0CIIKuwNz+DBZIbhTg8W/JeR551OmZUsCGw4fwwYUcDIXNFGnQmV+p7nS?= =?us-ascii?Q?uy6Tev5S+08M3WtACuxGdeYWfULNtKAcqeT0kmD/3XsoMo9ArYlX4CjjbSGj?= =?us-ascii?Q?e5DzOSRFabsZqtXDy1e5zdBLiFWOK5H3lbj23Sj+iRL6kWl91U9o5JQ93nYT?= =?us-ascii?Q?wiL08cQp/SFWhIYvw65nriqbkxozXv1yTZ4kWWKsH2+7/oL46ZpAYRx+WM8H?= =?us-ascii?Q?3y9whqGX4BdRvV/P2CTnTvv8PYcq24ivV0zUWRuSwHNVrLRcEBolKzEas5TW?= =?us-ascii?Q?+H42qypT96uQ38+aLNL0DtpF+UFyGkRKljP7YVzIXZ7q4QkecKn4GM0Ctnzf?= =?us-ascii?Q?TcLBW2M9C3rq3E8V5ywlW5/DsHFVhMTMx8s0XRWbUayYl/zvihVJQIFH5yiU?= =?us-ascii?Q?6X9vYUxxQrw24eQLmcZLmVbA7vdxYdpNW+44ytiNy30Katv1SX88Pk6PmFwV?= =?us-ascii?Q?g5tn1NOLqUrjyduktDddEEY2q/yXa+4t1Uxe5dUihttouNm/THcG50pbOx6w?= =?us-ascii?Q?WR9pLLZwUgxUd1Kg44o3LwYujL5BP7b2T8mvgxckmUlWSCMgsHIZWnktpI7X?= =?us-ascii?Q?W/ZwUPo8mLzaxfsb/DORbIwAw/PQxaHj8zI+LAaFjAnbowYbEtxYW7DxTXMx?= =?us-ascii?Q?utLWQt3VF0aJEVD/l+H/L6iDTJNY/f39UUFu6v5XI6K2lLGJlSnrTOEWxMNA?= =?us-ascii?Q?sgeifI5LmMXn5SloExZ5NAT4M3hrLP1sAP1QL/cqoFEfFfxIW96jX0OSqYvG?= =?us-ascii?Q?wdaCTWfp1YG400ZXtCarXIevpQaH2nQUJeH570otpv8JWX+z44ei7hgIXvHh?= =?us-ascii?Q?jNYfw0R9wBxsbHZCBPkaCNsCtnQCKazKvc/NnyyWh/C2RAgd7VXQ+BonwfIn?= =?us-ascii?Q?04FFAei2xeJMrNYImgRPG/LcMclZ+gyLmWgs24FIyyaoZVkWAzwzc2PQPaVc?= =?us-ascii?Q?Q1imnbLu72IbDzr66/M=3D?= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(36860700013)(7416014)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Jan 2026 07:48:50.6565 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ebedcd9b-6962-430f-c605-08de53415b96 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF000015C8.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB7264 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: William Tu The async ICOSQ is only required by TLS RX (for re-sync flow) and XSK TX. Create it only when these features are enabled instead of always allocating it. This reduces per-channel memory usage, saves hardware resources, improves latency, and decreases the default number of SQs (from 3 to 2) and CQs (from 4 to 3). It also speeds up channel open/close operations for a netdev when async ICOSQ is not needed. Currently when TLS RX is enabled, there is no channel reset triggered. As a result, async ICOSQ allocation is not triggered, causing a NULL pointer crash. One solution is to do channel reset every time when toggling TLS RX. However, it's not straightforward as the offload state matters only on connection creation, and can go on beyond the channels reset. Instead, introduce a new field 'ktls_rx_was_enabled': if TLS RX is enabled for the first time: reset channels, create async ICOSQ, set the field. From that point on, no need to reset channels for any TLS RX enable/disable. Async ICOSQ will always be needed. For XSK TX, async ICOSQ is used in wakeup control and is guaranteed to have async ICOSQ allocated. This improves the latency of interface up/down operations when it applies. Perf numbers: NIC: Connect-X7. Test: Latency of interface up + down operations. Measured 20% speedup. Saving ~0.36 sec for 248 channels (~1.45 msec per channel). Signed-off-by: William Tu Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/en.h | 1 + .../mellanox/mlx5/core/en_accel/ktls.c | 10 ++++- .../net/ethernet/mellanox/mlx5/core/en_main.c | 30 ++++++++++----- .../net/ethernet/mellanox/mlx5/core/en_txrx.c | 38 ++++++++++--------- 4 files changed, 50 insertions(+), 29 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en.h b/drivers/net/eth= ernet/mellanox/mlx5/core/en.h index a7076b26fd5c..d16bdef95703 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en.h @@ -939,6 +939,7 @@ struct mlx5e_priv { u8 max_opened_tc; bool tx_ptp_opened; bool rx_ptp_opened; + bool ktls_rx_was_enabled; struct kernel_hwtstamp_config hwtstamp_config; u16 q_counter[MLX5_SD_MAX_GROUP_SZ]; u16 drop_rq_q_counter; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ktls.c b/driv= ers/net/ethernet/mellanox/mlx5/core/en_accel/ktls.c index e3e57c849436..1c2cc2aad2b0 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ktls.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ktls.c @@ -135,10 +135,15 @@ int mlx5e_ktls_set_feature_rx(struct net_device *netd= ev, bool enable) int err =3D 0; =20 mutex_lock(&priv->state_lock); - if (enable) + if (enable) { err =3D mlx5e_accel_fs_tcp_create(priv->fs); - else + if (!err && !priv->ktls_rx_was_enabled) { + priv->ktls_rx_was_enabled =3D true; + mlx5e_safe_reopen_channels(priv); + } + } else { mlx5e_accel_fs_tcp_destroy(priv->fs); + } mutex_unlock(&priv->state_lock); =20 return err; @@ -161,6 +166,7 @@ int mlx5e_ktls_init_rx(struct mlx5e_priv *priv) destroy_workqueue(priv->tls->rx_wq); return err; } + priv->ktls_rx_was_enabled =3D true; } =20 return 0; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/en_main.c index aa4ff3963b86..d04ba93fe617 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c @@ -2632,7 +2632,8 @@ static void mlx5e_close_async_icosq(struct mlx5e_icos= q *async_icosq) =20 static int mlx5e_open_queues(struct mlx5e_channel *c, struct mlx5e_params *params, - struct mlx5e_channel_param *cparam) + struct mlx5e_channel_param *cparam, + bool async_icosq_needed) { const struct net_device_ops *netdev_ops =3D c->netdev->netdev_ops; struct dim_cq_moder icocq_moder =3D {0, 0}; @@ -2668,10 +2669,13 @@ static int mlx5e_open_queues(struct mlx5e_channel *= c, if (err) goto err_close_rx_cq; =20 - c->async_icosq =3D mlx5e_open_async_icosq(c, params, cparam, &ccp); - if (IS_ERR(c->async_icosq)) { - err =3D PTR_ERR(c->async_icosq); - goto err_close_rq_xdpsq_cq; + if (async_icosq_needed) { + c->async_icosq =3D mlx5e_open_async_icosq(c, params, cparam, + &ccp); + if (IS_ERR(c->async_icosq)) { + err =3D PTR_ERR(c->async_icosq); + goto err_close_rq_xdpsq_cq; + } } =20 mutex_init(&c->icosq_recovery_lock); @@ -2708,7 +2712,8 @@ static int mlx5e_open_queues(struct mlx5e_channel *c, mlx5e_close_icosq(&c->icosq); =20 err_close_async_icosq: - mlx5e_close_async_icosq(c->async_icosq); + if (c->async_icosq) + mlx5e_close_async_icosq(c->async_icosq); =20 err_close_rq_xdpsq_cq: if (c->xdp) @@ -2740,7 +2745,8 @@ static void mlx5e_close_queues(struct mlx5e_channel *= c) mlx5e_close_sqs(c); mlx5e_close_icosq(&c->icosq); mutex_destroy(&c->icosq_recovery_lock); - mlx5e_close_async_icosq(c->async_icosq); + if (c->async_icosq) + mlx5e_close_async_icosq(c->async_icosq); if (c->xdp) mlx5e_close_cq(&c->rq_xdpsq.cq); mlx5e_close_cq(&c->rq.cq); @@ -2825,6 +2831,7 @@ static int mlx5e_open_channel(struct mlx5e_priv *priv= , int ix, struct mlx5e_channel_param *cparam; struct mlx5_core_dev *mdev; struct mlx5e_xsk_param xsk; + bool async_icosq_needed; struct mlx5e_channel *c; unsigned int irq; int vec_ix; @@ -2874,7 +2881,8 @@ static int mlx5e_open_channel(struct mlx5e_priv *priv= , int ix, netif_napi_add_config_locked(netdev, &c->napi, mlx5e_napi_poll, ix); netif_napi_set_irq_locked(&c->napi, irq); =20 - err =3D mlx5e_open_queues(c, params, cparam); + async_icosq_needed =3D !!xsk_pool || priv->ktls_rx_was_enabled; + err =3D mlx5e_open_queues(c, params, cparam, async_icosq_needed); if (unlikely(err)) goto err_napi_del; =20 @@ -2912,7 +2920,8 @@ static void mlx5e_activate_channel(struct mlx5e_chann= el *c) for (tc =3D 0; tc < c->num_tc; tc++) mlx5e_activate_txqsq(&c->sq[tc]); mlx5e_activate_icosq(&c->icosq); - mlx5e_activate_icosq(c->async_icosq); + if (c->async_icosq) + mlx5e_activate_icosq(c->async_icosq); =20 if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state)) mlx5e_activate_xsk(c); @@ -2933,7 +2942,8 @@ static void mlx5e_deactivate_channel(struct mlx5e_cha= nnel *c) else mlx5e_deactivate_rq(&c->rq); =20 - mlx5e_deactivate_icosq(c->async_icosq); + if (c->async_icosq) + mlx5e_deactivate_icosq(c->async_icosq); mlx5e_deactivate_icosq(&c->icosq); for (tc =3D 0; tc < c->num_tc; tc++) mlx5e_deactivate_txqsq(&c->sq[tc]); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_txrx.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/en_txrx.c index 57c54265dbda..b31f689fe271 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_txrx.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_txrx.c @@ -125,6 +125,7 @@ int mlx5e_napi_poll(struct napi_struct *napi, int budge= t) { struct mlx5e_channel *c =3D container_of(napi, struct mlx5e_channel, napi); + struct mlx5e_icosq *aicosq =3D c->async_icosq; struct mlx5e_ch_stats *ch_stats =3D c->stats; struct mlx5e_xdpsq *xsksq =3D &c->xsksq; struct mlx5e_txqsq __rcu **qos_sqs; @@ -180,16 +181,18 @@ int mlx5e_napi_poll(struct napi_struct *napi, int bud= get) busy |=3D work_done =3D=3D budget; =20 mlx5e_poll_ico_cq(&c->icosq.cq); - if (mlx5e_poll_ico_cq(&c->async_icosq->cq)) - /* Don't clear the flag if nothing was polled to prevent - * queueing more WQEs and overflowing the async ICOSQ. - */ - clear_bit(MLX5E_SQ_STATE_PENDING_XSK_TX, - &c->async_icosq->state); - - /* Keep after async ICOSQ CQ poll */ - if (unlikely(mlx5e_ktls_rx_pending_resync_list(c, budget))) - busy |=3D mlx5e_ktls_rx_handle_resync_list(c, budget); + if (aicosq) { + if (mlx5e_poll_ico_cq(&aicosq->cq)) + /* Don't clear the flag if nothing was polled to prevent + * queueing more WQEs and overflowing the async ICOSQ. + */ + clear_bit(MLX5E_SQ_STATE_PENDING_XSK_TX, + &aicosq->state); + + /* Keep after async ICOSQ CQ poll */ + if (unlikely(mlx5e_ktls_rx_pending_resync_list(c, budget))) + busy |=3D mlx5e_ktls_rx_handle_resync_list(c, budget); + } =20 busy |=3D INDIRECT_CALL_2(rq->post_wqes, mlx5e_post_rx_mpwqes, @@ -237,16 +240,17 @@ int mlx5e_napi_poll(struct napi_struct *napi, int bud= get) =20 mlx5e_cq_arm(&rq->cq); mlx5e_cq_arm(&c->icosq.cq); - mlx5e_cq_arm(&c->async_icosq->cq); + if (aicosq) { + mlx5e_cq_arm(&aicosq->cq); + if (xsk_open) { + mlx5e_handle_rx_dim(xskrq); + mlx5e_cq_arm(&xsksq->cq); + mlx5e_cq_arm(&xskrq->cq); + } + } if (c->xdpsq) mlx5e_cq_arm(&c->xdpsq->cq); =20 - if (xsk_open) { - mlx5e_handle_rx_dim(xskrq); - mlx5e_cq_arm(&xsksq->cq); - mlx5e_cq_arm(&xskrq->cq); - } - if (unlikely(aff_change && busy_xsk)) { mlx5e_trigger_irq(&c->icosq); ch_stats->force_irq++; --=20 2.31.1