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Mon, 24 Nov 2025 14:29:43 -0800 From: Tariq Toukan To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Donald Hunter , Jiri Pirko , Jonathan Corbet , Saeed Mahameed , "Leon Romanovsky" , Tariq Toukan , Mark Bloch , , , , , Gal Pressman , Moshe Shemesh , Carolina Jubran , Cosmin Ratiu , Jiri Pirko Subject: [PATCH net-next V3 12/14] net/mlx5: qos: Support cross-device tx scheduling Date: Tue, 25 Nov 2025 00:27:37 +0200 Message-ID: <1764023259-1305453-13-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1764023259-1305453-1-git-send-email-tariqt@nvidia.com> References: <1764023259-1305453-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF0001709D:EE_|DS0PR12MB9321:EE_ X-MS-Office365-Filtering-Correlation-Id: 7e234eaa-3eb0-4e2b-d526-08de2ba9024a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|7416014|376014|1800799024|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?8BvAWCyWTL2TEIhDRifbwuv+1KDf8g67D28x9+ptBe5rflcP0jud5K5lfUIJ?= =?us-ascii?Q?uwA8cLG7FXwp7KfJFYpcd5YwbwiHxMhIVarJGTPlMGx9XptBkKONtPZnLPni?= =?us-ascii?Q?Ui2zWTFTccRPDGfqKa6I1qVjHAjqFwyi6/iyL/PIDWDQQ7nlRMuAy04p6qFt?= =?us-ascii?Q?hPZd3bFty3J7eJhJ1qckr4DD/8pf/mt2gFVnsVoJ468UR5q2e9sOiOGFhAWe?= =?us-ascii?Q?3FZrngKIzPoyytc3HyZc53+jG6saEljmoi9ug7+CLvX97bJrLy2yG/akqcXH?= =?us-ascii?Q?eeX3tyu2FsQ3Re0BIr3o5pJm+ZQFUAckf31B3+GUuJxPK9zEFgauUPr08lRx?= =?us-ascii?Q?gK593KzXv+n8Nln813pLwnJkqxtq8G4j2oCoETLJdb6tbFLySPtegAYW5v3Y?= =?us-ascii?Q?XXBY6iQ0+Sz/8cM33hDffsg+jf5CwUjSIefd9VeGHZcOCqw4I2boEtcUKxBl?= =?us-ascii?Q?0xRebcnj2Duc5vqiiX3dt0bJkOHwIgxwNpf7vvd9h/BzVVN8wnURcxE4iFpX?= =?us-ascii?Q?dJrS8cPpRe3huA9mgiodYUTkVmf6zLmg2sDn3BxtNT2iEhWt/47MP6sgaX/e?= =?us-ascii?Q?Yh+J8cS6Wm4BAxVHeQK7orfsvIBnA7o15wFO4VIrxwO6j27LVAnmg1cb1cUs?= =?us-ascii?Q?KFuS0vr5NsSuYTgohY4rMA+PyNu5gC29mc2GUk8uup2z3hDR2JAtqvIP+ZWc?= =?us-ascii?Q?QuQwu1D4Qn05qjeuZTRY5b9dXFDnZZZ1M0VSgo7/VOX/qUkIw2WdplXY1ROv?= =?us-ascii?Q?KX8biBJhI1ci2dT46J7rM2sEXro/0C1vziO489Wy3jCXpipda9f1n1ElGyei?= =?us-ascii?Q?2Xxy5q4GfXDQNfKo8Bx5a98/NrImsjFSmQx9EJMTHFKVrLGWDbWXRjjBtyIF?= =?us-ascii?Q?G87CPXZDNYzlOAHpyhmCfB7GVKSAnLPlHVX+4C44bbcDXpX3KzEZmljusQDh?= =?us-ascii?Q?9kuPLpRdrQb66qLDr1pA1Zo0Ba3F0cQOG4djystIu5ljCBAOeMR6V/Hhosp3?= =?us-ascii?Q?qoQ/rRx8Zoh6tYgorx33nkDBhW2oN1G4QXXct56Ytan5fT1ePQbqtc1OqDEn?= =?us-ascii?Q?9YuP3X3UW+691jRMdXquae6201TDb8NrELwtceMee761u9YnPArvg1zddX38?= =?us-ascii?Q?dSUyigb5XuS7tXrdpGU5vx/JMBKBQLlt+O6hZn9DnEVEPAQh8Kg0ANHlbeZB?= =?us-ascii?Q?j+lEopacd/gLgN8JGLfY0Lhep1CllnxksUHCzNKdCdcPguZSOgji/jRyXj8z?= =?us-ascii?Q?97GFmnhcpYuI6Pt3DGOLVAXYj1aIVcwlnizwDdboAInKdu34bCofWCRUMdqN?= =?us-ascii?Q?f+AbYmax0iUh7nu4/YXWS6PmrfeW2N0Pk1mGh/lKbf7MTzUZi7ZVv66UwqqD?= =?us-ascii?Q?h9wKGb43dXCVzD7z6gdUOIb8NkX8nXYIShzebKa3kjWr2lWgFhlnIReC73my?= =?us-ascii?Q?AnIWD1hE9qysEbnmy6F1Yihg2CYItAMm2n5EukOFi/VcJWEbXshiT2KYpj9a?= =?us-ascii?Q?NUz75Nvu7iMKRmDRzvXTDgE/Mltk5xNceLXO+JIbQrHerLn9ut3TjTVFP/wL?= =?us-ascii?Q?CdyTFsC/sNpNI21DZ/I=3D?= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(7416014)(376014)(1800799024)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Nov 2025 22:30:01.9844 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7e234eaa-3eb0-4e2b-d526-08de2ba9024a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF0001709D.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB9321 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Cosmin Ratiu Up to now, rate groups could only contain vports from the same E-Switch. This patch relaxes that restriction if the device supports it (HCA_CAP.esw_cross_esw_sched =3D=3D true) and the right conditions are met: - Link Aggregation (LAG) is enabled. - The E-Switches are from the same shared devlink device. This patch does not yet enable cross-esw scheduling, it's just the last preparatory patch. Signed-off-by: Cosmin Ratiu Reviewed-by: Carolina Jubran Signed-off-by: Tariq Toukan --- .../net/ethernet/mellanox/mlx5/core/esw/qos.c | 114 +++++++++++++----- 1 file changed, 81 insertions(+), 33 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/esw/qos.c index f86d7c50db42..3c8716b0644b 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c @@ -50,7 +50,9 @@ struct mlx5_esw_sched_node { enum sched_node_type type; /* The eswitch this node belongs to. */ struct mlx5_eswitch *esw; - /* The children nodes of this node, empty list for leaf nodes. */ + /* The children nodes of this node, empty list for leaf nodes. + * Can be from multiple E-Switches. + */ struct list_head children; /* Valid only if this node is associated with a vport. */ struct mlx5_vport *vport; @@ -419,6 +421,7 @@ esw_qos_vport_create_sched_element(struct mlx5_esw_sche= d_node *vport_node, struct mlx5_esw_sched_node *parent =3D vport_node->parent; u32 sched_ctx[MLX5_ST_SZ_DW(scheduling_context)] =3D {}; struct mlx5_core_dev *dev =3D vport_node->esw->dev; + struct mlx5_vport *vport =3D vport_node->vport; void *attr; =20 if (!mlx5_qos_element_type_supported( @@ -430,11 +433,18 @@ esw_qos_vport_create_sched_element(struct mlx5_esw_sc= hed_node *vport_node, MLX5_SET(scheduling_context, sched_ctx, element_type, SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT); attr =3D MLX5_ADDR_OF(scheduling_context, sched_ctx, element_attributes); - MLX5_SET(vport_element, attr, vport_number, vport_node->vport->vport); + MLX5_SET(vport_element, attr, vport_number, vport->vport); MLX5_SET(scheduling_context, sched_ctx, parent_element_id, parent ? parent->ix : vport_node->esw->qos.root_tsar_ix); MLX5_SET(scheduling_context, sched_ctx, max_average_bw, vport_node->max_rate); + if (vport->dev !=3D dev) { + /* The port is assigned to a node on another eswitch. */ + MLX5_SET(vport_element, attr, eswitch_owner_vhca_id_valid, + true); + MLX5_SET(vport_element, attr, eswitch_owner_vhca_id, + MLX5_CAP_GEN(vport->dev, vhca_id)); + } =20 return esw_qos_node_create_sched_element(vport_node, sched_ctx, extack); } @@ -446,6 +456,7 @@ esw_qos_vport_tc_create_sched_element(struct mlx5_esw_s= ched_node *vport_tc_node, { u32 sched_ctx[MLX5_ST_SZ_DW(scheduling_context)] =3D {}; struct mlx5_core_dev *dev =3D vport_tc_node->esw->dev; + struct mlx5_vport *vport =3D vport_tc_node->vport; void *attr; =20 if (!mlx5_qos_element_type_supported( @@ -457,8 +468,7 @@ esw_qos_vport_tc_create_sched_element(struct mlx5_esw_s= ched_node *vport_tc_node, MLX5_SET(scheduling_context, sched_ctx, element_type, SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC); attr =3D MLX5_ADDR_OF(scheduling_context, sched_ctx, element_attributes); - MLX5_SET(vport_tc_element, attr, vport_number, - vport_tc_node->vport->vport); + MLX5_SET(vport_tc_element, attr, vport_number, vport->vport); MLX5_SET(vport_tc_element, attr, traffic_class, vport_tc_node->tc); MLX5_SET(scheduling_context, sched_ctx, max_bw_obj_id, rate_limit_elem_ix); @@ -466,6 +476,13 @@ esw_qos_vport_tc_create_sched_element(struct mlx5_esw_= sched_node *vport_tc_node, vport_tc_node->parent->ix); MLX5_SET(scheduling_context, sched_ctx, bw_share, vport_tc_node->bw_share); + if (vport->dev !=3D dev) { + /* The port is assigned to a node on another eswitch. */ + MLX5_SET(vport_tc_element, attr, eswitch_owner_vhca_id_valid, + true); + MLX5_SET(vport_tc_element, attr, eswitch_owner_vhca_id, + MLX5_CAP_GEN(vport->dev, vhca_id)); + } =20 return esw_qos_node_create_sched_element(vport_tc_node, sched_ctx, extack); @@ -1194,6 +1211,29 @@ static int esw_qos_vport_tc_check_type(enum sched_no= de_type curr_type, return 0; } =20 +static bool esw_qos_validate_unsupported_tc_bw(struct mlx5_eswitch *esw, + u32 *tc_bw) +{ + int i, num_tcs =3D esw_qos_num_tcs(esw->dev); + + for (i =3D num_tcs; i < DEVLINK_RATE_TCS_MAX; i++) + if (tc_bw[i]) + return false; + + return true; +} + +static bool esw_qos_vport_validate_unsupported_tc_bw(struct mlx5_vport *vp= ort, + u32 *tc_bw) +{ + struct mlx5_esw_sched_node *node =3D vport->qos.sched_node; + struct mlx5_eswitch *esw =3D vport->dev->priv.eswitch; + + esw =3D (node && node->parent) ? node->parent->esw : esw; + + return esw_qos_validate_unsupported_tc_bw(esw, tc_bw); +} + static int esw_qos_vport_update(struct mlx5_vport *vport, enum sched_node_type type, struct mlx5_esw_sched_node *parent, @@ -1227,6 +1267,12 @@ static int esw_qos_vport_update(struct mlx5_vport *v= port, if (curr_type =3D=3D SCHED_NODE_TYPE_TC_ARBITER_TSAR && curr_type =3D=3D = type) { esw_qos_set_tc_arbiter_bw_shares(vport_node, curr_tc_bw, extack); + if (!esw_qos_validate_unsupported_tc_bw(parent->esw, + curr_tc_bw)) { + NL_SET_ERR_MSG_MOD(extack, + "Unsupported traffic classes on the new device"); + return -EOPNOTSUPP; + } } =20 return err; @@ -1575,30 +1621,6 @@ static int esw_qos_devlink_rate_to_mbps(struct mlx5_= core_dev *mdev, const char * return 0; } =20 -static bool esw_qos_validate_unsupported_tc_bw(struct mlx5_eswitch *esw, - u32 *tc_bw) -{ - int i, num_tcs =3D esw_qos_num_tcs(esw->dev); - - for (i =3D num_tcs; i < DEVLINK_RATE_TCS_MAX; i++) { - if (tc_bw[i]) - return false; - } - - return true; -} - -static bool esw_qos_vport_validate_unsupported_tc_bw(struct mlx5_vport *vp= ort, - u32 *tc_bw) -{ - struct mlx5_esw_sched_node *node =3D vport->qos.sched_node; - struct mlx5_eswitch *esw =3D vport->dev->priv.eswitch; - - esw =3D (node && node->parent) ? node->parent->esw : esw; - - return esw_qos_validate_unsupported_tc_bw(esw, tc_bw); -} - static bool esw_qos_tc_bw_disabled(u32 *tc_bw) { int i; @@ -1803,18 +1825,44 @@ int mlx5_esw_devlink_rate_node_del(struct devlink_r= ate *rate_node, void *priv, return 0; } =20 +static int +mlx5_esw_validate_cross_esw_scheduling(struct mlx5_eswitch *esw, + struct mlx5_esw_sched_node *parent, + struct netlink_ext_ack *extack) +{ + if (!parent || esw =3D=3D parent->esw) + return 0; + + if (!MLX5_CAP_QOS(esw->dev, esw_cross_esw_sched)) { + NL_SET_ERR_MSG_MOD(extack, + "Cross E-Switch scheduling is not supported"); + return -EOPNOTSUPP; + } + if (esw->dev->shd !=3D parent->esw->dev->shd) { + NL_SET_ERR_MSG_MOD(extack, + "Cannot add vport to a parent belonging to a different device"); + return -EOPNOTSUPP; + } + if (!mlx5_lag_is_active(esw->dev)) { + NL_SET_ERR_MSG_MOD(extack, + "Cross E-Switch scheduling requires LAG to be activated"); + return -EOPNOTSUPP; + } + + return 0; +} + static int mlx5_esw_qos_vport_update_parent(struct mlx5_vport *vport, struct mlx5_esw_sched_node *parent, struct netlink_ext_ack *extack) { struct mlx5_eswitch *esw =3D vport->dev->priv.eswitch; - int err =3D 0; + int err; =20 - if (parent && parent->esw !=3D esw) { - NL_SET_ERR_MSG_MOD(extack, "Cross E-Switch scheduling is not supported"); - return -EOPNOTSUPP; - } + err =3D mlx5_esw_validate_cross_esw_scheduling(esw, parent, extack); + if (err) + return err; =20 if (!vport->qos.sched_node && parent) { enum sched_node_type type; --=20 2.31.1