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Sat, 22 Nov 2025 23:24:20 -0800 From: Tariq Toukan To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Donald Hunter , Jiri Pirko , Jonathan Corbet , Saeed Mahameed , "Leon Romanovsky" , Tariq Toukan , Mark Bloch , , , , , Gal Pressman , Moshe Shemesh , Carolina Jubran , Cosmin Ratiu , Jiri Pirko Subject: [PATCH net-next V2 12/14] net/mlx5: qos: Support cross-device tx scheduling Date: Sun, 23 Nov 2025 09:22:58 +0200 Message-ID: <1763882580-1295213-13-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1763882580-1295213-1-git-send-email-tariqt@nvidia.com> References: <1763882580-1295213-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF00003445:EE_|IA1PR12MB7616:EE_ X-MS-Office365-Filtering-Correlation-Id: 2b32c8e2-a9f9-4ce9-78f4-08de2a615a99 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|376014|7416014|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?0jdIJrQt6MhQhmOyKNUwoEg0lbhE+rBQms190BofQraczDvr9MCytQPf2g3h?= =?us-ascii?Q?tTlwk7x87232u6gour+uDhh3gBQ4TtVflHUinCn2NjQyGDsQsMktyhSVPupo?= =?us-ascii?Q?HdbeOgM+uqiAeik048e+ZuwtEgDELN3XAzhKcHdgrxwzUqDMR7eADXCwK9jd?= =?us-ascii?Q?ZY04i8uacKBIGnZBHVnRh0/kYvs/aVpqt0FgHJbyaedJLEj/jSL7OZEsM4zY?= =?us-ascii?Q?o0ALxTbE4bEClzYIb2C2k8c9WIjWgDtmTVsUdOY10l7wjKaz2WdAne5s+0Hp?= =?us-ascii?Q?B94zj0PcRiPp6LtLt9esIgB4M/wmChkrrwrwXyzhzldlaGxO6xlM8ZH2OeSA?= =?us-ascii?Q?N4nkEYshIPEyzv+OjY7FWsyVOgSBwgcp5TLIP8krTNnJsz2N6yb4xLacuM3j?= =?us-ascii?Q?rsUfzs/0yC0QUsv8diN/pr/1NslxJhT+MLDGaopvl0WoDABM7oUute/3SKFK?= =?us-ascii?Q?IpsFDS9WDI7sqZ3tZUBrRYFZq2w2lRlKo3l1BSuDpZ8wiget8ibvvxk4B4Jm?= =?us-ascii?Q?B/tKA3n+POjod/XDsDxg/KDh1eGA83AqoQTzgGQzWWmoPmw+NPoLaaVthNXH?= =?us-ascii?Q?/L+UxSSxqd603PmzCVV6jZiV0MSSovplCiweqw6PsKOa0Jjb5QMgpKRgZBnO?= =?us-ascii?Q?t0erFYHXl3TT8x9cBM7wdl0ZhzZZ/NvS/fluE+2O2WiQpPgGb45XnbVlezhq?= =?us-ascii?Q?7jkaiHALmEx8FR4SvMPEkU7g7BCIkdOB1vAdRbTRQ6+HLeL4brg61wwbmiVa?= =?us-ascii?Q?E6vzxFKU3uEcnYSkTFITIeXkLI1feWKBqnd7Wu3FQcWcj+d+WPgxApd2J1qG?= =?us-ascii?Q?VtJN/IB29QbvwDWGhE+4zmMAk4BvX6pNknnal1O2r2MqkhmwJUc0BnoQWV1c?= =?us-ascii?Q?jPXY9UjeYXLgbsCYPX9A4mwGzj7DAQkOC0cX1Oo5vqyU8HsOdlNvKg9/VR+n?= =?us-ascii?Q?jXVMW6adCRqtI0UklzMltqLE/Q6kwBnUfA1hSjuE1xYjCkATlwvOrtUP2vGz?= =?us-ascii?Q?R397qXgt9aBv/OYrCYMxz51BLvxnT5WYeZBVKyXNiVZMngK1BFXd/wnMhElR?= =?us-ascii?Q?6hEXrVw/48I6SvwzpNeEbIyKkgA2TDEHAS0UIFS/gkEjNNmntDLohNtjhdo7?= =?us-ascii?Q?u1ZA5kVIwhiIvOoOBHLrPSYi8NDseso+rkoukAEsOlyYwKAa3eWmc7GIXSY7?= =?us-ascii?Q?hbdwPM2ZcttejcmIrUdf4WGkKnxD7PKx6WaRe1Zc55WkkZGFVugIMb6lK87t?= =?us-ascii?Q?VWr+2ziKjDaaat0N/9M1ZaJfu7Kx6NNsuNmCFv4CKh44J7lqZY9QWxh6Q/5v?= =?us-ascii?Q?clbk87HXe0ySFt+YblfhK5xdMTkKs69vOM4VOO93TItqv8h+MAnhFmESwDk5?= =?us-ascii?Q?KNftD89apze/t1mv1oK3wzL+TzC1t6GKdjkQE5sTJIjNJCBE0niVLRBi5dPr?= =?us-ascii?Q?atZd1qytn0OfJ+n2/M4lJbTical7HW+026YRQU9GGN77mbJRcxA6pszA4Px/?= =?us-ascii?Q?U5NPAN/fFxNH1DKaz4ztkM44+wIP9YRyZWGgmRas+vW0BkasouCbDusq9WFd?= =?us-ascii?Q?GqjIhgQBIZK1xz66o8k=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(1800799024)(376014)(7416014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Nov 2025 07:24:35.1937 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2b32c8e2-a9f9-4ce9-78f4-08de2a615a99 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF00003445.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB7616 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Cosmin Ratiu Up to now, rate groups could only contain vports from the same E-Switch. This patch relaxes that restriction if the device supports it (HCA_CAP.esw_cross_esw_sched =3D=3D true) and the right conditions are met: - Link Aggregation (LAG) is enabled. - The E-Switches are from the same shared devlink device. This patch does not yet enable cross-esw scheduling, it's just the last preparatory patch. Signed-off-by: Cosmin Ratiu Reviewed-by: Carolina Jubran Signed-off-by: Tariq Toukan --- .../net/ethernet/mellanox/mlx5/core/esw/qos.c | 114 +++++++++++++----- 1 file changed, 81 insertions(+), 33 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/esw/qos.c index f86d7c50db42..3c8716b0644b 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c @@ -50,7 +50,9 @@ struct mlx5_esw_sched_node { enum sched_node_type type; /* The eswitch this node belongs to. */ struct mlx5_eswitch *esw; - /* The children nodes of this node, empty list for leaf nodes. */ + /* The children nodes of this node, empty list for leaf nodes. + * Can be from multiple E-Switches. + */ struct list_head children; /* Valid only if this node is associated with a vport. */ struct mlx5_vport *vport; @@ -419,6 +421,7 @@ esw_qos_vport_create_sched_element(struct mlx5_esw_sche= d_node *vport_node, struct mlx5_esw_sched_node *parent =3D vport_node->parent; u32 sched_ctx[MLX5_ST_SZ_DW(scheduling_context)] =3D {}; struct mlx5_core_dev *dev =3D vport_node->esw->dev; + struct mlx5_vport *vport =3D vport_node->vport; void *attr; =20 if (!mlx5_qos_element_type_supported( @@ -430,11 +433,18 @@ esw_qos_vport_create_sched_element(struct mlx5_esw_sc= hed_node *vport_node, MLX5_SET(scheduling_context, sched_ctx, element_type, SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT); attr =3D MLX5_ADDR_OF(scheduling_context, sched_ctx, element_attributes); - MLX5_SET(vport_element, attr, vport_number, vport_node->vport->vport); + MLX5_SET(vport_element, attr, vport_number, vport->vport); MLX5_SET(scheduling_context, sched_ctx, parent_element_id, parent ? parent->ix : vport_node->esw->qos.root_tsar_ix); MLX5_SET(scheduling_context, sched_ctx, max_average_bw, vport_node->max_rate); + if (vport->dev !=3D dev) { + /* The port is assigned to a node on another eswitch. */ + MLX5_SET(vport_element, attr, eswitch_owner_vhca_id_valid, + true); + MLX5_SET(vport_element, attr, eswitch_owner_vhca_id, + MLX5_CAP_GEN(vport->dev, vhca_id)); + } =20 return esw_qos_node_create_sched_element(vport_node, sched_ctx, extack); } @@ -446,6 +456,7 @@ esw_qos_vport_tc_create_sched_element(struct mlx5_esw_s= ched_node *vport_tc_node, { u32 sched_ctx[MLX5_ST_SZ_DW(scheduling_context)] =3D {}; struct mlx5_core_dev *dev =3D vport_tc_node->esw->dev; + struct mlx5_vport *vport =3D vport_tc_node->vport; void *attr; =20 if (!mlx5_qos_element_type_supported( @@ -457,8 +468,7 @@ esw_qos_vport_tc_create_sched_element(struct mlx5_esw_s= ched_node *vport_tc_node, MLX5_SET(scheduling_context, sched_ctx, element_type, SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC); attr =3D MLX5_ADDR_OF(scheduling_context, sched_ctx, element_attributes); - MLX5_SET(vport_tc_element, attr, vport_number, - vport_tc_node->vport->vport); + MLX5_SET(vport_tc_element, attr, vport_number, vport->vport); MLX5_SET(vport_tc_element, attr, traffic_class, vport_tc_node->tc); MLX5_SET(scheduling_context, sched_ctx, max_bw_obj_id, rate_limit_elem_ix); @@ -466,6 +476,13 @@ esw_qos_vport_tc_create_sched_element(struct mlx5_esw_= sched_node *vport_tc_node, vport_tc_node->parent->ix); MLX5_SET(scheduling_context, sched_ctx, bw_share, vport_tc_node->bw_share); + if (vport->dev !=3D dev) { + /* The port is assigned to a node on another eswitch. */ + MLX5_SET(vport_tc_element, attr, eswitch_owner_vhca_id_valid, + true); + MLX5_SET(vport_tc_element, attr, eswitch_owner_vhca_id, + MLX5_CAP_GEN(vport->dev, vhca_id)); + } =20 return esw_qos_node_create_sched_element(vport_tc_node, sched_ctx, extack); @@ -1194,6 +1211,29 @@ static int esw_qos_vport_tc_check_type(enum sched_no= de_type curr_type, return 0; } =20 +static bool esw_qos_validate_unsupported_tc_bw(struct mlx5_eswitch *esw, + u32 *tc_bw) +{ + int i, num_tcs =3D esw_qos_num_tcs(esw->dev); + + for (i =3D num_tcs; i < DEVLINK_RATE_TCS_MAX; i++) + if (tc_bw[i]) + return false; + + return true; +} + +static bool esw_qos_vport_validate_unsupported_tc_bw(struct mlx5_vport *vp= ort, + u32 *tc_bw) +{ + struct mlx5_esw_sched_node *node =3D vport->qos.sched_node; + struct mlx5_eswitch *esw =3D vport->dev->priv.eswitch; + + esw =3D (node && node->parent) ? node->parent->esw : esw; + + return esw_qos_validate_unsupported_tc_bw(esw, tc_bw); +} + static int esw_qos_vport_update(struct mlx5_vport *vport, enum sched_node_type type, struct mlx5_esw_sched_node *parent, @@ -1227,6 +1267,12 @@ static int esw_qos_vport_update(struct mlx5_vport *v= port, if (curr_type =3D=3D SCHED_NODE_TYPE_TC_ARBITER_TSAR && curr_type =3D=3D = type) { esw_qos_set_tc_arbiter_bw_shares(vport_node, curr_tc_bw, extack); + if (!esw_qos_validate_unsupported_tc_bw(parent->esw, + curr_tc_bw)) { + NL_SET_ERR_MSG_MOD(extack, + "Unsupported traffic classes on the new device"); + return -EOPNOTSUPP; + } } =20 return err; @@ -1575,30 +1621,6 @@ static int esw_qos_devlink_rate_to_mbps(struct mlx5_= core_dev *mdev, const char * return 0; } =20 -static bool esw_qos_validate_unsupported_tc_bw(struct mlx5_eswitch *esw, - u32 *tc_bw) -{ - int i, num_tcs =3D esw_qos_num_tcs(esw->dev); - - for (i =3D num_tcs; i < DEVLINK_RATE_TCS_MAX; i++) { - if (tc_bw[i]) - return false; - } - - return true; -} - -static bool esw_qos_vport_validate_unsupported_tc_bw(struct mlx5_vport *vp= ort, - u32 *tc_bw) -{ - struct mlx5_esw_sched_node *node =3D vport->qos.sched_node; - struct mlx5_eswitch *esw =3D vport->dev->priv.eswitch; - - esw =3D (node && node->parent) ? node->parent->esw : esw; - - return esw_qos_validate_unsupported_tc_bw(esw, tc_bw); -} - static bool esw_qos_tc_bw_disabled(u32 *tc_bw) { int i; @@ -1803,18 +1825,44 @@ int mlx5_esw_devlink_rate_node_del(struct devlink_r= ate *rate_node, void *priv, return 0; } =20 +static int +mlx5_esw_validate_cross_esw_scheduling(struct mlx5_eswitch *esw, + struct mlx5_esw_sched_node *parent, + struct netlink_ext_ack *extack) +{ + if (!parent || esw =3D=3D parent->esw) + return 0; + + if (!MLX5_CAP_QOS(esw->dev, esw_cross_esw_sched)) { + NL_SET_ERR_MSG_MOD(extack, + "Cross E-Switch scheduling is not supported"); + return -EOPNOTSUPP; + } + if (esw->dev->shd !=3D parent->esw->dev->shd) { + NL_SET_ERR_MSG_MOD(extack, + "Cannot add vport to a parent belonging to a different device"); + return -EOPNOTSUPP; + } + if (!mlx5_lag_is_active(esw->dev)) { + NL_SET_ERR_MSG_MOD(extack, + "Cross E-Switch scheduling requires LAG to be activated"); + return -EOPNOTSUPP; + } + + return 0; +} + static int mlx5_esw_qos_vport_update_parent(struct mlx5_vport *vport, struct mlx5_esw_sched_node *parent, struct netlink_ext_ack *extack) { struct mlx5_eswitch *esw =3D vport->dev->priv.eswitch; - int err =3D 0; + int err; =20 - if (parent && parent->esw !=3D esw) { - NL_SET_ERR_MSG_MOD(extack, "Cross E-Switch scheduling is not supported"); - return -EOPNOTSUPP; - } + err =3D mlx5_esw_validate_cross_esw_scheduling(esw, parent, extack); + if (err) + return err; =20 if (!vport->qos.sched_node && parent) { enum sched_node_type type; --=20 2.31.1