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Sat, 22 Nov 2025 23:24:01 -0800 From: Tariq Toukan To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Donald Hunter , Jiri Pirko , Jonathan Corbet , Saeed Mahameed , "Leon Romanovsky" , Tariq Toukan , Mark Bloch , , , , , Gal Pressman , Moshe Shemesh , Carolina Jubran , Cosmin Ratiu , Jiri Pirko Subject: [PATCH net-next V2 09/14] net/mlx5: Introduce shared devlink instance for PFs on same chip Date: Sun, 23 Nov 2025 09:22:55 +0200 Message-ID: <1763882580-1295213-10-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1763882580-1295213-1-git-send-email-tariqt@nvidia.com> References: <1763882580-1295213-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000397AE:EE_|CY5PR12MB6621:EE_ X-MS-Office365-Filtering-Correlation-Id: 63b42825-0d2d-4144-8cad-08de2a615319 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|30052699003|1800799024|7416014|376014|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?XtHgbUTDpx5GF3972GKK6NVnoz1Zv0sA9Fc6U905P5Y4Xj1chbnhqbkXGgiQ?= =?us-ascii?Q?mBwkwtG1LTuhw6YCfLV8ugPJHLeeCkL9e26SZPPyL7eQbBe0/Qa5xxKJZy4g?= =?us-ascii?Q?4kqwbCnVJx0AkZj0ZfUAEUD+Y3ruLRujaNTuIiY3H8HlgebdXexIXO+h+RnG?= =?us-ascii?Q?p0kQSA8chAc0SjmcGhtz5Ta65c1snPV/M2vcasu2S/wxiBJu6E392oF4XyrW?= =?us-ascii?Q?BvQYjBplXCS8+6tbhim65kHJRUWr7ZEWgu559gkvgffm4neGheudOxvtp7vF?= =?us-ascii?Q?CpnnokofBRccgDNZ7Zc1/Z4LXiuUvQc9jJYVv548UcrJ+ZTmJ4acghdAS323?= =?us-ascii?Q?0A8pllFieWT+a10/0dcdcuJubNvj6qFzAUyvkNxs3f24+Gsfr/cbtt8LswZG?= =?us-ascii?Q?pHYuOiICqIlhM9P4MEzoO6hwbtEb5cIQkPOvDdr082lo0nwSv4w7oDSOKFsw?= =?us-ascii?Q?psDiQ3/fwTF/SE86gAyRVRgoczq6SRWlfFidD5gZWYKyR5zZaucjMIJSMa8A?= =?us-ascii?Q?C4AFriHCQ5eqRChSCmdImKa4QrohDe3Dx6sToAkGWWbmHzDiCCcyi70LL1hj?= =?us-ascii?Q?AQFA5TZ+NE3ziZzNZeiKphIzXlUezE2yv+Au/3FHcGSGdzQgXu7f0UziuEEn?= =?us-ascii?Q?IrROs8bobD0+6Nlkb373zvvII/zYaBU67P3xopWCMCGQYr3FQZxU/hU8f4aR?= =?us-ascii?Q?/qE3PSDWMEIo32OBnf+BztV1EdNeBBoaqIPmd6n+1QlQ4YJWpi7cm8waGUzy?= =?us-ascii?Q?VctRbvntNCmBZd3DYmr5NDrlp8uUzn8xanXum1gN9A1d9FFIZpALXYwwLri+?= =?us-ascii?Q?FdvONMf5P8nf/8PN98mFVW5HP3BlGDP0fyQNPAs1cLkHX8q7t6qAciGcAbYD?= =?us-ascii?Q?qmi8/lMphQRN3q5l8kO9ZJehH9V5YEUwDojmhg7/42l3F5/8GDFfKcuSYE2d?= =?us-ascii?Q?uTEB0M3IOJUAhvDv/BNB6qU0x5hVMR0SYvAU7sYahCNB+vEv2d5arFERzvkW?= =?us-ascii?Q?1UgBbLgooHrDhBzV9q3nuyTr0vDz1NFcmnr3rsEg5B9fv+ehFhyFNBzw0/wz?= =?us-ascii?Q?LXScxb0HrVmOYw3gw3gCTLCVhn9eRpIODgtc4rokCu/TSH/5YRxDX8PvGdT5?= =?us-ascii?Q?G5jq54Y2JaoUr5mbYgZligxnv/yDlrmoP6b4DTwIrSIoDUQ88slESCsg35lK?= =?us-ascii?Q?yG/1v7oBdA1JdScMbAQ6Iuhwy0JdTATQWeshrid8R0IAeK/CPs8rQJpWJklY?= =?us-ascii?Q?tN1jNNR5hDieV6UfHK6dewylMTcRShVF4a0+h/hqxcaPtDY6oeqU2dScVge5?= =?us-ascii?Q?CpxqtSVgQY8W2wdHOO62GUgnv0mppIwojWjM2T4pkghyhRGCPA9N2ysJoVLV?= =?us-ascii?Q?c9U0aSdhfBbnAphYzYM1S8q83/JZM072D//COViZnZWMe5Ztz1zuXgS38kwJ?= =?us-ascii?Q?eRbw3pzsO7AlEhT3JZvccJWqtA07n1SlLk/M6CQpDqTNXncv/GxinbQv6tfU?= =?us-ascii?Q?bPWWAwnZHfM/au8GJc8SzG9B51thQtZxMN92cNmxdipxYjFKt+OR1vkQ8fp5?= =?us-ascii?Q?GWLCDlz08HnwJWEC7uI=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(30052699003)(1800799024)(7416014)(376014)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Nov 2025 07:24:22.6134 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 63b42825-0d2d-4144-8cad-08de2a615319 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000397AE.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6621 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Jiri Pirko Multiple PFs may reside on the same physical chip, running a single firmware. Some of the resources and configurations may be shared among these PFs. Currently, there is not good object to pin the configuration knobs on. Introduce a shared devlink, instantiated upon probe of the first PF, removed during remove of the last PF. Back this shared devlink instance by faux device, as there is no PCI device related to it. Make the PF devlink instances nested in this shared devlink instance. Example: $ devlink dev pci/0000:08:00.0: nested_devlink: auxiliary/mlx5_core.eth.0 faux/mlx5_core_83013c12b77faa1a30000c82a1045c91: nested_devlink: pci/0000:08:00.0 pci/0000:08:00.1 auxiliary/mlx5_core.eth.0 pci/0000:08:00.1: nested_devlink: auxiliary/mlx5_core.eth.1 auxiliary/mlx5_core.eth.1 Signed-off-by: Jiri Pirko Reviewed-by: Cosmin Ratiu Signed-off-by: Tariq Toukan --- .../net/ethernet/mellanox/mlx5/core/Makefile | 5 +- .../net/ethernet/mellanox/mlx5/core/main.c | 18 ++ .../ethernet/mellanox/mlx5/core/sh_devlink.c | 166 ++++++++++++++++++ .../ethernet/mellanox/mlx5/core/sh_devlink.h | 13 ++ include/linux/mlx5/driver.h | 5 + 5 files changed, 205 insertions(+), 2 deletions(-) create mode 100644 drivers/net/ethernet/mellanox/mlx5/core/sh_devlink.c create mode 100644 drivers/net/ethernet/mellanox/mlx5/core/sh_devlink.h diff --git a/drivers/net/ethernet/mellanox/mlx5/core/Makefile b/drivers/net= /ethernet/mellanox/mlx5/core/Makefile index 8ffa286a18f5..d39fe9c4a87c 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/Makefile +++ b/drivers/net/ethernet/mellanox/mlx5/core/Makefile @@ -16,8 +16,9 @@ mlx5_core-y :=3D main.o cmd.o debugfs.o fw.o eq.o uar.o p= agealloc.o \ transobj.o vport.o sriov.o fs_cmd.o fs_core.o pci_irq.o \ fs_counters.o fs_ft_pool.o rl.o lag/debugfs.o lag/lag.o dev.o events.o w= q.o lib/gid.o \ lib/devcom.o lib/pci_vsc.o lib/dm.o lib/fs_ttc.o diag/fs_tracepoint.o \ - diag/fw_tracer.o diag/crdump.o devlink.o diag/rsc_dump.o diag/reporter_v= nic.o \ - fw_reset.o qos.o lib/tout.o lib/aso.o wc.o fs_pool.o lib/nv_param.o + diag/fw_tracer.o diag/crdump.o devlink.o sh_devlink.o diag/rsc_dump.o \ + diag/reporter_vnic.o fw_reset.o qos.o lib/tout.o lib/aso.o wc.o fs_pool.= o \ + lib/nv_param.o =20 # # Netdev basic diff --git a/drivers/net/ethernet/mellanox/mlx5/core/main.c b/drivers/net/e= thernet/mellanox/mlx5/core/main.c index 024339ce41f1..a8a285917688 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/main.c @@ -74,6 +74,7 @@ #include "mlx5_irq.h" #include "hwmon.h" #include "lag/lag.h" +#include "sh_devlink.h" =20 MODULE_AUTHOR("Eli Cohen "); MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX ser= ies) core driver"); @@ -1520,10 +1521,17 @@ int mlx5_init_one(struct mlx5_core_dev *dev) int err; =20 devl_lock(devlink); + if (dev->shd) { + err =3D devl_nested_devlink_set(priv_to_devlink(dev->shd), + devlink); + if (err) + goto unlock; + } devl_register(devlink); err =3D mlx5_init_one_devl_locked(dev); if (err) devl_unregister(devlink); +unlock: devl_unlock(devlink); return err; } @@ -2015,6 +2023,13 @@ static int probe_one(struct pci_dev *pdev, const str= uct pci_device_id *id) goto pci_init_err; } =20 + err =3D mlx5_shd_init(dev); + if (err) { + mlx5_core_err(dev, "mlx5_shd_init failed with error code %d\n", + err); + goto shd_init_err; + } + err =3D mlx5_init_one(dev); if (err) { mlx5_core_err(dev, "mlx5_init_one failed with error code %d\n", @@ -2026,6 +2041,8 @@ static int probe_one(struct pci_dev *pdev, const stru= ct pci_device_id *id) return 0; =20 err_init_one: + mlx5_shd_uninit(dev); +shd_init_err: mlx5_pci_close(dev); pci_init_err: mlx5_mdev_uninit(dev); @@ -2047,6 +2064,7 @@ static void remove_one(struct pci_dev *pdev) mlx5_drain_health_wq(dev); mlx5_sriov_disable(pdev, false); mlx5_uninit_one(dev); + mlx5_shd_uninit(dev); mlx5_pci_close(dev); mlx5_mdev_uninit(dev); mlx5_adev_idx_free(dev->priv.adev_idx); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/sh_devlink.c b/drivers= /net/ethernet/mellanox/mlx5/core/sh_devlink.c new file mode 100644 index 000000000000..e39a5e20e102 --- /dev/null +++ b/drivers/net/ethernet/mellanox/mlx5/core/sh_devlink.c @@ -0,0 +1,166 @@ +// SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB +/* Copyright (c) 2025, NVIDIA CORPORATION & AFFILIATES. All rights reserve= d. */ + +#include +#include +#include + +#include "sh_devlink.h" + +static LIST_HEAD(shd_list); +static DEFINE_MUTEX(shd_mutex); /* Protects shd_list and shd->list */ + +/* This structure represents a shared devlink instance, + * there is one created for PF group of the same chip. + */ +struct mlx5_shd { + /* Node in shd list */ + struct list_head list; + /* Serial number of the chip */ + const char *sn; + /* List of per-PF dev instances */ + struct list_head dev_list; + /* Related faux device */ + struct faux_device *faux_dev; +}; + +static const struct devlink_ops mlx5_shd_ops =3D { +}; + +static int mlx5_shd_faux_probe(struct faux_device *faux_dev) +{ + struct devlink *devlink; + struct mlx5_shd *shd; + + devlink =3D devlink_alloc(&mlx5_shd_ops, sizeof(struct mlx5_shd), + &faux_dev->dev); + if (!devlink) + return -ENOMEM; + shd =3D devlink_priv(devlink); + faux_device_set_drvdata(faux_dev, shd); + + devl_lock(devlink); + devl_register(devlink); + devl_unlock(devlink); + return 0; +} + +static void mlx5_shd_faux_remove(struct faux_device *faux_dev) +{ + struct mlx5_shd *shd =3D faux_device_get_drvdata(faux_dev); + struct devlink *devlink =3D priv_to_devlink(shd); + + devl_lock(devlink); + devl_unregister(devlink); + devl_unlock(devlink); + devlink_free(devlink); +} + +static const struct faux_device_ops mlx5_shd_faux_ops =3D { + .probe =3D mlx5_shd_faux_probe, + .remove =3D mlx5_shd_faux_remove, +}; + +static struct mlx5_shd *mlx5_shd_create(const char *sn) +{ + struct faux_device *faux_dev; + struct mlx5_shd *shd; + + faux_dev =3D faux_device_create(sn, NULL, &mlx5_shd_faux_ops); + if (!faux_dev) + return NULL; + shd =3D faux_device_get_drvdata(faux_dev); + if (!shd) + return NULL; + list_add_tail(&shd->list, &shd_list); + shd->sn =3D sn; + INIT_LIST_HEAD(&shd->dev_list); + shd->faux_dev =3D faux_dev; + return shd; +} + +static void mlx5_shd_destroy(struct mlx5_shd *shd) +{ + list_del(&shd->list); + kfree(shd->sn); + faux_device_destroy(shd->faux_dev); +} + +int mlx5_shd_init(struct mlx5_core_dev *dev) +{ + u8 *vpd_data __free(kfree) =3D NULL; + struct pci_dev *pdev =3D dev->pdev; + unsigned int vpd_size, kw_len; + struct mlx5_shd *shd; + const char *sn; + char *end; + int start; + int err; + + if (!mlx5_core_is_pf(dev)) + return 0; + + vpd_data =3D pci_vpd_alloc(pdev, &vpd_size); + if (IS_ERR(vpd_data)) { + err =3D PTR_ERR(vpd_data); + return err =3D=3D -ENODEV ? 0 : err; + } + start =3D pci_vpd_find_ro_info_keyword(vpd_data, vpd_size, "V3", &kw_len); + if (start < 0) { + /* Fall-back to SN for older devices. */ + start =3D pci_vpd_find_ro_info_keyword(vpd_data, vpd_size, + PCI_VPD_RO_KEYWORD_SERIALNO, &kw_len); + if (start < 0) + return -ENOENT; + } + sn =3D kstrndup(vpd_data + start, kw_len, GFP_KERNEL); + if (!sn) + return -ENOMEM; + /* Firmware may return spaces at the end of the string, strip it. */ + end =3D strchrnul(sn, ' '); + *end =3D '\0'; + + guard(mutex)(&shd_mutex); + list_for_each_entry(shd, &shd_list, list) { + if (!strcmp(shd->sn, sn)) { + kfree(sn); + goto found; + } + } + shd =3D mlx5_shd_create(sn); + if (!shd) { + kfree(sn); + return -ENOMEM; + } +found: + list_add_tail(&dev->shd_list, &shd->dev_list); + dev->shd =3D shd; + return 0; +} + +void mlx5_shd_uninit(struct mlx5_core_dev *dev) +{ + struct mlx5_shd *shd =3D dev->shd; + + if (!dev->shd) + return; + + guard(mutex)(&shd_mutex); + list_del(&dev->shd_list); + if (list_empty(&shd->dev_list)) + mlx5_shd_destroy(shd); +} + +void mlx5_shd_lock(struct mlx5_core_dev *dev) +{ + if (!dev->shd) + return; + devl_lock(priv_to_devlink(dev->shd)); +} + +void mlx5_shd_unlock(struct mlx5_core_dev *dev) +{ + if (!dev->shd) + return; + devl_unlock(priv_to_devlink(dev->shd)); +} diff --git a/drivers/net/ethernet/mellanox/mlx5/core/sh_devlink.h b/drivers= /net/ethernet/mellanox/mlx5/core/sh_devlink.h new file mode 100644 index 000000000000..54ce0389cfea --- /dev/null +++ b/drivers/net/ethernet/mellanox/mlx5/core/sh_devlink.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */ +/* Copyright (c) 2025, NVIDIA CORPORATION & AFFILIATES. All rights reserve= d. */ + +#ifndef __MLX5_SH_DEVLINK_H__ +#define __MLX5_SH_DEVLINK_H__ + +int mlx5_shd_init(struct mlx5_core_dev *dev); +void mlx5_shd_uninit(struct mlx5_core_dev *dev); +void mlx5_shd_lock(struct mlx5_core_dev *dev); +void mlx5_shd_unlock(struct mlx5_core_dev *dev); +void mlx5_shd_nested_set(struct mlx5_core_dev *dev); + +#endif /* __MLX5_SH_DEVLINK_H__ */ diff --git a/include/linux/mlx5/driver.h b/include/linux/mlx5/driver.h index 1c54aa6f74fb..29fd4dff1cd1 100644 --- a/include/linux/mlx5/driver.h +++ b/include/linux/mlx5/driver.h @@ -735,6 +735,8 @@ enum mlx5_wc_state { MLX5_WC_STATE_SUPPORTED, }; =20 +struct mlx5_shd; + struct mlx5_core_dev { struct device *device; enum mlx5_coredev_type coredev_type; @@ -798,6 +800,9 @@ struct mlx5_core_dev { enum mlx5_wc_state wc_state; /* sync write combining state */ struct mutex wc_state_lock; + /* node in shared devlink list */ + struct list_head shd_list; + struct mlx5_shd *shd; }; =20 struct mlx5_db { --=20 2.31.1