From nobody Tue Dec 2 00:46:21 2025 Received: from SN4PR0501CU005.outbound.protection.outlook.com (mail-southcentralusazon11011071.outbound.protection.outlook.com [40.93.194.71]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 154C22343C0; Sun, 23 Nov 2025 07:23:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.93.194.71 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763882615; cv=fail; b=aTGayoh1viDFVxC62kbw5UNTEh1N8KAA84qNpmTn+ptahDM+IwKRUqfF5t0PB2H0MbjkZhh0fC6HDD1YuCSpwUP2pA78Vo/LgbhkEl8BQpR0ZRPe9NjxHWIoNurrW9p6pgG5sPkxHaTgFOKchG5RVfsXcZu4JRCbUyYLNAAvRGs= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763882615; c=relaxed/simple; bh=P8W0FIsXR1/VWMEyIG4knFrRhHdsOvI7EcP/vxGKWms=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=qpARWDZX5ZnMxftv1gl3vuea0wCGaD9sH6JjqU+Ixp6yCckzrhRCK20v8PrPI1tEkdgS+m/PpUE14IkXVvohokyyvj/11LvbFed29rt3ukcF1uxGJJ3OFx8RxPYFbn6jWGlBsY15wkiVOPCNFgqUdpAhcGY3HVwuer/lh4J/uLk= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=E5T1XH8W; arc=fail smtp.client-ip=40.93.194.71 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="E5T1XH8W" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=Mvmh0PC2lmhpIl9n38YOi6eLk7rmiesQvOyRW32/qcnAcSOVGapKfzmdtuQCUJl7Llrl8w0tSU2eYB/SyjBpjlN8lIG4W8tMZKf6UC0GG2je+A4nlt/U8UW7Gyzj22Lh0DJhWl0NnLNcUiXN+DyFpyUKfEu1SnzgGKtJskJCE1cxqj041PDGhmuctQ6SrNIiH0aJC5YdpPqUPIJoiOSBz1YTLizFuP9q5dsw02kuBSTsto4rNfNapbhuH659EWw3ZhLckOnUk8nesaM7CguEHULg251RpbMru52C6ZyYNWJUIEhXIsE87w1dvR0WE3fiVou9KZNlu/YIuKmIcPepuw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=kglGhXi4BWERJc11i4b/YsEsnv0Fea8SDE586jjlVTY=; b=sTNXaYpmO2bEtLFSB5N2UEW+mxMA10VMbVdMUCfxSoX1lfgDPQa5ieN9xX0JeYrAl2zHaJ82IwdKl/+qeZCEjAtv8h7XAwSK446HF3IrU0+2huGZgzeJADUPF46FFIBN9U75kPa9muD4FL+lSWIOE4sM2GsFYTwYh8bHC3fwEZrFS43PYt05q42rYdYObY+y1B+8rPY9fCn/p8f8k/+cQ+TvW0kkkE5ITVLRLMDMZETri81QpBpc3iY0CkPbVnjpW/djPdCWEmZSg4l+wCX2pKxOjKj9qA+QYSy138bdt8+atcr6nJSJbcmcVWuTWMIC6cUBBL+VF1UbEZ/0ytUA5g== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=google.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=kglGhXi4BWERJc11i4b/YsEsnv0Fea8SDE586jjlVTY=; b=E5T1XH8WQ/uW/q8ORe7ph2VwRnwBHiIcoY/nltknWUgE1eSrBE/CwldD6phjv/IuUMcvZvNchH0mYw11LPK0BfK8IjJ/EmFCKr1YvuAN/Fn0fiCjr0Dd2MMDtOHyJlgGuA5wXTzdVm88P7WMBXK217caahtnEnuw3WQTAI9h00gb7O7DgqS4Uu53BbtwtWkYYOFkqro3VouCtJLtUXPKahBfCfgXF6/ekaH7GR7tDk0aYU70XFrdOWk8SJ5AQQJb+MZdFzT78jZ9JYJuqyoNF+rejb6VE9c69T2uldUR5F2W+ps/OzT1j58SnkpzVwsl57jTn1UaeYFPAA6Pxtmj+A== Received: from DM6PR02CA0142.namprd02.prod.outlook.com (2603:10b6:5:332::9) by BY5PR12MB4258.namprd12.prod.outlook.com (2603:10b6:a03:20d::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9343.16; Sun, 23 Nov 2025 07:23:27 +0000 Received: from DS2PEPF00003442.namprd04.prod.outlook.com (2603:10b6:5:332:cafe::2c) by DM6PR02CA0142.outlook.office365.com (2603:10b6:5:332::9) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9343.15 via Frontend Transport; Sun, 23 Nov 2025 07:23:23 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by DS2PEPF00003442.mail.protection.outlook.com (10.167.17.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9343.9 via Frontend Transport; Sun, 23 Nov 2025 07:23:26 +0000 Received: from rnnvmail204.nvidia.com (10.129.68.6) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Sat, 22 Nov 2025 23:23:18 -0800 Received: from rnnvmail201.nvidia.com (10.129.68.8) by rnnvmail204.nvidia.com (10.129.68.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Sat, 22 Nov 2025 23:23:17 -0800 Received: from vdi.nvidia.com (10.127.8.10) by mail.nvidia.com (10.129.68.8) with Microsoft SMTP Server id 15.2.2562.20 via Frontend Transport; Sat, 22 Nov 2025 23:23:12 -0800 From: Tariq Toukan To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Donald Hunter , Jiri Pirko , Jonathan Corbet , Saeed Mahameed , "Leon Romanovsky" , Tariq Toukan , Mark Bloch , , , , , Gal Pressman , Moshe Shemesh , Carolina Jubran , Cosmin Ratiu , Jiri Pirko Subject: [PATCH net-next V2 01/14] devlink: Reverse locking order for nested instances Date: Sun, 23 Nov 2025 09:22:47 +0200 Message-ID: <1763882580-1295213-2-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1763882580-1295213-1-git-send-email-tariqt@nvidia.com> References: <1763882580-1295213-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF00003442:EE_|BY5PR12MB4258:EE_ X-MS-Office365-Filtering-Correlation-Id: ba5ae0ca-2970-4bae-2df8-08de2a6131b4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|82310400026|376014|7416014|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?3yEDzQD/YSiOEzj3Hbj0iJqQiOokHzR+C8Kh7Fch+mAeZ+zvzW1xTzmd0skg?= =?us-ascii?Q?w2nRkVuimsPicstvKepx2GOcnIezxvXWafis68qw0brsBeyyRej0OY316brH?= =?us-ascii?Q?oVLxlD7a72gpu5hOgGNsdOSUgiZKxhiKj1NTeRC6YwAYdVICWf06UWi9AqIq?= =?us-ascii?Q?SmoUH1+rcnCkD4MSJTKeFH3rPsjs6/u8wv7pw8+QTwT4GeHfx1WhX4bnLxhA?= =?us-ascii?Q?i9+xIfXMIrpNGy7hpVZeCzgS2luJhR0rwfx0W7bRW9nrV27vqhed2OpzXJYv?= =?us-ascii?Q?fSd4tldUMRIyyAKd6PYN1sAZ58x1wqEPZ92ovyHwg3dXlcq/pWtGlOAnC/Y+?= =?us-ascii?Q?69DGhcENcfy1CBVeabeV+HaE9tG7d33QzR2fpkYhMSJJP12TA/GIWKQkvzYp?= =?us-ascii?Q?433kv0iskHClV6W6QqVEYOy57XsmhmbBre6VV3yUuIPUj0HgJ8/ydqiGVijE?= =?us-ascii?Q?S60R7DxPaG2qtHhexviN/7HEPDfOKUWCscMLHPJN6j5daPabFaWWSt+7CT+c?= =?us-ascii?Q?mtI8pCXsE0sB+OrbU5VK92iF6K1PoK+JMQzNQVl8t14xGn5lR3tMhGrgPGpI?= =?us-ascii?Q?fGmKTv1FhlMb/6GCENQhBqhq3laBwkwYz4/ksVfY+IvWQrzUsQYdB7nf1xK4?= =?us-ascii?Q?POVKiZ+hPC8eRZ6Q61AmE06fZWX/Vi2b+1D11WVV9FCuXTWo91M2DBCj1Bdb?= =?us-ascii?Q?9bLT1dwqwqumLlG4TmrDGiOLXeIGxAYEDqmKorwTekh+ts1bTrYMRX/UI347?= =?us-ascii?Q?7g/jnWNUdMBo4HvPjV7jp6RMrIPmexzspDi7pWo7DijQD5viQEFgk6vrv7Fk?= =?us-ascii?Q?xo6Z8ZNrHJMdCKQiPloq/xW91DPxAKfbwMvTWHtA/K+2DvROadB0ODa7jDgQ?= =?us-ascii?Q?OQJORha+ISlsGLGAn5p9Lq28AQIQrAA8L0bgRmbBTJLKC8j4oP9/AEeWA8xB?= =?us-ascii?Q?AEb0LTAVP4XC6jx5x6XAcSMqMWejdMAdmVluwuWg2ur3QbbOK3ipTKblrB5m?= =?us-ascii?Q?HBTAdyRIm0lZE6xgJxTg7IjIWcgYSksU0g3vRQEST1ePXlMKKSVO+RBz2gG9?= =?us-ascii?Q?pesOP2obIBI+RLCUFzIBpYe+Y1fDBD9p8NwwYdPXVOq7Pe2qJOFRTefXHJgC?= =?us-ascii?Q?yPqHGzXJiOlA2XAq5ZSx90YH03sWHMDACx38RtFmbBldxqOtcbF6o9JmkJ12?= =?us-ascii?Q?y0wHtnTOznAKXMxRmXsA1yGNvp6ypsUeZav7HeVf1AA4kUXpuUFCT7HMIU4I?= =?us-ascii?Q?OERj4qCNszIebwlOUe0AcgyuyoPJfbALOBKJMiVoDtdlE/NAb1jIc8Obk+8X?= =?us-ascii?Q?8FMylpdFSYI3KuiaWWYbotuvPSEwm71xhUo6lJU92eAoGxD7Jk2CzUMJGsSe?= =?us-ascii?Q?wjTTbrSDwtRxEoETCA3TQxoplb7VW9NznW5HiuFiMbdZE8sVn3w0Cc5J/Jzz?= =?us-ascii?Q?a4XFAeVtaY5eBLQxxnoOoLKlxyZbf2b0NkRvSWO1Td2Z0qMvn0lnp956cq7z?= =?us-ascii?Q?twtB9CNJbbV8uS+lWkFUPZL9MF6DzU541xqFztfWNLJluNIA3RhMncfyjILI?= =?us-ascii?Q?suK95AtN2lHHU9sY0H4=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(82310400026)(376014)(7416014)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Nov 2025 07:23:26.5793 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ba5ae0ca-2970-4bae-2df8-08de2a6131b4 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF00003442.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4258 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Cosmin Ratiu Commit [1] defined the locking expectations for nested devlink instances: the nested-in devlink instance lock needs to be acquired before the nested devlink instance lock. The code handling devlink rels was architected with that assumption in mind. There are no actual users of double locking yet but that is about to change in the upcoming patches in the series. Code operating on nested devlink instances will require also obtaining the nested-in instance lock, but such code may already be called from a variety of places with the nested devlink instance lock. Then, there's no way to acquire the nested-in lock other than making sure that all callers acquire it first. Reversing the nested lock order allows incrementally acquiring the nested-in instance lock when needed (perhaps even a chain of locks up to the root) without affecting any caller. The only affected use of nesting is devlink_nl_nested_fill(), which iterates over nested devlink instances with the RCU lock, without locking them, so there's no possibility of deadlock. So this commit just updates a comment regarding the nested locks. [1] commit c137743bce02b ("devlink: introduce object and nested devlink relationship infra") Signed-off-by: Cosmin Ratiu Reviewed-by: Jiri Pirko Signed-off-by: Tariq Toukan --- net/devlink/core.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/net/devlink/core.c b/net/devlink/core.c index 58093f49c090..6ae62c7f2a80 100644 --- a/net/devlink/core.c +++ b/net/devlink/core.c @@ -178,9 +178,7 @@ int devlink_rel_nested_in_add(u32 *rel_index, u32 devli= nk_index, * a notification of a change of this object should be sent * over netlink. The parent devlink instance lock needs to be * taken during the notification preparation. - * However, since the devlink lock of nested instance is held here, - * we would end with wrong devlink instance lock ordering and - * deadlock. Therefore the work is utilized to avoid that. + * Since the parent may or may not be locked, 'work' is utilized. */ void devlink_rel_nested_in_notify(struct devlink *devlink) { --=20 2.31.1 From nobody Tue Dec 2 00:46:21 2025 Received: from CH1PR05CU001.outbound.protection.outlook.com (mail-northcentralusazon11010054.outbound.protection.outlook.com [52.101.193.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0C766296BBE; Sun, 23 Nov 2025 07:23:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.193.54 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763882621; cv=fail; b=TCU1rVipIR1A7PI3Y5VYKwYBfO3O+nSAVDUaDNiaKNojepkEqA1wKJ36gPcu6a/MQSA0SDFX5o03dvANn6Ovw585WreXosm9p4C72Um4MxoMvgl15vt9oudtzgfWW5XDmJTwX924uxPti5rGHiYJ3tyw7BJF6oechYKYDt2vREY= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763882621; c=relaxed/simple; bh=Qkb6pNUnyaj/v81+ET9DNUBziUveBX//R0BNmlCVy9g=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=cwkJHTCsW3OroE5qdpyLZMW+o/YC/3CAAgO9L5Eu0ntFFjb8w/gFswXEDIMxp66AvN5GLXwmay2i9ErC1Xer3SYdHJUX0TW231K5YnULAFsWxUc34xqWz/udEoGtxkAIbRaTPMJIqVx4SN75TaTuyuCA/7SN3BLnvxyNlFWr2UY= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=oBBFkxnx; arc=fail smtp.client-ip=52.101.193.54 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="oBBFkxnx" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=IJg3bOYuY6Y3HjXPY8Ewa/4/5j8Nhtg51WezMRbbrjbWYINoR3DynlyI6SHhbrh3WAwMwZDSDjpM/H42QcQ3FjGUxWIUsA+u2+BDZJFPGadmXg6svD5vjm+gUZm4jkmqEOtJ8Cq3XuHFtopyIfYF/Qh95T0mVR0DN+hn1k+bLMVCBUiBOleAR6ive7PS22NYpM8PwFy9iP4syPcH0vuxutRXXhH16ukska4kO1c/GaxU6taJzz9/wYdc648qmJK0j8MI1WDB1JKt4DcHeqjggPfjp5SBgArxVbgxSK65JpcFLOTysL6guv3qBlXc0mPjbQUFHgs3pggs2NTqsKBpuQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=dB0KCazrhTv9T4oxZp74zais9T3F8hs6VqNcq2QNfQM=; b=A43m7XZpGNG/8tDF4D00iwfYwSai1JeMaCKwZt+CN44Aa2lWVYGYNdsld0kFqWDb9SIKXDPqEJZTvkcsFZAuddcUgB0/WCJ6GvFGh3Pc8Fbp6nEBg5enTRYZs9iwo1aoOy2+rhR8iqe3KFWSe1FY/xeIYKPXJHfH65UL6xmqy4oN/qsLlefpu2xFywS58sXCeSjnOat0nZjJAfq96mqL+o+IIAPTcNc74OmeSZlXImgEJ6EP9T5+ezlh9DVOvOIr2CseogPOkF78AAO2YDD/8giglQcDPQKRl+zzcLLzOTjAVKJ8g98BHJ6ARiD9zvoHtkVTDp0CdWWiqC9yBSgGtQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=google.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=dB0KCazrhTv9T4oxZp74zais9T3F8hs6VqNcq2QNfQM=; b=oBBFkxnxYy2oTRfYoGYEEgNw5Bjm6sEH7+z/ZN9BO64HSVlpaixpXGoXZRdSaJqbmpB/hUo/vsmlFwF7QDvjyg6VU7pgUi4FH39FJp7msbHOPsE16MHFms1Qo//ldxXovVvnCjXHs3ccsZSHfMjL/f2ohgA+mJwQ6pexu1rb2aeGjgPMpmdsegO6G78HFd3NamXREvzHvN6iWMJgzUaUDxPW9TpWcr0+9rtSbDJD/aFYwgGdHdMYjlajILaNSRW4ojC54mponCeiM3nUSRKi5geV5IiUSk4x2fMGtPe5ZloZWONNyVISxj80ZJnh0MTp3cPhoEtRswUoLMwz5nk4Sg== Received: from CH0PR04CA0021.namprd04.prod.outlook.com (2603:10b6:610:76::26) by CYYPR12MB8891.namprd12.prod.outlook.com (2603:10b6:930:c0::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9343.15; Sun, 23 Nov 2025 07:23:32 +0000 Received: from DS2PEPF00003447.namprd04.prod.outlook.com (2603:10b6:610:76:cafe::a1) by CH0PR04CA0021.outlook.office365.com (2603:10b6:610:76::26) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9343.16 via Frontend Transport; Sun, 23 Nov 2025 07:23:32 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by DS2PEPF00003447.mail.protection.outlook.com (10.167.17.74) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9366.7 via Frontend Transport; Sun, 23 Nov 2025 07:23:32 +0000 Received: from rnnvmail203.nvidia.com (10.129.68.9) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Sat, 22 Nov 2025 23:23:24 -0800 Received: from rnnvmail201.nvidia.com (10.129.68.8) by rnnvmail203.nvidia.com (10.129.68.9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Sat, 22 Nov 2025 23:23:23 -0800 Received: from vdi.nvidia.com (10.127.8.10) by mail.nvidia.com (10.129.68.8) with Microsoft SMTP Server id 15.2.2562.20 via Frontend Transport; Sat, 22 Nov 2025 23:23:18 -0800 From: Tariq Toukan To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Donald Hunter , Jiri Pirko , Jonathan Corbet , Saeed Mahameed , "Leon Romanovsky" , Tariq Toukan , Mark Bloch , , , , , Gal Pressman , Moshe Shemesh , Carolina Jubran , Cosmin Ratiu , Jiri Pirko Subject: [PATCH net-next V2 02/14] documentation: networking: add shared devlink documentation Date: Sun, 23 Nov 2025 09:22:48 +0200 Message-ID: <1763882580-1295213-3-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1763882580-1295213-1-git-send-email-tariqt@nvidia.com> References: <1763882580-1295213-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF00003447:EE_|CYYPR12MB8891:EE_ X-MS-Office365-Filtering-Correlation-Id: e8b08e2a-b99e-4724-11db-08de2a613531 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|7416014|376014|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?o8QI8FrrPNMjFIKJhxxr/UL3S6S8THTn0zfAuYgg0JeMIlPZTjmGLLNASuDz?= =?us-ascii?Q?l8aCH1PQvz3/kiv8Vf9Pk9nsSNoIbxAQkZIxVIb7x5whHSng50JQw+rSekdV?= =?us-ascii?Q?10D7zD9w0PZ2zJovFeLBd7+Q0TP9+yEP/nReqTdiUVumv9omKIpEkGGuKgZ5?= =?us-ascii?Q?vh2AT6tMtwuUWNIIs56bLNObcKYwSYbN0RCrv7SPzG0yke+mj6mLQ+hRZde7?= =?us-ascii?Q?4bLsibpA5pYc43rJS17wAWv77vo2pzzuHGNlW0LzNIdZPfke6mbhFGU//7NI?= =?us-ascii?Q?+vrplpSw2oYx3ZBOkIKI1B3rDnSEc1xqkb9NiOM3nO8MkjU4iY0tN50yuHqN?= =?us-ascii?Q?6e5iUK7OaE3Fhl0KhI4kGZFDGKwwGnBmCRMCS6YZdRzHa2QY9o8lMfOWnI4B?= =?us-ascii?Q?fRivcFdEDeFXMaiqEZqB2ne07PEDM0ucSLyHtwLYkV2ZuoMSgqXwIFMDQjMy?= =?us-ascii?Q?bIN3fxdsTOweq4T9fPQO7KmADdsIDomV/+sp77Ag/G6OAjV5xA86q2r9hcFx?= =?us-ascii?Q?vgfiph4P2n3EfFmyo3m/ZWSGnohf7vc/F/pKcsutI97RxPEFM6t/AVn/VPxM?= =?us-ascii?Q?7qvWfTgBBaoo68IrQmoGYdWcoFrZokMNy5OfTtNQKdBHtP+IOSBVvAJzxRw0?= =?us-ascii?Q?gmJMvLoIXP+PSscPorKs7djMtg0ncs58bNUpg/a2CpSBrMNk+ozuICg9ppGX?= =?us-ascii?Q?52bS4Gg/vBOjiMeYSnCxA3ZCRxpcolRZdMnmdWPfiqEpZnbcStgVUiys/geV?= =?us-ascii?Q?oK5yqnF0lERokT4llqcOeTKNCt039EHLOOizetsC0oj6oCx5Y9xGjewOsvz1?= =?us-ascii?Q?okuu4WwtdXrxA8j4p2xZgawP+b8NgYNyPfWMDGAel9OewKeyxeH+n/+fsFfc?= =?us-ascii?Q?mFEkCHomoxzjwxPErX5Og4/b7QbxGgBk1P8eChgVBLNIfH9QOuLqMBILXGzL?= =?us-ascii?Q?U/O0eI/7wregl7BFA2xTZ7cPVaL6V71a7p5IzIweov+e87oEXxjv0qSo+F4e?= =?us-ascii?Q?/1MEfGdvZusgShLNr4CoKIGKl8C7RRRtw/xFaxtIFxE+yPUgSR1eFYMt0pZj?= =?us-ascii?Q?cNyu04SJ40D9iu20RyTVmpMhsUWfYVHZemQZbFKdVo9ywIfhtQdBrwdJGPvA?= =?us-ascii?Q?3/S596brXYzaXe0JzAFCkN76qe5tMB0Sveb97iG0z0ClFnZZ35Pl92nvZ2c+?= =?us-ascii?Q?wsx+tuNltud9OwB6HZ1lCMZHyJlZkh50nWQ271SmHzBpms9gWpFMN86Vfv5K?= =?us-ascii?Q?7xVTlzSl9D6faxyoR1mO4z9+R19/5Fi+l8Ppkx+u2GfZ8IDkBL12V898m9FX?= =?us-ascii?Q?OozDMLQEQUKf8JzyaLIrsCt/Nff1oTHR0/0EpkupbyTlrmO0ELXfQIBzyVH2?= =?us-ascii?Q?ZD4m2c2t/c7LsqCt+6nCJztNMqYfrR8T3EaHqWMhUjwc08PE+g5f26/zc/38?= =?us-ascii?Q?4wa/7SAeEBBvJTz1NFPRae/1QhjKOVVCbbdeMFeHlXKjYoYclhPt0cl5OMYr?= =?us-ascii?Q?Y+2kZMhDyRRrGRvB0rVR3SEgQd/t9Y1ghDWB852ItKPPink9gf6o4vQjQWcu?= =?us-ascii?Q?ms3gkcsKxmKJkHGreYg=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(1800799024)(7416014)(376014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Nov 2025 07:23:32.4242 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e8b08e2a-b99e-4724-11db-08de2a613531 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF00003447.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CYYPR12MB8891 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Jiri Pirko Document shared devlink instances for multiple PFs on the same chip. Signed-off-by: Jiri Pirko Reviewed-by: Cosmin Ratiu Signed-off-by: Tariq Toukan --- .../networking/devlink/devlink-shared.rst | 66 +++++++++++++++++++ Documentation/networking/devlink/index.rst | 3 + 2 files changed, 69 insertions(+) create mode 100644 Documentation/networking/devlink/devlink-shared.rst diff --git a/Documentation/networking/devlink/devlink-shared.rst b/Document= ation/networking/devlink/devlink-shared.rst new file mode 100644 index 000000000000..8377d524998f --- /dev/null +++ b/Documentation/networking/devlink/devlink-shared.rst @@ -0,0 +1,66 @@ +.. SPDX-License-Identifier: GPL-2.0 + +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D +Devlink Shared Instances +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D + +Overview +=3D=3D=3D=3D=3D=3D=3D=3D + +Shared devlink instances allow multiple physical functions (PFs) on the sa= me +chip to share an additional devlink instance for chip-wide operations. This +should be implemented within individual drivers alongside the individual PF +devlink instances, not replacing them. + +The shared devlink instance should be backed by a faux device and should +provide a common interface for operations that affect the entire chip +rather than individual PFs. + +Implementation +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +Architecture +------------ + +The implementation should use: + +* **Faux device**: Virtual device backing the shared devlink instance +* **Chip identification**: PFs are grouped by chip using a driver-specific= identifier +* **Shared instance management**: Global list of shared instances with ref= erence counting + +Initialization Flow +------------------- + +1. **PF calls shared devlink init** during driver probe +2. **Chip identification** using driver-specific method to determine devic= e identity +3. **Lookup existing shared instance** for this chip identifier +4. **Create new shared instance** if none exists: + + * Create faux device with chip identifier as name + * Allocate and register devlink instance + * Add to global shared instances list + +5. **Add PF to shared instance** PF list +6. **Set nested devlink instance** dor the PF devlink instance + +Cleanup Flow +------------ + +1. **Cleanup** when PF is removed; destroy shared instance when last PF is= removed + +Chip Identification +------------------- + +PFs belonging to the same chip are identified using a driver-specific meth= od. +The driver is free to choose any identifier that is suitable for determini= ng +whether two PFs are part of the same device. Examples include VPD serial n= umbers, +device tree properties, or other hardware-specific identifiers. + +Locking +------- + +A global per-driver mutex protects the shared instances list and individua= l shared +instance PF lists during registration/deregistration. + +Similarly to other nested devlink instance relationships, devlink lock of +the shared instance should be always taken after the devlink lock of PF. diff --git a/Documentation/networking/devlink/index.rst b/Documentation/net= working/devlink/index.rst index 35b12a2bfeba..d14a764e9b1d 100644 --- a/Documentation/networking/devlink/index.rst +++ b/Documentation/networking/devlink/index.rst @@ -68,6 +68,9 @@ general. devlink-resource devlink-selftests devlink-trap + devlink-linecard + devlink-eswitch-attr + devlink-shared =20 Driver-specific documentation ----------------------------- --=20 2.31.1 From nobody Tue Dec 2 00:46:21 2025 Received: from DM1PR04CU001.outbound.protection.outlook.com (mail-centralusazon11010046.outbound.protection.outlook.com [52.101.61.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C44942C028C; Sun, 23 Nov 2025 07:23:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.61.46 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763882624; cv=fail; b=dJwYNmqxLYnqr1Ehxt+00xYCoTcvJRYXg4wW3DJwIhAMTjyCEHHDW3BRbxQvrMvh/pBiarP+6PL87GoKR99KKt4++xlT0P8+BqJBpcdM5ub2JnqrxnpoyZL8AnaG9w7mSggx4i81qcpLOFJBqg6zzX6MMc8FbHflxNwxkYoTUAo= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763882624; c=relaxed/simple; bh=TR6J5kaeMnMHt+COoNaLdOk/eQgwymLaKE8/E4+L7Mw=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=ggajgqrazIxVWXH11g3XnBRYC/fnkjOYekrNfccXlaL2HRL6TkuZuAFBMMZ6KEsEcvdg/k0KOPFFg2OmaGAi7huIw6gXjwSOTcofNXHlHngiDmrEfwoOcnzv9iVWSyYYBJn+EvxU+HL49wT2Q+LKStAb/VXHaXj7DbINF7ofJ14= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=BIVJeMb+; arc=fail smtp.client-ip=52.101.61.46 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="BIVJeMb+" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=cEKokqASazj4pHB4fD+3Fv+dmHoxEd+z5Ct7vtlWqFheZ6T6kFrAh/C1AyZk9uDnZL98NWHE1cGnULHDBSMbflfzN0p7pbOR9V8bRMhSpgVjwjnHrNpv6FQlShUPPrdxYe4okP/W0CXMiVUKbNgFy6smEegO71eW6+adUPLzSjXRsLFyiEwVBh8s7wevpgUrMjSg0VgknaVLTMbTCZaqLzJJ2EU7ecIiXrtNBWwj/W/20F4SNnaNAzfXuwsisrNRv1uISibm0deQAGcy5Hy/XILHuGEi6f5FMjY1SQt5Pco5Fuvi60qdjB1CrnXQQ+OTXHDspFIo1NF7pq4tl+pXug== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=3CdlQFXorOD2C7oWz685wggWy9NmZxX/sOcpJpJC7aM=; b=oqEuZq8CeNtHBTc3eA1+zem/QJxEqL0zhljmUTRQZgpRZftFLoI0IDigisKaXhn0MUbsFfC3thHrkexk/lSIIvoU2LSHRftKSFGzQ8jmyErAeFNTCdcCxpIO7LoVKznupRzOi5CKYFkxubD2N1P0aAddxZIi4SmrbKDkHKeX3lDHJRGfLGYuVvgz+j/qf33tUX1pBP6onCKhQGByq1+YCKbvvWgsbvQ5YZeo/LbYsmDWrDuR+rFbdBzMfQ+ErYXNF6jzg5HrWYMYwqzS++hD2U+DMGjGvIRIoc047l2/mq9nkrFF7an/yYR3iD5ru1/4Ze8dmrUb/i04NdejY/FkbA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=google.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=3CdlQFXorOD2C7oWz685wggWy9NmZxX/sOcpJpJC7aM=; b=BIVJeMb+DWsJXCXolRXcVitFvTS8izM2cpwFTnMVvfN+4M9UAZBeZna6w6dsjE9vsyp2AIagrAE2c3d1nmrG3nrHpAVwkN6EVUebwtooq4LciEmh2XaaWl2r/bn0nLmdHe1QSP/ANT25ZUMD9Wr53GoXCYLkYVwRh914C9VzrJ3QYuiZiwwAWSq3ztaGmyzkyfKM4xBrWI38YNLYOaOSlSYU7sNxrLFsojujMl6cma4qIn0sB9BA6O0YP082bW09P3w/jknFKO1pALcgoXmg4oiHn+XhWV/l3oy7YuIKXnQ9t0hQ9OYblJTmtxhtWl5eojYxSb/Lss5IEeBAUGoY6w== Received: from PH8P220CA0025.NAMP220.PROD.OUTLOOK.COM (2603:10b6:510:348::9) by BL1PR12MB5753.namprd12.prod.outlook.com (2603:10b6:208:390::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9320.15; Sun, 23 Nov 2025 07:23:38 +0000 Received: from SN1PEPF000397B0.namprd05.prod.outlook.com (2603:10b6:510:348:cafe::e5) by PH8P220CA0025.outlook.office365.com (2603:10b6:510:348::9) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9343.17 via Frontend Transport; Sun, 23 Nov 2025 07:23:52 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by SN1PEPF000397B0.mail.protection.outlook.com (10.167.248.54) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9366.7 via Frontend Transport; Sun, 23 Nov 2025 07:23:38 +0000 Received: from rnnvmail204.nvidia.com (10.129.68.6) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Sat, 22 Nov 2025 23:23:30 -0800 Received: from rnnvmail201.nvidia.com (10.129.68.8) by rnnvmail204.nvidia.com (10.129.68.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Sat, 22 Nov 2025 23:23:29 -0800 Received: from vdi.nvidia.com (10.127.8.10) by mail.nvidia.com (10.129.68.8) with Microsoft SMTP Server id 15.2.2562.20 via Frontend Transport; Sat, 22 Nov 2025 23:23:24 -0800 From: Tariq Toukan To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Donald Hunter , Jiri Pirko , Jonathan Corbet , Saeed Mahameed , "Leon Romanovsky" , Tariq Toukan , Mark Bloch , , , , , Gal Pressman , Moshe Shemesh , Carolina Jubran , Cosmin Ratiu , Jiri Pirko Subject: [PATCH net-next V2 03/14] devlink: Add helpers to lock nested-in instances Date: Sun, 23 Nov 2025 09:22:49 +0200 Message-ID: <1763882580-1295213-4-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1763882580-1295213-1-git-send-email-tariqt@nvidia.com> References: <1763882580-1295213-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000397B0:EE_|BL1PR12MB5753:EE_ X-MS-Office365-Filtering-Correlation-Id: d325884b-bf2b-4972-015b-08de2a613886 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|7416014|36860700013|376014|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?nb9ok7yFb7XlL4pZWJWdwqPA0lqhZyDCnKdqTG9lXBdKGE0AI18K6CUfGoIV?= =?us-ascii?Q?Ikpr6ngj3ZhaH0sFRKXPLxpScVH08XXdKAVkjGtKBZ54XYsztFfXTSHM9+ag?= =?us-ascii?Q?KpqIRdb8elhOQZQoWwDwjUT1fTyCizPXnc6NT6S/r6a2d3iiB9bD0Fz3lxp9?= =?us-ascii?Q?fW6QQAZRT4a3o4ZdkuRRhztJhw/LIgL7dysBRFZFaK1ihFq4bwLZHPWO2sxy?= =?us-ascii?Q?+gZLSm1H1brBQx7rFUpO4Kz7epMFIboJmsWaGsksLp9vzJc6tmBN5vmzUGdp?= =?us-ascii?Q?VdOTROLFdlqwEA07HBb/vWfoCrLWMD6DRQDrWA+sQo9WJrs78VG23aH/2yCV?= =?us-ascii?Q?LQuYmb4JrXU1sqxLAnn3TG+oRz2BXpSJqwwA6tvQyReMuvnSLY/oWQYayZg4?= =?us-ascii?Q?Wwo2KBX5yrmY/sNxRVxQGkW3cmcI7g/3YOwSQ22TXcsn+MfOzJLPArUNWKxb?= =?us-ascii?Q?/aUjb139lrFvDtjPo2Xyvur+QYS5CifUDhS+BwiyQNCl4p+joNB+anfpHk/i?= =?us-ascii?Q?70b/AH2MThzwXPP7IAchcNml/0We4ucHDqiIwvnQ2nJ87y0PBCfsbICKvDms?= =?us-ascii?Q?7rbGYPXXxK+WfeT3fbvrArnVw0ofp2PjNEzAWL4PzHtKmVgUThSxXZaPEVUQ?= =?us-ascii?Q?G/iSBZX05YpJrW2n1UgV08gulz/NL+rIb/KxcsYlBREVY5DPv4Fj3iDe0v7b?= =?us-ascii?Q?XeJj251bBkL72WyiUxoUIyBRNSeSmu5DEwlrevbgDxLzJTrOIV8tt5qp75yl?= =?us-ascii?Q?pbNVhxWamorUTWwdv+iuXMZwYTptanaAYnalzJC6d7CMfgfWUpmZGcIkIWla?= =?us-ascii?Q?NOqpg3fmFKZNUcoV3n80qu8dXlUkblirz69iUUjJ6dqnuQAA0ocpzkbiyRZq?= =?us-ascii?Q?2Mq6kun6m204WE985DDMkc2lz9f6ODi4TvHLTEhb5BEcxyuT5ziMud0Nw1EG?= =?us-ascii?Q?4tr53/ZCHA0B18vxM7DjQL2PkktUeiVZGRmrlqCVaQ4qm6Kw5px6J0tpkbH+?= =?us-ascii?Q?JYlB4nIQw3dMmrgCd+6gBTznwdFAFNPrDLzzaapfJ/lgazoZcVFTwGjmm4MI?= =?us-ascii?Q?8OoAU9P0vw8caYPQuqD2JL7kEwL+m3WoP7X3j8PROEmZZ1eYZxWuJbOvnsCs?= =?us-ascii?Q?Nj7PXkWu1ShOqXEFA9FzIgOeQTmNqEP6JuBAoEq4zuSqpPQ+Woy/vd4g6JML?= =?us-ascii?Q?IVVQjAv3WzFExAKNXiTTTpVQR5E8N4TszBeVQ61ZJFNahE+Wn7YyCIKJa2K+?= =?us-ascii?Q?R0cveXlmvALLRk5ptouzRt1iJ6Q1ikK+wiAjL1XsQuZDjruEYSOCwix1OfmV?= =?us-ascii?Q?j3OJsWs0Q/oG2Zm+J6bGzvo6HNrZo5qUDykRoI5xqybWzklYlpm9gWopyu/Y?= =?us-ascii?Q?FJcESYFF2w79KaSsow6x9bvbGFOEdEEGoNV1+gKt7utUS1JygpnXadeN4jhN?= =?us-ascii?Q?ZjKJl1urfp5MqAYcq/68+1olrUkgwA9diG66r7Jb2xoLy+JMhh1xrOuvLvhj?= =?us-ascii?Q?N5j+27yVsbHqqB1cQVFLiEPXM16d3HNCNc8g0KvYcjMduH2K/j6ayiwnu20x?= =?us-ascii?Q?g0vTO7eQlzfGJEnylN8=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(7416014)(36860700013)(376014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Nov 2025 07:23:38.0231 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d325884b-bf2b-4972-015b-08de2a613886 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000397B0.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5753 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Cosmin Ratiu Upcoming code will need to obtain a reference to locked nested-in devlink instances. Add helpers to lock, obtain an already locked reference and unlock/unref the nested-in instance. Signed-off-by: Cosmin Ratiu Reviewed-by: Carolina Jubran Reviewed-by: Jiri Pirko Signed-off-by: Tariq Toukan --- net/devlink/core.c | 42 +++++++++++++++++++++++++++++++++++++ net/devlink/devl_internal.h | 3 +++ 2 files changed, 45 insertions(+) diff --git a/net/devlink/core.c b/net/devlink/core.c index 6ae62c7f2a80..f228190df346 100644 --- a/net/devlink/core.c +++ b/net/devlink/core.c @@ -67,6 +67,48 @@ static void __devlink_rel_put(struct devlink_rel *rel) devlink_rel_free(rel); } =20 +struct devlink *devlink_nested_in_get_lock(struct devlink_rel *rel) +{ + struct devlink *devlink; + + if (!rel) + return NULL; + devlink =3D devlinks_xa_get(rel->nested_in.devlink_index); + if (!devlink) + return NULL; + devl_lock(devlink); + if (devl_is_registered(devlink)) + return devlink; + devl_unlock(devlink); + devlink_put(devlink); + return NULL; +} + +/* Returns the nested in devlink object and validates its lock is held. */ +struct devlink *devlink_nested_in_get_locked(struct devlink_rel *rel) +{ + struct devlink *devlink; + unsigned long index; + + if (!rel) + return NULL; + index =3D rel->nested_in.devlink_index; + devlink =3D xa_find(&devlinks, &index, index, DEVLINK_REGISTERED); + if (devlink) + devl_assert_locked(devlink); + return devlink; +} + +void devlink_nested_in_put_unlock(struct devlink_rel *rel) +{ + struct devlink *devlink =3D devlink_nested_in_get_locked(rel); + + if (devlink) { + devl_unlock(devlink); + devlink_put(devlink); + } +} + static void devlink_rel_nested_in_notify_work(struct work_struct *work) { struct devlink_rel *rel =3D container_of(work, struct devlink_rel, diff --git a/net/devlink/devl_internal.h b/net/devlink/devl_internal.h index 14eaad9cfe35..aea43d750d23 100644 --- a/net/devlink/devl_internal.h +++ b/net/devlink/devl_internal.h @@ -120,6 +120,9 @@ typedef void devlink_rel_notify_cb_t(struct devlink *de= vlink, u32 obj_index); typedef void devlink_rel_cleanup_cb_t(struct devlink *devlink, u32 obj_ind= ex, u32 rel_index); =20 +struct devlink *devlink_nested_in_get_lock(struct devlink_rel *rel); +struct devlink *devlink_nested_in_get_locked(struct devlink_rel *rel); +void devlink_nested_in_put_unlock(struct devlink_rel *rel); void devlink_rel_nested_in_clear(u32 rel_index); int devlink_rel_nested_in_add(u32 *rel_index, u32 devlink_index, u32 obj_index, devlink_rel_notify_cb_t *notify_cb, --=20 2.31.1 From nobody Tue Dec 2 00:46:21 2025 Received: from CH5PR02CU005.outbound.protection.outlook.com (mail-northcentralusazon11012018.outbound.protection.outlook.com [40.107.200.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 63FED29E114; Sun, 23 Nov 2025 07:23:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.200.18 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763882632; cv=fail; b=LhyqFSMhDiv2IDrHTPmMvdJOiiBZl1oKKOUSOVlVoXK7Hc0y0JDJe04B/IOyTIsKbm5H9qya62ehz54n0aQYSJ7satmhWj8cGezcR7yt9KpJwjKgdYiD5KvxRDEvFjQipT6lx8ZGKqJcRd49yHYfZQbj+uhG3zs061ya6URy3yM= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763882632; c=relaxed/simple; bh=xhJB/sYh0ubkeeYp1a8DRm5dsj7cwoJdOdCWOS6Tmb0=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=fOjpfozVNkhBFGmMEyZXpJP/iQItSKY/jbtMFDVKxN7+c4d/6bkJljD80YQUI4ykZc639KF71zXCJiFTMk5fviedFwABZVJU1xoHafDDMvvgJa4KSE0zlNHQLlwhB1OoRgBMrmnQr5EcOT//Ng+1MSuVFjJablSiHm+1F68cjnk= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=dWMnoOX6; arc=fail smtp.client-ip=40.107.200.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="dWMnoOX6" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=bANy8COPN7TeS0qtR2Wi5XFsospQZPWBD0fJSqjknk4nUenvuo/VHEOBXman9pfMAlXlTFn1PyL6v2iQDp32lqNDdsnk2lpz3+9z8BNjqW+0kkTXdZ5lCUFstI45z8b/WKUdPSe1j8+jMZD4mp3pdFrQXqiWanpNF0sT5/xvMBuesz+uoUEydKi08VqynMD+Wi79EDgqxp8TJ1x8pIUjP1RXt+sh/Ilmq3ya9h8Yrn75RFOM5AhBrA3hHDssRo6FBK8zeE/lMzBYiBZw9yJ4kJ77hA8/kEa4BRS4i8oJRHchB5Rl99wCIG2o7gX54zVzJ6aS6uumBigqyFfm/1OOZw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=PUAQAuCDnrjxX94659OK3IBx8BMuWDkmqvGWavblWHQ=; b=C2NXKxqWlzl6MJIYKHk8uOKXVRxpX+GJGTPoSOBSdLgRwoXgV3TKBZWaUzjJvsSXPiVzilyKLDxtHgHDgByf30h4OM3gWqWZl9hH8uRUjvxJNTLQmLCsPLZmDTiMOP6STfnnwZvMxeP88nAYnAlyaqECDUz4AkQJ2c7KDJRJaZV5f2+LGmi62wYxyE6nS2hKkJy0ZHQQIK8JCJkTzkuTG2m+D/sPcEJ/Uy2JZB51mYmuz2bfIuvpeE4e0GJcgHRCWb8KbJ4GF1xKY3PM2kmzbKkpvcpilIuyAzNIYw3tORYjUlQYMpegy6kACsT8Zr/JEwtUmAWXJMPuxYsYsfn6bQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=google.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=PUAQAuCDnrjxX94659OK3IBx8BMuWDkmqvGWavblWHQ=; b=dWMnoOX6a6sFmte6kmBqTke83pcOgB2m4wDB+UHX5vC/okZQequ881UDp3QjyLk3fuYqmzRt+gydpqz2mpIgxlsoZla0EkBSGS/2oL3x2zDk2UrAgSeEHSl0tGHW3Uwgtioc1lCKpcuDAvYHalp7Hsbjj0AT2NOXRTr01/MRGwK2PFE+NvM7PhS0uwxXglha+3Bz3WRZSjd1m00Qdws6FAWzCQuubwW2SXtJnQ44SfZRqK8IwWrrpvghp+h08jVE8/N9NpQkRj4PyoXDSFsD0X5CRHf5dRlqoxX6afkGqNnALq8KUnlry9h+3bovV1aKC0GdB69WiNyOYShLIWD2tQ== Received: from SA9PR13CA0047.namprd13.prod.outlook.com (2603:10b6:806:22::22) by SN7PR12MB7978.namprd12.prod.outlook.com (2603:10b6:806:34b::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9343.15; Sun, 23 Nov 2025 07:23:46 +0000 Received: from SN1PEPF000397B3.namprd05.prod.outlook.com (2603:10b6:806:22:cafe::fb) by SA9PR13CA0047.outlook.office365.com (2603:10b6:806:22::22) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9343.10 via Frontend Transport; Sun, 23 Nov 2025 07:23:45 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by SN1PEPF000397B3.mail.protection.outlook.com (10.167.248.57) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9366.7 via Frontend Transport; Sun, 23 Nov 2025 07:23:45 +0000 Received: from rnnvmail202.nvidia.com (10.129.68.7) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Sat, 22 Nov 2025 23:23:36 -0800 Received: from rnnvmail201.nvidia.com (10.129.68.8) by rnnvmail202.nvidia.com (10.129.68.7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Sat, 22 Nov 2025 23:23:36 -0800 Received: from vdi.nvidia.com (10.127.8.10) by mail.nvidia.com (10.129.68.8) with Microsoft SMTP Server id 15.2.2562.20 via Frontend Transport; Sat, 22 Nov 2025 23:23:30 -0800 From: Tariq Toukan To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Donald Hunter , Jiri Pirko , Jonathan Corbet , Saeed Mahameed , "Leon Romanovsky" , Tariq Toukan , Mark Bloch , , , , , Gal Pressman , Moshe Shemesh , Carolina Jubran , Cosmin Ratiu , Jiri Pirko Subject: [PATCH net-next V2 04/14] devlink: Refactor devlink_rate_nodes_check Date: Sun, 23 Nov 2025 09:22:50 +0200 Message-ID: <1763882580-1295213-5-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1763882580-1295213-1-git-send-email-tariqt@nvidia.com> References: <1763882580-1295213-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000397B3:EE_|SN7PR12MB7978:EE_ X-MS-Office365-Filtering-Correlation-Id: 4eb0ac2c-bb99-4bb4-6a9f-08de2a613d25 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|7416014|376014|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?T3/VTdheOeqFar1eOBHtIsOf8ZHPff9KdTPnVczIez2yzXWQ9X4jXPQZ264f?= =?us-ascii?Q?0we6Iw2BB9SojsmQAclOWAopc+jeNjbidiy5tEO6q12pbnU505jetZ0efxl7?= =?us-ascii?Q?R8nqUzNWvPoerNw+ypFCcxu9+RMM8ZaXBq6B2CWQbPwbPFZ6jF/VoJfqJpzy?= =?us-ascii?Q?tOnaggRPIjRqEgMGT4TUQ5oMe2VvqD+luAKKTW7ITdqMei+uYJENCaRse0AK?= =?us-ascii?Q?dHQu2+9cfypCmStY/rZG9z4RfQzZYFcKDwGLnxCb6xMahx+fpui15Ikgv+9Y?= =?us-ascii?Q?Uos939WXpyD4b0LJbGsSbij3G5tdrb4rg2LKGsdT4CxI8y6eMdKM23vRiAp1?= =?us-ascii?Q?dsoCBfuV4UNfuBGZKoo7XBmVZLkDZt0PKw/qnqWufndTk+2cPPcvHWt5UU/e?= =?us-ascii?Q?moCroINr23DGJ+lH8tCmeT+5osHX8YRPmrZ29R1i9KVoqL58tYrWMcspAg4G?= =?us-ascii?Q?nnwARuk79iiSVBqc0lSKtnumTbk0sevm6HuPIfSxQSrS3n2UFSf4YnXsCuRK?= =?us-ascii?Q?/q27Avf7yKAhEMNEGMlG7Uc24yUmlbLsVs9F/dtHsvCmLnBVQ9AbKaJpufNI?= =?us-ascii?Q?VTJ3ngforD31af1cOlT2BQD0Rknnkl/n640EybXx5axuHn8lo0Py2JsabVRM?= =?us-ascii?Q?fkuPJPoacDKM5BFnUvzJmY4UiNVdOFN1teW179TL9ICrHst9UV8SPKZ2C4J7?= =?us-ascii?Q?E2GZ3v25rEkEx+XFMvNSfGOLG8Cf6cBkUcu3jwqtQjOG7yuaUoK184fIKPBc?= =?us-ascii?Q?WrjkQBv09qXwu3FKZy8PPucVdXHwTn3SD72U4V5IEYpp9A2lM7l+mhfos3pb?= =?us-ascii?Q?jZtQdy+7aCoGu4yn41II+fsLGoJ1ukZDUqExRW9P+vZkgH3i3Zzo8Jw7sPnZ?= =?us-ascii?Q?8GbWRBx3kuW/YtwXKOx97C1Bk12NYNewWhWpicWpGBfaxP+jHGr0yIiWTCkF?= =?us-ascii?Q?NOyfcyIYEwpbpLlgrv17p2/DRSk1gHbuArqQ05f48Fb8aZ8Wpfud2UM4HIvb?= =?us-ascii?Q?Sq89FrIzVl+R6BxZq8x7iy1Z6qsOacjfULb7p2xK6D8UumFAETXAaCakAYds?= =?us-ascii?Q?YY/71yem+xnCFpbBuLYFDzBbnsL3Se/3s3O0wzFVl1wq42BUlfYzLG4LJIzN?= =?us-ascii?Q?2lU2inGfy1bftuJey3eNrzFRZy27r6CHR5j3mly9NQj4dS7kKUUBqkElVWd9?= =?us-ascii?Q?Xdxy471bwcP+tYMs8b4lo3OAudEPR49pu9TTMaIGGZKPyXtknDkV3gnX8/80?= =?us-ascii?Q?ngZkTcXUPHp0q8qKaA080UraoEvc/NZ5yaE+hiaRZXrs3YhaXEuzwjF0aoQ4?= =?us-ascii?Q?YwR933sQ7hDWQF2kcnaMYh+N+SfYhu1Q1jLBgiQO01tIdcxGuDtBddMP1tiA?= =?us-ascii?Q?kB5aR1ldSmwQP3dvRffybb4T39AWGmdEUNU49nKTMJduzZFBraubv9PIXTla?= =?us-ascii?Q?ASJ0Nae3gw6/RM9uMh/9wPjZTDmPqvORP0BUZMOvmfuGWtmWKcPwVgO4AJI1?= =?us-ascii?Q?FRf9vyQn9JCccT3zNydJ+2yx1TVAkHrHJDy1jIaexqacRkpjApilP7sXnN9l?= =?us-ascii?Q?eScrEMSYgSrHXhlgS8k=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(1800799024)(7416014)(376014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Nov 2025 07:23:45.7810 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4eb0ac2c-bb99-4bb4-6a9f-08de2a613d25 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000397B3.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB7978 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Cosmin Ratiu devlink_rate_nodes_check() was used to verify there are no devlink rate nodes created when switching the esw mode. Rate management code is about to become more complex, so refactor this function: - remove unused param 'mode'. - add a new 'rate_filter' param. - rename to devlink_rates_check(). - expose devlink_rate_is_node() to be used as a rate filter. This makes it more usable from multiple places, so use it from those places as well. Signed-off-by: Cosmin Ratiu Reviewed-by: Carolina Jubran Reviewed-by: Jiri Pirko Signed-off-by: Tariq Toukan --- net/devlink/core.c | 2 +- net/devlink/dev.c | 7 ++++--- net/devlink/devl_internal.h | 6 ++++-- net/devlink/rate.c | 13 +++++++------ 4 files changed, 16 insertions(+), 12 deletions(-) diff --git a/net/devlink/core.c b/net/devlink/core.c index f228190df346..f72d8cc0d6dd 100644 --- a/net/devlink/core.c +++ b/net/devlink/core.c @@ -517,7 +517,7 @@ void devlink_free(struct devlink *devlink) WARN_ON(!list_empty(&devlink->resource_list)); WARN_ON(!list_empty(&devlink->dpipe_table_list)); WARN_ON(!list_empty(&devlink->sb_list)); - WARN_ON(!list_empty(&devlink->rate_list)); + WARN_ON(devlink_rates_check(devlink, NULL, NULL)); WARN_ON(!list_empty(&devlink->linecard_list)); WARN_ON(!xa_empty(&devlink->ports)); =20 diff --git a/net/devlink/dev.c b/net/devlink/dev.c index 02602704bdea..e3a36de4f4ae 100644 --- a/net/devlink/dev.c +++ b/net/devlink/dev.c @@ -434,7 +434,7 @@ static void devlink_reload_reinit_sanity_check(struct d= evlink *devlink) WARN_ON(!list_empty(&devlink->trap_list)); WARN_ON(!list_empty(&devlink->dpipe_table_list)); WARN_ON(!list_empty(&devlink->sb_list)); - WARN_ON(!list_empty(&devlink->rate_list)); + WARN_ON(devlink_rates_check(devlink, NULL, NULL)); WARN_ON(!list_empty(&devlink->linecard_list)); WARN_ON(!xa_empty(&devlink->ports)); } @@ -713,10 +713,11 @@ int devlink_nl_eswitch_set_doit(struct sk_buff *skb, = struct genl_info *info) if (info->attrs[DEVLINK_ATTR_ESWITCH_MODE]) { if (!ops->eswitch_mode_set) return -EOPNOTSUPP; - mode =3D nla_get_u16(info->attrs[DEVLINK_ATTR_ESWITCH_MODE]); - err =3D devlink_rate_nodes_check(devlink, mode, info->extack); + err =3D devlink_rates_check(devlink, devlink_rate_is_node, + info->extack); if (err) return err; + mode =3D nla_get_u16(info->attrs[DEVLINK_ATTR_ESWITCH_MODE]); err =3D ops->eswitch_mode_set(devlink, mode, info->extack); if (err) return err; diff --git a/net/devlink/devl_internal.h b/net/devlink/devl_internal.h index aea43d750d23..8374c9cab6ce 100644 --- a/net/devlink/devl_internal.h +++ b/net/devlink/devl_internal.h @@ -300,8 +300,10 @@ int devlink_resources_validate(struct devlink *devlink, struct genl_info *info); =20 /* Rates */ -int devlink_rate_nodes_check(struct devlink *devlink, u16 mode, - struct netlink_ext_ack *extack); +bool devlink_rate_is_node(const struct devlink_rate *devlink_rate); +int devlink_rates_check(struct devlink *devlink, + bool (*rate_filter)(const struct devlink_rate *), + struct netlink_ext_ack *extack); =20 /* Linecards */ unsigned int devlink_linecard_index(struct devlink_linecard *linecard); diff --git a/net/devlink/rate.c b/net/devlink/rate.c index d157a8419bca..0d68b5c477dc 100644 --- a/net/devlink/rate.c +++ b/net/devlink/rate.c @@ -12,8 +12,7 @@ devlink_rate_is_leaf(struct devlink_rate *devlink_rate) return devlink_rate->type =3D=3D DEVLINK_RATE_TYPE_LEAF; } =20 -static inline bool -devlink_rate_is_node(struct devlink_rate *devlink_rate) +bool devlink_rate_is_node(const struct devlink_rate *devlink_rate) { return devlink_rate->type =3D=3D DEVLINK_RATE_TYPE_NODE; } @@ -688,14 +687,16 @@ int devlink_nl_rate_del_doit(struct sk_buff *skb, str= uct genl_info *info) return err; } =20 -int devlink_rate_nodes_check(struct devlink *devlink, u16 mode, - struct netlink_ext_ack *extack) +int devlink_rates_check(struct devlink *devlink, + bool (*rate_filter)(const struct devlink_rate *), + struct netlink_ext_ack *extack) { struct devlink_rate *devlink_rate; =20 list_for_each_entry(devlink_rate, &devlink->rate_list, list) - if (devlink_rate_is_node(devlink_rate)) { - NL_SET_ERR_MSG(extack, "Rate node(s) exists."); + if (!rate_filter || rate_filter(devlink_rate)) { + if (extack) + NL_SET_ERR_MSG(extack, "Rate node(s) exists."); return -EBUSY; } return 0; --=20 2.31.1 From nobody Tue Dec 2 00:46:21 2025 Received: from BL0PR03CU003.outbound.protection.outlook.com (mail-eastusazon11012025.outbound.protection.outlook.com [52.101.53.25]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 96D47296BAA; Sun, 23 Nov 2025 07:24:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.53.25 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763882644; cv=fail; b=sfhJPlxilvp/ezoC+lm1kdDcra2hyWpmY9sBYHqU+EdK+Dmcy9+xeUk0gZ37ba/BeCdh9aXn/p8KVeWKJda+8W9dBmnCRT+FbpV8SjzCnjdO5RvI8qIpl5DQMuvrxLpSKixYyamw6qICjEh/MmBpQ5UkHSwNNxBSQdu0knkspmQ= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763882644; c=relaxed/simple; bh=i4wia0sHLKDHhSKGvUEYQSrIb1YQHBSPHrimw1lpyaI=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=T3gemI8N5L41izQlbRgz0FSxwfonAfslvQtMi0wLAKOAxZHtQcDJpkocvTjSuNMu98qk+vneyLvZHLkT2HK7YOkyNdyTvRxlGpo9RGcTgzFSiuxPHvv2wcsl+6mo0xOpXEnOsjbOA8nB/SeAh7dT/r9M4gJMwP7pmcgD7FCI7QM= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=tLff/M2I; arc=fail smtp.client-ip=52.101.53.25 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="tLff/M2I" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=NXu959jGKULQEREjcTHQ3RGbRtfxHtuUcCifNbaY9QzstccEo5vrlmYydRWcsmDc5bB6sdeJR8RFZFMR1wsaU4UKgekGB6LCYEnxLv3h9oruVUqQvItcnMjaQWLlU5fzk3LpP7zLvhXPGeT+5rd2U+LbBGEHkQWlHBKGt7v67UC1z+RNxsLKt4iY1Rb8DeNu1JrdsfJI1UW8S9CJUSo2XagY6+ML9I66BiW2kV4Cnw8vDVlJ66PPIBZQH5P9cvaRpbsLLnU8gzZcDPkTWcV+Ni32+mCbEb5ug/DWT8cYEcWJKfwULgfrYxreAWEO1oC9Eom/fp6nd+RYbiktI0SBCA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=jtWrTV9+wo2tN7h17N/HD6NvbGEo5t0j7CYUEjUbLdY=; b=g6O6zOkYU5aogNIn1fGlantOaEbnEtd0DsZ9Lmik9xjEDp0B3SxzDs4AwGeLrsA7kZ7LSVir37I+gyfVVY5J2sIeFaJnxDxDVn/JOmUmke6ud7NMgF6/oyPkolWwuSKy/+o6pZRXSI5f6oB2YumjStZBeS2gOXdWtQvEO8n87bx735vKYT99Lgl+jUx3+y3Nrbn49uc+C/0eq1etKccO0tFLFQctbUOY6vkwZXLuLczN2YIICgsmtbPP7gOeRNcblTUaEAyXK31AcLbLBQj01r0126RD1CX9tQ7AJ+o00j2ZWNrPuFgtt8rg0vqXvwF8mdjz/tHcAkumDlenHIHs0w== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=google.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=jtWrTV9+wo2tN7h17N/HD6NvbGEo5t0j7CYUEjUbLdY=; b=tLff/M2IBkaC0o4xiiVzSTETWdSFF7ZBktixVbfIMHVeURFfZ7xSyCXhvGHu+rJmQjfHnT715DW2+rYA/0GspSMbMIOLVqz5EbKKKGgbuMSlmTZUrl5Uy90W/kv7fu+ao+ITxAoYGsMs4lSQYg3vf4YiadVuLLI0NFk/tmwdiwhWQeWaoDyJq3oR0N4j68p5qY7t5IrPWRxz5Dsrmu42yaP9dpdxk6nDEFWTi4Kyyndyt1fRsAbERobeVARRZq/NdxoEMzFY/4G08GImijPkRifPDJrMKQPA3EZd/jb6Qx73huoOfHz9EczGn0Eyi5bhp8iWfvhAGGTb9FuLeSjsNQ== Received: from SA9PR13CA0049.namprd13.prod.outlook.com (2603:10b6:806:22::24) by PH7PR12MB6417.namprd12.prod.outlook.com (2603:10b6:510:1ff::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9343.15; Sun, 23 Nov 2025 07:23:51 +0000 Received: from SN1PEPF000397B3.namprd05.prod.outlook.com (2603:10b6:806:22:cafe::d3) by SA9PR13CA0049.outlook.office365.com (2603:10b6:806:22::24) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9366.8 via Frontend Transport; Sun, 23 Nov 2025 07:23:48 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by SN1PEPF000397B3.mail.protection.outlook.com (10.167.248.57) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9366.7 via Frontend Transport; Sun, 23 Nov 2025 07:23:51 +0000 Received: from rnnvmail202.nvidia.com (10.129.68.7) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Sat, 22 Nov 2025 23:23:42 -0800 Received: from rnnvmail201.nvidia.com (10.129.68.8) by rnnvmail202.nvidia.com (10.129.68.7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Sat, 22 Nov 2025 23:23:42 -0800 Received: from vdi.nvidia.com (10.127.8.10) by mail.nvidia.com (10.129.68.8) with Microsoft SMTP Server id 15.2.2562.20 via Frontend Transport; Sat, 22 Nov 2025 23:23:36 -0800 From: Tariq Toukan To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Donald Hunter , Jiri Pirko , Jonathan Corbet , Saeed Mahameed , "Leon Romanovsky" , Tariq Toukan , Mark Bloch , , , , , Gal Pressman , Moshe Shemesh , Carolina Jubran , Cosmin Ratiu , Jiri Pirko Subject: [PATCH net-next V2 05/14] devlink: Decouple rate storage from associated devlink object Date: Sun, 23 Nov 2025 09:22:51 +0200 Message-ID: <1763882580-1295213-6-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1763882580-1295213-1-git-send-email-tariqt@nvidia.com> References: <1763882580-1295213-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000397B3:EE_|PH7PR12MB6417:EE_ X-MS-Office365-Filtering-Correlation-Id: 8879d69e-1a82-4339-d5a3-08de2a61406b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|7416014|376014|82310400026|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?OmQ0HSLEMtVXxl0Q2sU9gsPUOgOcYJpHS74TsRdzvo51ShAe2goFHwe3AJ4j?= =?us-ascii?Q?rC0VgQtYshBwdrM8SC7Er2GPuuaQPqz3Lu+EJtO/J9huqnnNB11tYuHY1NB6?= =?us-ascii?Q?gIQuFx0NqKVfQPEdCGgobxKonpY/yViQfJXwtfrn/KhV7Eywmz7zl0uupocq?= =?us-ascii?Q?c4dISB4V6t30BHFtMnNEIkzOWnwbAxtZ5vQ7hnNE+HllqGkMoI03wT8sUXtC?= =?us-ascii?Q?gdwYAlN4M/fBvP+eO3enkIaz9UK8GHjoWtdr9CTRnZjFOnffyvbBLejeHrFk?= =?us-ascii?Q?aAe6uvko6wo0UEAjGld++7jKeKFA+j1dDtVhIZDpTYm820n0PqQUTQkSWE3X?= =?us-ascii?Q?PkFNt2iT6dRtlWl38oDAY52U4P6L7qTpMIrx9CpaJZG/6IYiiZROTehZujrN?= =?us-ascii?Q?es+heCoDc+1be5Mxm7sAKyehOa/G+dI5onLp1LYVmDTPx35UiE8NIqXlhJJI?= =?us-ascii?Q?dyosli9DrOT2MCkuX1/nGyQtRFeUWKlh++c7Ga9IPC8yUjGjBnk83CSVgFk/?= =?us-ascii?Q?akCA9xTC771P//x3FttMZmU7XBX5MVSZ2Q3lxiaGpWQONfh2MaKBUGVtZw8l?= =?us-ascii?Q?FrZVaL9/TMRdvG8nt+n7gg7t8MRs5Ow86styISOlqUVU9qr5/1VMr05vLYJD?= =?us-ascii?Q?6ZJ0kuSUsPr/6m61qlvzct+aMkARVY6Tx2pHveYEAFYAOuWhr0864X//J/4h?= =?us-ascii?Q?ZHNQW0P0xCiYQzBc+/XT4ta9QnvVfWpDUf45tmAKFo4X9eNV13t1xpyAONSG?= =?us-ascii?Q?RqTyWL5Q5rMgQ0ldBjOwuBR2KzHMXIYsmdwhzwWnuogQVil5LQSpEDwREyIc?= =?us-ascii?Q?rdS0WWHVIifV+WQEwtqzu6W/EmeOddKjNJPb02nNbx/dIb3dnAL4RgutKbPF?= =?us-ascii?Q?bNR1R+59QJU3IPQ6B5tkm9VUzz/rB0wR1tOJEtsEpmoNZyaRlrSWGqK9zYQU?= =?us-ascii?Q?OE/crH6tlO5p52fCZ+KCql6LZG3De6P1FhHR1G57s41pT4qK5DsUC13PHMXU?= =?us-ascii?Q?YC5ooKarouNrkx2aKava9ja/axqiIubKttfaE39MjcrtP3uaJWX4+X/kQV3E?= =?us-ascii?Q?T0ZBKTGnPhhjXBOUQXD1sbWOCRFsHDS5Dd+TAhXr9oRwhZiROZY3jRN9lLp9?= =?us-ascii?Q?F36LBXQeydMdUQWqgDDNIWXdrYDx/a55oE/ahey78ikw0ud84uoa5Wptw1eD?= =?us-ascii?Q?iVVxN5kTUXWHAoGJkFCnfdRIJM2ybMrE6YCVtpJkYkgQQ8cSstXd4EsSlaZp?= =?us-ascii?Q?vgcBa7hV3a5VykkRtOIQlnaTeACwTDN617YHCYaBoPl+MJPIPslhz+Cz74Jx?= =?us-ascii?Q?EYcWJFadowV7YnHYdtMeP34zErQrRC2VN8jttiGrci2DDr/OyaTDKTqrGpG6?= =?us-ascii?Q?X3S7HdVbJc5fmvtNts0M06x2ysbNe538utg4lr6QCm+T3upjeWM8ouIKLx5N?= =?us-ascii?Q?0wEhc0F/PGU9cYmI9M8Q4I0MhKkUMeIq0nqtWeJr5Stlea1IxglX8QNnpHMf?= =?us-ascii?Q?sLOSZ0HefnDovMacATw6oPAX8cAmw9T3l/dg37Zclmo5bZs0pX3duuu0FJME?= =?us-ascii?Q?3LguYRxum3CQ7vDuflE=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(7416014)(376014)(82310400026)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Nov 2025 07:23:51.2590 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8879d69e-1a82-4339-d5a3-08de2a61406b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000397B3.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6417 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Cosmin Ratiu Devlink rate leafs and nodes were stored in their respective devlink objects pointed to by devlink_rate->devlink. This patch removes that association by introducing the concept of 'rate node devlink', which is where all rates that could link to each other are stored. For now this is the same as devlink_rate->devlink. After this patch, the devlink rates stored in this devlink instance could potentially be from multiple other devlink instances. So all rate node manipulation code was updated to: - correctly compare the actual devlink object during iteration. - maybe acquire additional locks (noop for now). Signed-off-by: Cosmin Ratiu Reviewed-by: Carolina Jubran Signed-off-by: Tariq Toukan Reviewed-by: Jiri Pirko --- include/net/devlink.h | 2 + net/devlink/rate.c | 192 +++++++++++++++++++++++++++++++----------- 2 files changed, 144 insertions(+), 50 deletions(-) diff --git a/include/net/devlink.h b/include/net/devlink.h index cb839e0435a1..df481af91473 100644 --- a/include/net/devlink.h +++ b/include/net/devlink.h @@ -1814,6 +1814,8 @@ void devlink_port_attrs_pci_sf_set(struct devlink_por= t *devlink_port, bool external); int devl_port_fn_devlink_set(struct devlink_port *devlink_port, struct devlink *fn_devlink); +struct devlink *devl_rate_lock(struct devlink *devlink); +void devl_rate_unlock(struct devlink *devlink); struct devlink_rate * devl_rate_node_create(struct devlink *devlink, void *priv, char *node_name, struct devlink_rate *parent); diff --git a/net/devlink/rate.c b/net/devlink/rate.c index 0d68b5c477dc..ddbd0beec4b9 100644 --- a/net/devlink/rate.c +++ b/net/devlink/rate.c @@ -30,13 +30,31 @@ devlink_rate_leaf_get_from_info(struct devlink *devlink= , struct genl_info *info) return devlink_rate ?: ERR_PTR(-ENODEV); } =20 +struct devlink *devl_rate_lock(struct devlink *devlink) +{ + return devlink; +} + +static struct devlink * +devl_get_rate_node_instance_locked(struct devlink *devlink) +{ + return devlink; +} + +void devl_rate_unlock(struct devlink *devlink) +{ +} + static struct devlink_rate * devlink_rate_node_get_by_name(struct devlink *devlink, const char *node_na= me) { struct devlink_rate *devlink_rate; + struct devlink *rate_devlink; =20 - list_for_each_entry(devlink_rate, &devlink->rate_list, list) { - if (devlink_rate_is_node(devlink_rate) && + rate_devlink =3D devl_get_rate_node_instance_locked(devlink); + list_for_each_entry(devlink_rate, &rate_devlink->rate_list, list) { + if (devlink_rate->devlink =3D=3D devlink && + devlink_rate_is_node(devlink_rate) && !strcmp(node_name, devlink_rate->name)) return devlink_rate; } @@ -190,17 +208,25 @@ static void devlink_rate_notify(struct devlink_rate *= devlink_rate, void devlink_rates_notify_register(struct devlink *devlink) { struct devlink_rate *rate_node; + struct devlink *rate_devlink; =20 - list_for_each_entry(rate_node, &devlink->rate_list, list) - devlink_rate_notify(rate_node, DEVLINK_CMD_RATE_NEW); + rate_devlink =3D devl_rate_lock(devlink); + list_for_each_entry(rate_node, &rate_devlink->rate_list, list) + if (rate_node->devlink =3D=3D devlink) + devlink_rate_notify(rate_node, DEVLINK_CMD_RATE_NEW); + devl_rate_unlock(devlink); } =20 void devlink_rates_notify_unregister(struct devlink *devlink) { struct devlink_rate *rate_node; + struct devlink *rate_devlink; =20 - list_for_each_entry_reverse(rate_node, &devlink->rate_list, list) - devlink_rate_notify(rate_node, DEVLINK_CMD_RATE_DEL); + rate_devlink =3D devl_rate_lock(devlink); + list_for_each_entry_reverse(rate_node, &rate_devlink->rate_list, list) + if (rate_node->devlink =3D=3D devlink) + devlink_rate_notify(rate_node, DEVLINK_CMD_RATE_DEL); + devl_rate_unlock(devlink); } =20 static int @@ -209,10 +235,12 @@ devlink_nl_rate_get_dump_one(struct sk_buff *msg, str= uct devlink *devlink, { struct devlink_nl_dump_state *state =3D devlink_dump_state(cb); struct devlink_rate *devlink_rate; + struct devlink *rate_devlink; int idx =3D 0; int err =3D 0; =20 - list_for_each_entry(devlink_rate, &devlink->rate_list, list) { + rate_devlink =3D devl_rate_lock(devlink); + list_for_each_entry(devlink_rate, &rate_devlink->rate_list, list) { enum devlink_command cmd =3D DEVLINK_CMD_RATE_NEW; u32 id =3D NETLINK_CB(cb->skb).portid; =20 @@ -220,6 +248,9 @@ devlink_nl_rate_get_dump_one(struct sk_buff *msg, struc= t devlink *devlink, idx++; continue; } + if (devlink_rate->devlink !=3D devlink) + continue; + err =3D devlink_nl_rate_fill(msg, devlink_rate, cmd, id, cb->nlh->nlmsg_seq, flags, NULL); if (err) { @@ -228,6 +259,7 @@ devlink_nl_rate_get_dump_one(struct sk_buff *msg, struc= t devlink *devlink, } idx++; } + devl_rate_unlock(devlink); =20 return err; } @@ -244,23 +276,33 @@ int devlink_nl_rate_get_doit(struct sk_buff *skb, str= uct genl_info *info) struct sk_buff *msg; int err; =20 + devl_rate_lock(devlink); devlink_rate =3D devlink_rate_get_from_info(devlink, info); - if (IS_ERR(devlink_rate)) - return PTR_ERR(devlink_rate); + if (IS_ERR(devlink_rate)) { + err =3D PTR_ERR(devlink_rate); + goto unlock; + } =20 msg =3D nlmsg_new(NLMSG_DEFAULT_SIZE, GFP_KERNEL); - if (!msg) - return -ENOMEM; + if (!msg) { + err =3D -ENOMEM; + goto unlock; + } =20 err =3D devlink_nl_rate_fill(msg, devlink_rate, DEVLINK_CMD_RATE_NEW, info->snd_portid, info->snd_seq, 0, info->extack); - if (err) { - nlmsg_free(msg); - return err; - } + if (err) + goto err_fill; =20 + devl_rate_unlock(devlink); return genlmsg_reply(msg, info); + +err_fill: + nlmsg_free(msg); +unlock: + devl_rate_unlock(devlink); + return err; } =20 static bool @@ -590,24 +632,32 @@ int devlink_nl_rate_set_doit(struct sk_buff *skb, str= uct genl_info *info) const struct devlink_ops *ops; int err; =20 + devl_rate_lock(devlink); devlink_rate =3D devlink_rate_get_from_info(devlink, info); - if (IS_ERR(devlink_rate)) - return PTR_ERR(devlink_rate); + if (IS_ERR(devlink_rate)) { + err =3D PTR_ERR(devlink_rate); + goto unlock; + } =20 ops =3D devlink->ops; - if (!ops || !devlink_rate_set_ops_supported(ops, info, devlink_rate->type= )) - return -EOPNOTSUPP; + if (!ops || + !devlink_rate_set_ops_supported(ops, info, devlink_rate->type)) { + err =3D -EOPNOTSUPP; + goto unlock; + } =20 err =3D devlink_nl_rate_set(devlink_rate, ops, info); =20 if (!err) devlink_rate_notify(devlink_rate, DEVLINK_CMD_RATE_NEW); +unlock: + devl_rate_unlock(devlink); return err; } =20 int devlink_nl_rate_new_doit(struct sk_buff *skb, struct genl_info *info) { - struct devlink *devlink =3D info->user_ptr[0]; + struct devlink *rate_devlink, *devlink =3D info->user_ptr[0]; struct devlink_rate *rate_node; const struct devlink_ops *ops; int err; @@ -621,15 +671,21 @@ int devlink_nl_rate_new_doit(struct sk_buff *skb, str= uct genl_info *info) if (!devlink_rate_set_ops_supported(ops, info, DEVLINK_RATE_TYPE_NODE)) return -EOPNOTSUPP; =20 + rate_devlink =3D devl_rate_lock(devlink); rate_node =3D devlink_rate_node_get_from_attrs(devlink, info->attrs); - if (!IS_ERR(rate_node)) - return -EEXIST; - else if (rate_node =3D=3D ERR_PTR(-EINVAL)) - return -EINVAL; + if (!IS_ERR(rate_node)) { + err =3D -EEXIST; + goto unlock; + } else if (rate_node =3D=3D ERR_PTR(-EINVAL)) { + err =3D -EINVAL; + goto unlock; + } =20 rate_node =3D kzalloc(sizeof(*rate_node), GFP_KERNEL); - if (!rate_node) - return -ENOMEM; + if (!rate_node) { + err =3D -ENOMEM; + goto unlock; + } =20 rate_node->devlink =3D devlink; rate_node->type =3D DEVLINK_RATE_TYPE_NODE; @@ -648,8 +704,9 @@ int devlink_nl_rate_new_doit(struct sk_buff *skb, struc= t genl_info *info) goto err_rate_set; =20 refcount_set(&rate_node->refcnt, 1); - list_add(&rate_node->list, &devlink->rate_list); + list_add(&rate_node->list, &rate_devlink->rate_list); devlink_rate_notify(rate_node, DEVLINK_CMD_RATE_NEW); + devl_rate_unlock(devlink); return 0; =20 err_rate_set: @@ -658,6 +715,8 @@ int devlink_nl_rate_new_doit(struct sk_buff *skb, struc= t genl_info *info) kfree(rate_node->name); err_strdup: kfree(rate_node); +unlock: + devl_rate_unlock(devlink); return err; } =20 @@ -667,13 +726,17 @@ int devlink_nl_rate_del_doit(struct sk_buff *skb, str= uct genl_info *info) struct devlink_rate *rate_node; int err; =20 + devl_rate_lock(devlink); rate_node =3D devlink_rate_node_get_from_info(devlink, info); - if (IS_ERR(rate_node)) - return PTR_ERR(rate_node); + if (IS_ERR(rate_node)) { + err =3D PTR_ERR(rate_node); + goto unlock; + } =20 if (refcount_read(&rate_node->refcnt) > 1) { NL_SET_ERR_MSG(info->extack, "Node has children. Cannot delete node."); - return -EBUSY; + err =3D -EBUSY; + goto unlock; } =20 devlink_rate_notify(rate_node, DEVLINK_CMD_RATE_DEL); @@ -684,6 +747,8 @@ int devlink_nl_rate_del_doit(struct sk_buff *skb, struc= t genl_info *info) list_del(&rate_node->list); kfree(rate_node->name); kfree(rate_node); +unlock: + devl_rate_unlock(devlink); return err; } =20 @@ -692,14 +757,20 @@ int devlink_rates_check(struct devlink *devlink, struct netlink_ext_ack *extack) { struct devlink_rate *devlink_rate; + struct devlink *rate_devlink; + int err =3D 0; =20 - list_for_each_entry(devlink_rate, &devlink->rate_list, list) - if (!rate_filter || rate_filter(devlink_rate)) { + rate_devlink =3D devl_rate_lock(devlink); + list_for_each_entry(devlink_rate, &rate_devlink->rate_list, list) + if (devlink_rate->devlink =3D=3D devlink && + (!rate_filter || rate_filter(devlink_rate))) { if (extack) NL_SET_ERR_MSG(extack, "Rate node(s) exists."); - return -EBUSY; + err =3D -EBUSY; + break; } - return 0; + devl_rate_unlock(devlink); + return err; } =20 /** @@ -716,14 +787,20 @@ devl_rate_node_create(struct devlink *devlink, void *= priv, char *node_name, struct devlink_rate *parent) { struct devlink_rate *rate_node; + struct devlink *rate_devlink; =20 + rate_devlink =3D devl_rate_lock(devlink); rate_node =3D devlink_rate_node_get_by_name(devlink, node_name); - if (!IS_ERR(rate_node)) - return ERR_PTR(-EEXIST); + if (!IS_ERR(rate_node)) { + rate_node =3D ERR_PTR(-EEXIST); + goto unlock; + } =20 rate_node =3D kzalloc(sizeof(*rate_node), GFP_KERNEL); - if (!rate_node) - return ERR_PTR(-ENOMEM); + if (!rate_node) { + rate_node =3D ERR_PTR(-ENOMEM); + goto unlock; + } =20 if (parent) { rate_node->parent =3D parent; @@ -737,12 +814,15 @@ devl_rate_node_create(struct devlink *devlink, void *= priv, char *node_name, rate_node->name =3D kstrdup(node_name, GFP_KERNEL); if (!rate_node->name) { kfree(rate_node); - return ERR_PTR(-ENOMEM); + rate_node =3D ERR_PTR(-ENOMEM); + goto unlock; } =20 refcount_set(&rate_node->refcnt, 1); - list_add(&rate_node->list, &devlink->rate_list); + list_add(&rate_node->list, &rate_devlink->rate_list); devlink_rate_notify(rate_node, DEVLINK_CMD_RATE_NEW); +unlock: + devl_rate_unlock(devlink); return rate_node; } EXPORT_SYMBOL_GPL(devl_rate_node_create); @@ -758,10 +838,10 @@ EXPORT_SYMBOL_GPL(devl_rate_node_create); int devl_rate_leaf_create(struct devlink_port *devlink_port, void *priv, struct devlink_rate *parent) { - struct devlink *devlink =3D devlink_port->devlink; + struct devlink *rate_devlink, *devlink =3D devlink_port->devlink; struct devlink_rate *devlink_rate; =20 - devl_assert_locked(devlink_port->devlink); + devl_assert_locked(devlink); =20 if (WARN_ON(devlink_port->devlink_rate)) return -EBUSY; @@ -770,6 +850,7 @@ int devl_rate_leaf_create(struct devlink_port *devlink_= port, void *priv, if (!devlink_rate) return -ENOMEM; =20 + rate_devlink =3D devl_rate_lock(devlink); if (parent) { devlink_rate->parent =3D parent; refcount_inc(&devlink_rate->parent->refcnt); @@ -779,9 +860,10 @@ int devl_rate_leaf_create(struct devlink_port *devlink= _port, void *priv, devlink_rate->devlink =3D devlink; devlink_rate->devlink_port =3D devlink_port; devlink_rate->priv =3D priv; - list_add_tail(&devlink_rate->list, &devlink->rate_list); + list_add_tail(&devlink_rate->list, &rate_devlink->rate_list); devlink_port->devlink_rate =3D devlink_rate; devlink_rate_notify(devlink_rate, DEVLINK_CMD_RATE_NEW); + devl_rate_unlock(devlink); =20 return 0; } @@ -797,16 +879,19 @@ EXPORT_SYMBOL_GPL(devl_rate_leaf_create); void devl_rate_leaf_destroy(struct devlink_port *devlink_port) { struct devlink_rate *devlink_rate =3D devlink_port->devlink_rate; + struct devlink *devlink =3D devlink_port->devlink; =20 - devl_assert_locked(devlink_port->devlink); + devl_assert_locked(devlink); if (!devlink_rate) return; =20 + devl_rate_lock(devlink); devlink_rate_notify(devlink_rate, DEVLINK_CMD_RATE_DEL); if (devlink_rate->parent) refcount_dec(&devlink_rate->parent->refcnt); list_del(&devlink_rate->list); devlink_port->devlink_rate =3D NULL; + devl_rate_unlock(devlink); kfree(devlink_rate); } EXPORT_SYMBOL_GPL(devl_rate_leaf_destroy); @@ -815,18 +900,22 @@ EXPORT_SYMBOL_GPL(devl_rate_leaf_destroy); * devl_rate_nodes_destroy - destroy all devlink rate nodes on device * @devlink: devlink instance * - * Unset parent for all rate objects and destroy all rate nodes - * on specified device. + * Unset parent for all rate objects involving this device and destroy all= rate + * nodes on it. */ void devl_rate_nodes_destroy(struct devlink *devlink) { const struct devlink_ops *ops =3D devlink->ops; struct devlink_rate *devlink_rate, *tmp; + struct devlink *rate_devlink; =20 devl_assert_locked(devlink); + rate_devlink =3D devl_rate_lock(devlink); =20 - list_for_each_entry(devlink_rate, &devlink->rate_list, list) { - if (!devlink_rate->parent) + list_for_each_entry(devlink_rate, &rate_devlink->rate_list, list) { + if (!devlink_rate->parent || + (devlink_rate->devlink !=3D devlink && + devlink_rate->parent->devlink !=3D devlink)) continue; =20 if (devlink_rate_is_leaf(devlink_rate)) @@ -839,13 +928,16 @@ void devl_rate_nodes_destroy(struct devlink *devlink) refcount_dec(&devlink_rate->parent->refcnt); devlink_rate->parent =3D NULL; } - list_for_each_entry_safe(devlink_rate, tmp, &devlink->rate_list, list) { - if (devlink_rate_is_node(devlink_rate)) { + list_for_each_entry_safe(devlink_rate, tmp, &rate_devlink->rate_list, + list) { + if (devlink_rate->devlink =3D=3D devlink && + devlink_rate_is_node(devlink_rate)) { ops->rate_node_del(devlink_rate, devlink_rate->priv, NULL); list_del(&devlink_rate->list); kfree(devlink_rate->name); kfree(devlink_rate); } } + devl_rate_unlock(devlink); } EXPORT_SYMBOL_GPL(devl_rate_nodes_destroy); --=20 2.31.1 From nobody Tue Dec 2 00:46:21 2025 Received: from SN4PR2101CU001.outbound.protection.outlook.com (mail-southcentralusazon11012026.outbound.protection.outlook.com [40.93.195.26]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DB1C929A33E; Sun, 23 Nov 2025 07:24:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.93.195.26 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763882646; cv=fail; b=kyBruPV8ft2BQxUcxaf3AsZEhyDcKX+HHJziuwmC5Vf81A5IoUjDlsi8N24BzQWQ4F0Z47tx+d3t+PiLzF2Z9kvH+3/Pvw3XNsMQDvHv7MGA0vJphShy2xs/Dq5wMWOLwwLyKEo0vwGR67t0k4Uzju/jySbMVxpNEYLdtAJRQFs= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763882646; c=relaxed/simple; bh=H6KAI3Olm7BD8Q+V8uGc/XoHS9h5SDKyKzKXzLM9g+g=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Z8d584IAAFEoR3q66DfYwI2Ef7woxTLTS1RGKCrnyOkFIB5Ret0DREIA2Uuj9PF2nlIlwdYl8r0KuSu9kPE0zn4vFEPAXtBO71dZZo922v35EeAdp5srN08gOkxS+rcmiA+sB5GMQbU7uGgZOO2ovxvlkjnnDDLOxv3CYTCv6kA= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=pHZ2NR0O; arc=fail smtp.client-ip=40.93.195.26 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="pHZ2NR0O" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=PyeBALAqX3CZye5MVO/3nm0Jx8pJCbTIoYI/t7fArwYJsCM1kLswZszYu70V+h4L9f8H9QlU7dMF+uLfiMlWJ57nSquFfzr9Mwq9XbYZb5l8x8+PdyJtD2lHEtfuHKySNqM62X7Mrh6uuCI3ItAYkD0RgHmEavsjarCV7UY1XSvG7YxEccyi65DxQfhACKbUX2rQKx638bO57hHv0JKHzv/Bz4FgqiAVxzYygYSYDDizBV3aJPyl6ObGJZ726QuUHLPGFfcMBKJ3WD7YYQZH5GdD6PUkahiZO1iQPtuSaqtQ/qU5/WTf4qui8egvJJB6kjCBccYsgoskPewckNxJOQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=B5DniNffgu6Qz2rhmTFtzXOMPEVkhKMk0T2S6iDPd6o=; b=Tg53gE2VJuy2W4E9QA73ftrryvPESCSKl2N5C8RM3WLjY5MA/NRkrQghWb/Svaxqf+3Jcz0A2uqx4jZQufUH9lURbZR6EJVk166p+naOWrwbAmrKYxuaFl30tPyc1US3Hps+hvHTWZQhysUaxj3p9mJ+P73A4H0c+UocjLHgQU/zotWP9Fj1vBWJLed781IEG3ApNdNFoJ7s4k4JIz/XqleUzh7poOlH59q5A5y4PptefTo6Lr/ob5TFulM+k6npeVEO/kkfucKR9BXXX4G0snJgTG+0GB4E9FFyvdP6Tr4ITuUyvQCZLJ0ldIORB2sV5ctoHVum8I/ofxWellxcpg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=google.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=B5DniNffgu6Qz2rhmTFtzXOMPEVkhKMk0T2S6iDPd6o=; b=pHZ2NR0OSzXs9Bhx89gQE9nDhVYKlR6KpbsE1TadUeW1o/pO8lY7oHDhW0h38m50jOQHM+TV5vt3qcBVmVF00Ujoe5vsOoaPVVjL/5+eoICZQs4KK9IeJXV9QAqwCOxsHuNuPY0lkswctisQGL39IKvnr+ThHNiYxjF+ciSz6S8oUDb2LRDZCXst36n5/CFKdUdRdf5nkPTLITSA2Anp6HjNMBTeD38OlajOt8lSQpVwxmAR9GZU4AN0w0Ng13ABrLIjZBfXKjDE3LVWaGVP5xDYgJ99+T4kdztNnhgT6fJRyM5tBKEqaDevcZ8NsQOt47XGlGa4K+o3D8uWzWcKcQ== Received: from CH0P220CA0018.NAMP220.PROD.OUTLOOK.COM (2603:10b6:610:ef::30) by PH0PR12MB8774.namprd12.prod.outlook.com (2603:10b6:510:28e::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9343.15; Sun, 23 Nov 2025 07:23:59 +0000 Received: from DS2PEPF00003441.namprd04.prod.outlook.com (2603:10b6:610:ef:cafe::69) by CH0P220CA0018.outlook.office365.com (2603:10b6:610:ef::30) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9343.16 via Frontend Transport; Sun, 23 Nov 2025 07:23:39 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by DS2PEPF00003441.mail.protection.outlook.com (10.167.17.68) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9366.7 via Frontend Transport; Sun, 23 Nov 2025 07:23:58 +0000 Received: from rnnvmail202.nvidia.com (10.129.68.7) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Sat, 22 Nov 2025 23:23:49 -0800 Received: from rnnvmail201.nvidia.com (10.129.68.8) by rnnvmail202.nvidia.com (10.129.68.7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Sat, 22 Nov 2025 23:23:48 -0800 Received: from vdi.nvidia.com (10.127.8.10) by mail.nvidia.com (10.129.68.8) with Microsoft SMTP Server id 15.2.2562.20 via Frontend Transport; Sat, 22 Nov 2025 23:23:43 -0800 From: Tariq Toukan To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Donald Hunter , Jiri Pirko , Jonathan Corbet , Saeed Mahameed , "Leon Romanovsky" , Tariq Toukan , Mark Bloch , , , , , Gal Pressman , Moshe Shemesh , Carolina Jubran , Cosmin Ratiu , Jiri Pirko Subject: [PATCH net-next V2 06/14] devlink: Add parent dev to devlink API Date: Sun, 23 Nov 2025 09:22:52 +0200 Message-ID: <1763882580-1295213-7-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1763882580-1295213-1-git-send-email-tariqt@nvidia.com> References: <1763882580-1295213-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF00003441:EE_|PH0PR12MB8774:EE_ X-MS-Office365-Filtering-Correlation-Id: 7d4a358f-dbc4-4f50-44fb-08de2a6144a9 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|7416014|376014|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?EytidXjNv1WFN1BDO0kTQKA/LHoGTBEyYLXGqQHR1e7juxVRUaBQOvTNL0jJ?= =?us-ascii?Q?Edi2SHCiVpSz+Yd8G0jzCXaPaRCvi5klfA/4eX3fpfGOc7SmBVbP3zwMZxiW?= =?us-ascii?Q?ukyu/yi9Kez739uPZI9TCGdhVE4ANcfzW6vKqeGkYlnu/ViGIhN/GkhCaHLX?= =?us-ascii?Q?Orn9maGIxwXY9tuVpc5ImFA42hgcAEaMewvwkRD0+1t26wCZNswJUHWAX4tt?= =?us-ascii?Q?FnsN9rtjPeyKYTjqcDcCBi7ZSCtPunk+3utvE3irvDpk29F9Bvld8KaX6jRM?= =?us-ascii?Q?RaEeCs/wZBOSw2ydcykz1az7L0YCr6cdI3XCalVfiVey8RWkonZkjUQtJmDq?= =?us-ascii?Q?oio3F7w3nfqlMoDx9Ng5vLtCzB4GW4fyaWkraCJY95J4VG+4x6gE9kohALFK?= =?us-ascii?Q?HwfdzEkPUBO1k+l0oOE2C5y5bTP2w72fVcIdQueDn1PeNn5VKRGZczpL0ECI?= =?us-ascii?Q?qqy5JalBftWKond+PRKtjHHEvdDYXS/awnXl4nYj9+CN4NE+1qP0eu5cO7Lo?= =?us-ascii?Q?LYk8NfXk8JmGzb7dWcACzZW/D5Ytp+/4WRbzNQ+Nh1ijqfWJwa/j9UAKSyu5?= =?us-ascii?Q?ZwMOi2ntAFNtOALJodsPAib9H6O8uiFShxXcn+M41MX0t4KMGGfXMZbbEyP8?= =?us-ascii?Q?xlBW2rvLRW9pzBPzNTTxpl/AUIhe9a3+PeUMBijBgexsDnBQy+VS6JEf4yMW?= =?us-ascii?Q?VG+/P7p8PQtLuWTjwAXPKUBiR1/cZm6Q/Zd7oV3FybUMD+ZoOqiM44qkKlLZ?= =?us-ascii?Q?PJxpxR//ooDNKKH2qh4Bbn4ha890da92mTZ/hv11eXc3y0lmGpkLorymoob5?= =?us-ascii?Q?uJUoYxYHMC7PVTjPL3uBPdkJCAa9LOb9usBpzi77kIs8z1btccsnBzC8iT9C?= =?us-ascii?Q?tRIu54mGVptBLEBBL0eHeUmuW6mcDyL93G9OUbSIbX0HqLaFYjGHPk7Khgxq?= =?us-ascii?Q?K3TXpoy4kF6MybpIH8Eg46LDlHoNqe+r5zrgvLkD4Nblterz8ftKYoo8Tos5?= =?us-ascii?Q?70xou3zJKwkQxdeWquGW5uYC5aVYfDbmggluuRgjsMbRp11p3m21s6E5vN2z?= =?us-ascii?Q?sM+IoxFEyR/P1NgqCribaymm9MMyDFc9S/Y41PwC3qI8BozTEnU5SceGjukM?= =?us-ascii?Q?+P2onI+OzSPRTRCsW4nhQVdq6AyEUrEHP4BhDhdM/Ivz44GU1wyyy3DaTQNl?= =?us-ascii?Q?WQO/Mgi4XLzusxHKAbHlssB2uN+qwrF5QgoiokxXUYrfUxf8Ig91cQ8RT5V/?= =?us-ascii?Q?SKs9et9pgJYKJfGRVI2mxPagI1A/+khXE/eoN4WYmZxXa7uPSP0bQTu5NNPc?= =?us-ascii?Q?JHa4ZhHcr2aXpSkLUd/Igjn3EzbFijVghdwpk5OhyCajV41laH6/gbCdXozM?= =?us-ascii?Q?IA3VwL1X3mAtrt5/DwFhKbq7AFxaKZ3wKtYPfcSGX8kmeMDccaQmQwxKIcJw?= =?us-ascii?Q?8uNSxLDnoI1v45juwqng7OZZxLdSf29SuOiq6YKxv2sapoNQH3dJ0Qor8C1o?= =?us-ascii?Q?cbpJW2Z1rzhUGrDYA54rx+KX8j90dcWQynitMVWuc2b8JCpuaxkiySEKYBYO?= =?us-ascii?Q?Xbl5JSNaSGSFu9dCAY8=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(1800799024)(7416014)(376014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Nov 2025 07:23:58.3850 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7d4a358f-dbc4-4f50-44fb-08de2a6144a9 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF00003441.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB8774 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Cosmin Ratiu Upcoming changes to the rate commands need the parent devlink specified. This change adds a nested 'parent-dev' attribute to the API and helpers to obtain and put a reference to the parent devlink instance in info->user_ptr[1]. To avoid deadlocks, the parent devlink is unlocked before obtaining the main devlink instance that is the target of the request. A reference to the parent is kept until the end of the request to avoid it suddenly disappearing. This means that this reference is of limited use without additional protection. Signed-off-by: Cosmin Ratiu Reviewed-by: Carolina Jubran Reviewed-by: Jiri Pirko Signed-off-by: Tariq Toukan --- Documentation/netlink/specs/devlink.yaml | 11 ++++ include/uapi/linux/devlink.h | 2 + net/devlink/devl_internal.h | 2 + net/devlink/netlink.c | 67 ++++++++++++++++++++++-- net/devlink/netlink_gen.c | 5 ++ net/devlink/netlink_gen.h | 8 +++ 6 files changed, 90 insertions(+), 5 deletions(-) diff --git a/Documentation/netlink/specs/devlink.yaml b/Documentation/netli= nk/specs/devlink.yaml index 837112da6738..1f41d934dc5b 100644 --- a/Documentation/netlink/specs/devlink.yaml +++ b/Documentation/netlink/specs/devlink.yaml @@ -867,6 +867,9 @@ attribute-sets: type: flag doc: Request restoring parameter to its default value. value: 183 + - name: parent-dev + type: nest + nested-attributes: dl-parent-dev - name: dl-dev-stats subset-of: devlink @@ -1289,6 +1292,14 @@ attribute-sets: Specifies the bandwidth share assigned to the Traffic Class. The bandwidth for the traffic class is determined in proportion to the sum of the shares of all configured clas= ses. + - + name: dl-parent-dev + subset-of: devlink + attributes: + - + name: bus-name + - + name: dev-name =20 operations: enum-model: directional diff --git a/include/uapi/linux/devlink.h b/include/uapi/linux/devlink.h index e7d6b6d13470..94b8a4437bac 100644 --- a/include/uapi/linux/devlink.h +++ b/include/uapi/linux/devlink.h @@ -642,6 +642,8 @@ enum devlink_attr { DEVLINK_ATTR_PARAM_VALUE_DEFAULT, /* dynamic */ DEVLINK_ATTR_PARAM_RESET_DEFAULT, /* flag */ =20 + DEVLINK_ATTR_PARENT_DEV, /* nested */ + /* Add new attributes above here, update the spec in * Documentation/netlink/specs/devlink.yaml and re-generate * net/devlink/netlink_gen.c. diff --git a/net/devlink/devl_internal.h b/net/devlink/devl_internal.h index 8374c9cab6ce..3ca4cc8517cd 100644 --- a/net/devlink/devl_internal.h +++ b/net/devlink/devl_internal.h @@ -162,6 +162,8 @@ typedef int devlink_nl_dump_one_func_t(struct sk_buff *= msg, struct devlink * devlink_get_from_attrs_lock(struct net *net, struct nlattr **attrs, bool dev_lock); +struct devlink * +devlink_get_parent_from_attrs_lock(struct net *net, struct nlattr **attrs); =20 int devlink_nl_dumpit(struct sk_buff *msg, struct netlink_callback *cb, devlink_nl_dump_one_func_t *dump_one); diff --git a/net/devlink/netlink.c b/net/devlink/netlink.c index 593605c1b1ef..781758b8632c 100644 --- a/net/devlink/netlink.c +++ b/net/devlink/netlink.c @@ -12,6 +12,7 @@ #define DEVLINK_NL_FLAG_NEED_PORT BIT(0) #define DEVLINK_NL_FLAG_NEED_DEVLINK_OR_PORT BIT(1) #define DEVLINK_NL_FLAG_NEED_DEV_LOCK BIT(2) +#define DEVLINK_NL_FLAG_OPTIONAL_PARENT_DEV BIT(3) =20 static const struct genl_multicast_group devlink_nl_mcgrps[] =3D { [DEVLINK_MCGRP_CONFIG] =3D { .name =3D DEVLINK_GENL_MCGRP_CONFIG_NAME }, @@ -206,19 +207,51 @@ devlink_get_from_attrs_lock(struct net *net, struct n= lattr **attrs, return ERR_PTR(-ENODEV); } =20 +struct devlink * +devlink_get_parent_from_attrs_lock(struct net *net, struct nlattr **attrs) +{ + struct nlattr *tb[DEVLINK_ATTR_DEV_NAME + 1]; + int err; + + if (!attrs[DEVLINK_ATTR_PARENT_DEV]) + return ERR_PTR(-EINVAL); + + err =3D nla_parse_nested(tb, DEVLINK_ATTR_DEV_NAME, + attrs[DEVLINK_ATTR_PARENT_DEV], + devlink_dl_parent_dev_nl_policy, NULL); + if (err) + return ERR_PTR(err); + + return devlink_get_from_attrs_lock(net, tb, false); +} + static int __devlink_nl_pre_doit(struct sk_buff *skb, struct genl_info *in= fo, u8 flags) { + bool parent_dev =3D flags & DEVLINK_NL_FLAG_OPTIONAL_PARENT_DEV; bool dev_lock =3D flags & DEVLINK_NL_FLAG_NEED_DEV_LOCK; + struct devlink *devlink, *parent_devlink =3D NULL; + struct net *net =3D genl_info_net(info); + struct nlattr **attrs =3D info->attrs; struct devlink_port *devlink_port; - struct devlink *devlink; int err; =20 - devlink =3D devlink_get_from_attrs_lock(genl_info_net(info), info->attrs, - dev_lock); - if (IS_ERR(devlink)) - return PTR_ERR(devlink); + if (parent_dev && attrs[DEVLINK_ATTR_PARENT_DEV]) { + parent_devlink =3D devlink_get_parent_from_attrs_lock(net, attrs); + if (IS_ERR(parent_devlink)) + return PTR_ERR(parent_devlink); + info->user_ptr[1] =3D parent_devlink; + /* Drop the parent devlink lock but don't release the reference. + * This will keep it alive until the end of the request. + */ + devl_unlock(parent_devlink); + } =20 + devlink =3D devlink_get_from_attrs_lock(net, attrs, dev_lock); + if (IS_ERR(devlink)) { + err =3D PTR_ERR(devlink); + goto parent_put; + } info->user_ptr[0] =3D devlink; if (flags & DEVLINK_NL_FLAG_NEED_PORT) { devlink_port =3D devlink_port_get_from_info(devlink, info); @@ -237,6 +270,9 @@ static int __devlink_nl_pre_doit(struct sk_buff *skb, s= truct genl_info *info, unlock: devl_dev_unlock(devlink, dev_lock); devlink_put(devlink); +parent_put: + if (parent_dev && parent_devlink) + devlink_put(parent_devlink); return err; } =20 @@ -265,6 +301,14 @@ int devlink_nl_pre_doit_port_optional(const struct gen= l_split_ops *ops, return __devlink_nl_pre_doit(skb, info, DEVLINK_NL_FLAG_NEED_DEVLINK_OR_P= ORT); } =20 +int devlink_nl_pre_doit_parent_dev_optional(const struct genl_split_ops *o= ps, + struct sk_buff *skb, + struct genl_info *info) +{ + return __devlink_nl_pre_doit(skb, info, + DEVLINK_NL_FLAG_OPTIONAL_PARENT_DEV); +} + static void __devlink_nl_post_doit(struct sk_buff *skb, struct genl_info *= info, u8 flags) { @@ -274,6 +318,11 @@ static void __devlink_nl_post_doit(struct sk_buff *skb= , struct genl_info *info, devlink =3D info->user_ptr[0]; devl_dev_unlock(devlink, dev_lock); devlink_put(devlink); + if ((flags & DEVLINK_NL_FLAG_OPTIONAL_PARENT_DEV) && + info->user_ptr[1]) { + devlink =3D info->user_ptr[1]; + devlink_put(devlink); + } } =20 void devlink_nl_post_doit(const struct genl_split_ops *ops, @@ -289,6 +338,14 @@ devlink_nl_post_doit_dev_lock(const struct genl_split_= ops *ops, __devlink_nl_post_doit(skb, info, DEVLINK_NL_FLAG_NEED_DEV_LOCK); } =20 +void +devlink_nl_post_doit_parent_dev_optional(const struct genl_split_ops *ops, + struct sk_buff *skb, + struct genl_info *info) +{ + __devlink_nl_post_doit(skb, info, DEVLINK_NL_FLAG_OPTIONAL_PARENT_DEV); +} + static int devlink_nl_inst_single_dumpit(struct sk_buff *msg, struct netlink_callback *cb, int flags, devlink_nl_dump_one_func_t *dump_one, diff --git a/net/devlink/netlink_gen.c b/net/devlink/netlink_gen.c index 580985025f49..8fbe0417ab55 100644 --- a/net/devlink/netlink_gen.c +++ b/net/devlink/netlink_gen.c @@ -38,6 +38,11 @@ devlink_attr_param_type_validate(const struct nlattr *at= tr, } =20 /* Common nested types */ +const struct nla_policy devlink_dl_parent_dev_nl_policy[DEVLINK_ATTR_DEV_N= AME + 1] =3D { + [DEVLINK_ATTR_BUS_NAME] =3D { .type =3D NLA_NUL_STRING, }, + [DEVLINK_ATTR_DEV_NAME] =3D { .type =3D NLA_NUL_STRING, }, +}; + const struct nla_policy devlink_dl_port_function_nl_policy[DEVLINK_PORT_FN= _ATTR_CAPS + 1] =3D { [DEVLINK_PORT_FUNCTION_ATTR_HW_ADDR] =3D { .type =3D NLA_BINARY, }, [DEVLINK_PORT_FN_ATTR_STATE] =3D NLA_POLICY_MAX(NLA_U8, 1), diff --git a/net/devlink/netlink_gen.h b/net/devlink/netlink_gen.h index 09cc6f264ccf..94566cab1734 100644 --- a/net/devlink/netlink_gen.h +++ b/net/devlink/netlink_gen.h @@ -12,6 +12,7 @@ #include =20 /* Common nested types */ +extern const struct nla_policy devlink_dl_parent_dev_nl_policy[DEVLINK_ATT= R_DEV_NAME + 1]; extern const struct nla_policy devlink_dl_port_function_nl_policy[DEVLINK_= PORT_FN_ATTR_CAPS + 1]; extern const struct nla_policy devlink_dl_rate_tc_bws_nl_policy[DEVLINK_RA= TE_TC_ATTR_BW + 1]; extern const struct nla_policy devlink_dl_selftest_id_nl_policy[DEVLINK_AT= TR_SELFTEST_ID_FLASH + 1]; @@ -28,12 +29,19 @@ int devlink_nl_pre_doit_dev_lock(const struct genl_spli= t_ops *ops, int devlink_nl_pre_doit_port_optional(const struct genl_split_ops *ops, struct sk_buff *skb, struct genl_info *info); +int devlink_nl_pre_doit_parent_dev_optional(const struct genl_split_ops *o= ps, + struct sk_buff *skb, + struct genl_info *info); void devlink_nl_post_doit(const struct genl_split_ops *ops, struct sk_buff *skb, struct genl_info *info); void devlink_nl_post_doit_dev_lock(const struct genl_split_ops *ops, struct sk_buff *skb, struct genl_info *info); +void +devlink_nl_post_doit_parent_dev_optional(const struct genl_split_ops *ops, + struct sk_buff *skb, + struct genl_info *info); =20 int devlink_nl_get_doit(struct sk_buff *skb, struct genl_info *info); int devlink_nl_get_dumpit(struct sk_buff *skb, struct netlink_callback *cb= ); --=20 2.31.1 From nobody Tue Dec 2 00:46:21 2025 Received: from CY3PR05CU001.outbound.protection.outlook.com (mail-westcentralusazon11013013.outbound.protection.outlook.com [40.93.201.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5EACD2D1914; Sun, 23 Nov 2025 07:24:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.93.201.13 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763882654; cv=fail; b=eD0aVdhQrkRbNDduzicum7sIWfeUn5yLtI+QBh0leEYrQwlBhQ/+YCuTiu/VNjI5PVMIDLOb3jXP0Nj03eByzXjB1PtpfuwI4F3Z2y/BTnjzG+MNRdv9nirTqK0BNxQpHIregfszbOv4p7UYjgoV7AmQ//K2oeg8BRIq2f0vuZs= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763882654; c=relaxed/simple; bh=j+JpDB8lrUITToa6HtXVUiQKkYMS06iYiub1LMNjBWI=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=epsQHFuQXLMrAqnMlZquNN72ByzrKPBnI/iBs7FOh4exyW13ZKhv5wGMO0R1zmUcOGm7PUrQD1iq0IpsGizZCDIBNj9rYaPhmbIyEcSeRXpsXlDSrzzn/q7OhKz/HEVOQ6XTGGjRvLKkAgNK37GElcWc+G1FIdy9P8bsswbyHYk= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=ZsZrJqI3; arc=fail smtp.client-ip=40.93.201.13 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="ZsZrJqI3" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=zRp9U6NrFNMVtjCPetxFeIhUqF4fJwBHh7sV90wsZq7EoiM85ffyLgc+jv7RJACOmNEBN8sU7ZFXKz2dJqRIAmxKQc24EaQvv/TXKfrybxP/1fHfrYRr29NWnxuK0aAc0ZIDzsyLio7elMfMGRM7oX07eSk8SVjLj+YMsZXray2jsPq6gqlAlAiNCpI2nWVH05tTXlY810tp+rEzopEPBcgVm6iXCv8eLkobm0y/T+iZuhD/NOX/C/SENi4iktQ4mfwGwUKEX2u2Xh9nnTaBUj1l25IJV+1Nm55YjdB8WoeZW9JMbmA3GvtCTQNvJvrFn523vQiGYiTfDJO5Ko4c7Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=E7MGL78J8w1FDJhYk01+ZTwT+lZwV/itnX/hL3p0kBQ=; b=TY5w2XV7nq82MGzgCkrANVBX0/tDOoncbQDr5I2oZwh1Uy3sBAX7iMPqCJfDs1dfT4l+Rei+YMcV/Hl97FjefZW+X1hi0aQV60/orxITLSkyxzu9H0njY267Jo+3IVVfqaW2+Pf5i3L33lNfdytt5fXJbbK1O8L+HHLo6EhWkXanAkA42RtUezinVSKVnYyoOv3OapRiGLUC9aDNtnkczA3Ne1D12DfkxauuKub8IpmVWjg2hSO6ncgYJuI7K1f3pl30wXoCbboXNb7CIt6tfSodis0SuD2SmUswWfsUHhAphZUQnJGmshiXt/2EiqqZbwsiQVOKvVTTn8IqIZIODQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=google.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=E7MGL78J8w1FDJhYk01+ZTwT+lZwV/itnX/hL3p0kBQ=; b=ZsZrJqI3IL7B1iGTjO16sQkI+i9LpL/R1ZcFc75evuk3d9/fBEHg+OGO0dPYTJh869Vugwmx0lqdYFFoDOAjcMDlYhUdC7yKUeL2K1/RzW1NPGY5iNLl7vbeOfiUVmWDN4AvgNDOV7x3dlGnK6IGD4CktG0V9Wjtr8k+IJiz1P4KigIeTmkiO6+im9aQdRnFSl4q0NsAx9dujJmp/w9IyWop9Lb/m0YOP7NJ463XmaFa9oH3qc6xFRI5I1mRxr9fag/qJRS5UGFknra5wityZIv2/tKdLD3iZLqVKzPcio1RQYzuwMBF31+sOeUsvN4yf3RcVaa6N07tVhIPRdtd1g== Received: from PH5P220CA0008.NAMP220.PROD.OUTLOOK.COM (2603:10b6:510:34a::6) by PH7PR12MB7308.namprd12.prod.outlook.com (2603:10b6:510:20c::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9343.15; Sun, 23 Nov 2025 07:24:07 +0000 Received: from SN1PEPF000397B4.namprd05.prod.outlook.com (2603:10b6:510:34a:cafe::4e) by PH5P220CA0008.outlook.office365.com (2603:10b6:510:34a::6) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9343.17 via Frontend Transport; Sun, 23 Nov 2025 07:24:20 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by SN1PEPF000397B4.mail.protection.outlook.com (10.167.248.58) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9366.7 via Frontend Transport; Sun, 23 Nov 2025 07:24:06 +0000 Received: from rnnvmail203.nvidia.com (10.129.68.9) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Sat, 22 Nov 2025 23:23:55 -0800 Received: from rnnvmail201.nvidia.com (10.129.68.8) by rnnvmail203.nvidia.com (10.129.68.9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Sat, 22 Nov 2025 23:23:54 -0800 Received: from vdi.nvidia.com (10.127.8.10) by mail.nvidia.com (10.129.68.8) with Microsoft SMTP Server id 15.2.2562.20 via Frontend Transport; Sat, 22 Nov 2025 23:23:49 -0800 From: Tariq Toukan To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Donald Hunter , Jiri Pirko , Jonathan Corbet , Saeed Mahameed , "Leon Romanovsky" , Tariq Toukan , Mark Bloch , , , , , Gal Pressman , Moshe Shemesh , Carolina Jubran , Cosmin Ratiu , Jiri Pirko Subject: [PATCH net-next V2 07/14] devlink: Allow parent dev for rate-set and rate-new Date: Sun, 23 Nov 2025 09:22:53 +0200 Message-ID: <1763882580-1295213-8-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1763882580-1295213-1-git-send-email-tariqt@nvidia.com> References: <1763882580-1295213-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000397B4:EE_|PH7PR12MB7308:EE_ X-MS-Office365-Filtering-Correlation-Id: cd71e4d6-237e-45bb-a29f-08de2a6149be X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|7416014|82310400026|376014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?4uaVownBJs2XkFx+SPJuqqTBqDRwa1Sk+1BMQfSkKiUa/MZQLzpqr2uM9E5Z?= =?us-ascii?Q?KGy5l15iUnAPxI6jC0us5pdsPHbsACtNFWcmCyIjvuMdrIQpRrpCAaOsMXLg?= =?us-ascii?Q?6fAt0Q6JstnnFSdTWQ7bx4RQATsVYg2IFGUq6vfEijlVGxgUdXXYMcN4bLAq?= =?us-ascii?Q?sAII9wSQ/lcELFcG/rKNqWYJAkZbRbxC1EfD1NjkRrdoj/4hP3fgD3tjIKuc?= =?us-ascii?Q?EKsa4dxax5JZeziwD8UPT9tRF6DHksm7vaF9gI/JN4D01dJP5IGjxm9E0nSL?= =?us-ascii?Q?mjUw6VQ54QgTY/ujCFfSDTuAfofMJIFzizfR8mZE9AAHwHML13uVwZHWMMY6?= =?us-ascii?Q?VS/rvSAZEmpE/tGfmA5fcXf0xfDldPuO+q+15giAI+QRuCM+SN6UWbFnbym8?= =?us-ascii?Q?ZSt7JwYwGXZ+3oTXabSsZ49KCSzG2ymxkUD8eAYKEvopMIqGRZouIzvLTLRI?= =?us-ascii?Q?Qn4lRswkTARyxwEh+auQ/Uy1haiCWim23IRM+shfhss6FR905LmmpjXUKl0O?= =?us-ascii?Q?x92c5iE0Hv7P2lHZPrRykJqJ+ULkLi7S9wE4M8VKMIAH2DRGQzfNUgHegYwp?= =?us-ascii?Q?5RmNFqD/3Mgjt+0LmrkbcNDiOfZIxNQmpj+h80B/kxglj1GKL4DJu+hga9PK?= =?us-ascii?Q?GNmy/sl0i5SQZBm1LCk7grTpigVx8qA/ztRE7mQOv/cuNC/5QeT0iSoo7m8F?= =?us-ascii?Q?2WvlWhN2wpPOxdOuFze3/A0BsAv8qvRjOZGfl6VCSEWIcBvJzkeVQ0b9C+E8?= =?us-ascii?Q?CcV0jnw7FFAtrAhsa2+556JDUVdc6ULwLlHNF5FfZEhTo9zh9ZjHD5YSUr0E?= =?us-ascii?Q?gyPZU0kKKEABL6qmPIz4FoiIyZlLeFguc8VvfoOJhLBrbq5vUGqAxg6W1ELp?= =?us-ascii?Q?nlW8G/G9xG4ymVbeMY5cXcxPSbx3BcPMBIEj8sJDr/W9g3cQS3I4R0W4SniI?= =?us-ascii?Q?V6gi3WOeend4dfyX/mFmjsdLQUqdJoNYmsC8KDG4yrjo3AI6Q/4OSn7t80mi?= =?us-ascii?Q?QxVJpqYZ+e+WkDJqeuvsemFZxoxRR/lsHnnCWnIFvZm7BQV7t39i/IxahdcR?= =?us-ascii?Q?ZrNqieK+LMdzhYXNx+gTkj4TBaM0nlfq/++Hp8C71c6u76uRWlsIPevAtJX3?= =?us-ascii?Q?6MHseLkWTx3Fzp1kYaAoypwPO24Zmvkquvk1cdGPrhK+1DgkzOfJ86FZ0g0o?= =?us-ascii?Q?lnNyT5iTWmSw/KQySRpEeOHji5ESryYrN5PxXZkFNjwQgz+fHLnYAvldLPGE?= =?us-ascii?Q?PQEUBC+1bYpzuJznCAYI5/SIZyuZmavDYobS0RSQEfEOzt4MWlRYbSveA/g7?= =?us-ascii?Q?2AydyGqTLp5/Pu2/DcHejmT9wPnGneYTiOxDEZva0YS9A3FqQAMnHGxmy5Q7?= =?us-ascii?Q?7ijMT6VK9ff1uijpGYtD3RqdYIFH/INW49nouCunXTC0WWrBdhHQdNKT1aCU?= =?us-ascii?Q?MAYrNs5CMP5S9GrZD5gGWaBrq6D33MaV0y7B6bA7+s1yohKVQe6lZ0E9Qu2c?= =?us-ascii?Q?qbq+pgoRhUUckcAZk605Ko7DjBIUILx1d6M7x2EnudkzfjRSo2LWS01F9V1H?= =?us-ascii?Q?QsddzHgvXy/CebvnYjw=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(1800799024)(7416014)(82310400026)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Nov 2025 07:24:06.8944 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cd71e4d6-237e-45bb-a29f-08de2a6149be X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000397B4.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB7308 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Cosmin Ratiu Currently, a devlink rate's parent device is assumed to be the same as the one where the devlink rate is created. This patch changes that to allow rate commands to accept an additional argument that specifies the parent dev. This will allow devlink rate groups with leafs from other devices. Example of the new usage with ynl: Creating a group on pci/0000:08:00.1 with a parent to an already existing pci/0000:08:00.1/group1: ./tools/net/ynl/pyynl/cli.py --spec \ Documentation/netlink/specs/devlink.yaml --do rate-new --json '{ "bus-name": "pci", "dev-name": "0000:08:00.1", "rate-node-name": "group2", "rate-parent-node-name": "group1", "parent-dev": { "bus-name": "pci", "dev-name": "0000:08:00.1" } }' Setting the parent of leaf node pci/0000:08:00.1/65537 to pci/0000:08:00.0/group1: ./tools/net/ynl/pyynl/cli.py --spec \ Documentation/netlink/specs/devlink.yaml --do rate-set --json '{ "bus-name": "pci", "dev-name": "0000:08:00.1", "port-index": 65537, "parent-dev": { "bus-name": "pci", "dev-name": "0000:08:00.0" }, "rate-parent-node-name": "group1" }' Signed-off-by: Cosmin Ratiu Reviewed-by: Carolina Jubran Reviewed-by: Jiri Pirko Signed-off-by: Tariq Toukan --- Documentation/netlink/specs/devlink.yaml | 10 ++++++---- net/devlink/netlink_gen.c | 18 ++++++++++-------- 2 files changed, 16 insertions(+), 12 deletions(-) diff --git a/Documentation/netlink/specs/devlink.yaml b/Documentation/netli= nk/specs/devlink.yaml index 1f41d934dc5b..bfeacfcfdf9e 100644 --- a/Documentation/netlink/specs/devlink.yaml +++ b/Documentation/netlink/specs/devlink.yaml @@ -2217,8 +2217,8 @@ operations: dont-validate: [strict] flags: [admin-perm] do: - pre: devlink-nl-pre-doit - post: devlink-nl-post-doit + pre: devlink-nl-pre-doit-parent-dev-optional + post: devlink-nl-post-doit-parent-dev-optional request: attributes: - bus-name @@ -2230,6 +2230,7 @@ operations: - rate-tx-weight - rate-parent-node-name - rate-tc-bws + - parent-dev =20 - name: rate-new @@ -2238,8 +2239,8 @@ operations: dont-validate: [strict] flags: [admin-perm] do: - pre: devlink-nl-pre-doit - post: devlink-nl-post-doit + pre: devlink-nl-pre-doit-parent-dev-optional + post: devlink-nl-post-doit-parent-dev-optional request: attributes: - bus-name @@ -2251,6 +2252,7 @@ operations: - rate-tx-weight - rate-parent-node-name - rate-tc-bws + - parent-dev =20 - name: rate-del diff --git a/net/devlink/netlink_gen.c b/net/devlink/netlink_gen.c index 8fbe0417ab55..91d2c9b69391 100644 --- a/net/devlink/netlink_gen.c +++ b/net/devlink/netlink_gen.c @@ -535,7 +535,7 @@ static const struct nla_policy devlink_rate_get_dump_nl= _policy[DEVLINK_ATTR_DEV_ }; =20 /* DEVLINK_CMD_RATE_SET - do */ -static const struct nla_policy devlink_rate_set_nl_policy[DEVLINK_ATTR_RAT= E_TC_BWS + 1] =3D { +static const struct nla_policy devlink_rate_set_nl_policy[DEVLINK_ATTR_PAR= ENT_DEV + 1] =3D { [DEVLINK_ATTR_BUS_NAME] =3D { .type =3D NLA_NUL_STRING, }, [DEVLINK_ATTR_DEV_NAME] =3D { .type =3D NLA_NUL_STRING, }, [DEVLINK_ATTR_RATE_NODE_NAME] =3D { .type =3D NLA_NUL_STRING, }, @@ -545,10 +545,11 @@ static const struct nla_policy devlink_rate_set_nl_po= licy[DEVLINK_ATTR_RATE_TC_B [DEVLINK_ATTR_RATE_TX_WEIGHT] =3D { .type =3D NLA_U32, }, [DEVLINK_ATTR_RATE_PARENT_NODE_NAME] =3D { .type =3D NLA_NUL_STRING, }, [DEVLINK_ATTR_RATE_TC_BWS] =3D NLA_POLICY_NESTED(devlink_dl_rate_tc_bws_n= l_policy), + [DEVLINK_ATTR_PARENT_DEV] =3D NLA_POLICY_NESTED(devlink_dl_parent_dev_nl_= policy), }; =20 /* DEVLINK_CMD_RATE_NEW - do */ -static const struct nla_policy devlink_rate_new_nl_policy[DEVLINK_ATTR_RAT= E_TC_BWS + 1] =3D { +static const struct nla_policy devlink_rate_new_nl_policy[DEVLINK_ATTR_PAR= ENT_DEV + 1] =3D { [DEVLINK_ATTR_BUS_NAME] =3D { .type =3D NLA_NUL_STRING, }, [DEVLINK_ATTR_DEV_NAME] =3D { .type =3D NLA_NUL_STRING, }, [DEVLINK_ATTR_RATE_NODE_NAME] =3D { .type =3D NLA_NUL_STRING, }, @@ -558,6 +559,7 @@ static const struct nla_policy devlink_rate_new_nl_poli= cy[DEVLINK_ATTR_RATE_TC_B [DEVLINK_ATTR_RATE_TX_WEIGHT] =3D { .type =3D NLA_U32, }, [DEVLINK_ATTR_RATE_PARENT_NODE_NAME] =3D { .type =3D NLA_NUL_STRING, }, [DEVLINK_ATTR_RATE_TC_BWS] =3D NLA_POLICY_NESTED(devlink_dl_rate_tc_bws_n= l_policy), + [DEVLINK_ATTR_PARENT_DEV] =3D NLA_POLICY_NESTED(devlink_dl_parent_dev_nl_= policy), }; =20 /* DEVLINK_CMD_RATE_DEL - do */ @@ -1201,21 +1203,21 @@ const struct genl_split_ops devlink_nl_ops[74] =3D { { .cmd =3D DEVLINK_CMD_RATE_SET, .validate =3D GENL_DONT_VALIDATE_STRICT, - .pre_doit =3D devlink_nl_pre_doit, + .pre_doit =3D devlink_nl_pre_doit_parent_dev_optional, .doit =3D devlink_nl_rate_set_doit, - .post_doit =3D devlink_nl_post_doit, + .post_doit =3D devlink_nl_post_doit_parent_dev_optional, .policy =3D devlink_rate_set_nl_policy, - .maxattr =3D DEVLINK_ATTR_RATE_TC_BWS, + .maxattr =3D DEVLINK_ATTR_PARENT_DEV, .flags =3D GENL_ADMIN_PERM | GENL_CMD_CAP_DO, }, { .cmd =3D DEVLINK_CMD_RATE_NEW, .validate =3D GENL_DONT_VALIDATE_STRICT, - .pre_doit =3D devlink_nl_pre_doit, + .pre_doit =3D devlink_nl_pre_doit_parent_dev_optional, .doit =3D devlink_nl_rate_new_doit, - .post_doit =3D devlink_nl_post_doit, + .post_doit =3D devlink_nl_post_doit_parent_dev_optional, .policy =3D devlink_rate_new_nl_policy, - .maxattr =3D DEVLINK_ATTR_RATE_TC_BWS, + .maxattr =3D DEVLINK_ATTR_PARENT_DEV, .flags =3D GENL_ADMIN_PERM | GENL_CMD_CAP_DO, }, { --=20 2.31.1 From nobody Tue Dec 2 00:46:21 2025 Received: from SJ2PR03CU001.outbound.protection.outlook.com (mail-westusazon11012047.outbound.protection.outlook.com [52.101.43.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7FE4D2D2493; Sun, 23 Nov 2025 07:24:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.43.47 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763882656; cv=fail; b=nRf4JYp0SwegYhv7zN9tHyRJG08DSLWmS7iqHeUdvkH3Tghkq4MfOBJURcj0tCQKqHYJ/akaMCKh2UlnNWx4dJJEnG5bomOAHWoF/WpjIdbYRjyO4WK4N+jRrOksMcn6Jj7mQa41nmOB6BBY9vIfV4NV8NmJ8QIutDkXd41w/xY= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763882656; c=relaxed/simple; bh=e4UMip5zlJLjD4EFppWhVW2MYA1Sj1FMnNI5AkYneqo=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=bps4DnyQIjJRjxjj4DLg95IKvvrn0JObeDrWknDIVD7/1nwxTm7fq5rZlbNY4kckE7n68iPZd9lVnZImA0FGNIdoOUiZECgCNGT4rgDCBF+zgN9nlAFCqeXAyikRUfHpIt+Lf/5JItORkYtcHeHwD6mGWoOip2ID22ybZ3nICM0= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=UVbOyHB4; arc=fail smtp.client-ip=52.101.43.47 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="UVbOyHB4" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=vBnbNY58FUV1gZMwh1QozA/fDixIO0xKH1tUndIkrxs4aEtLzRGm45xR9ZW3fjGxOZj+mR6NxTe+0Gilf7Ontc2JJJxQH4OZ1FXnEaH1AeT+lk0xGEk3OLXAAa0uRUqpiv1XPgSTcUsp5StSdn8FaBmvGrIxETMHOKFNhq0g/ICY735MpTS880TPu927/pRROgy+hCllRc0EKLmmwF/SW2rgGcEJ1t3X0vGsKWn/U0Ck+1BNijcR7nt90EO7hTrO4Jc6U/HIvqSJQZw032PXRfOrPL6IUxIZKE4Q1F0VPMhS3Hz1VI6l6OyRsmIb9BPEq0PAWu/CC75kaShrQGzOyg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=w6WCn79jicBvaRTc7FGjKgqmH+CPsvHhzXkkiOoddIY=; b=IwtsJjxUk552NXI0FevV0nvsbaL7HRjd40+1PtNwMukOqmQ4kKQbAPPjFfm3gc2vxE8efH2CM2K4iblJ8n5q0bVPEH0CyDHi2melIlnGA6lNEaPFM5AMN2XCoEAwxGZGXZord1kKQ6+I1c2cQyty1PC95p+BbH103Up/0IjHVm2ZktEik/n8mY8CWHLV7y7qowmsZ0NpL5YNjoyCiqJy2D0IBrHD37H8T6fWGRBnmbQLV9a4xay+GK8xF9cp0nl21C9Pzj232ciHPXWi8ngPhHROm9x9lVooiYbtXvEYmQBHuN0i4TCIs9hLgBtnZTdhVC5lB4Clp3ftYxCL7Um5Sg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=google.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=w6WCn79jicBvaRTc7FGjKgqmH+CPsvHhzXkkiOoddIY=; b=UVbOyHB4qcOxKO+iYsVD7W4qdRTtNbpNxK7EtrC+j3GdaPU0cgC0NOeLWoZtbNKY3MP+QraKF726TuAH/hgO4ZUdZ5yxHEEbvqg+5OgP54kqUmK5QMKL57CzUOA0D9iyW8kdICoTobjvg6mkWv5BH7IbQjZF0kVbdi5Q9afsZrQMp/CC7anhGzphJYyjCVDI3H5weHvp5Z+jRoGvpd1yAJIyl0Lq0ByuNyWG5AGbzWS1+bbVJeLuVtGAsD0hCwR8n7dvpCvFRGz3eR7uBMxIIvxFQxrQZpromYQ4HNLTM4ELChGq26l5ZL+on0HKDpKDd2gRKVi070BHIQ6/J7/HHg== Received: from DM6PR11CA0002.namprd11.prod.outlook.com (2603:10b6:5:190::15) by DM4PR12MB8522.namprd12.prod.outlook.com (2603:10b6:8:18f::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9343.15; Sun, 23 Nov 2025 07:24:10 +0000 Received: from DS2PEPF00003445.namprd04.prod.outlook.com (2603:10b6:5:190:cafe::6c) by DM6PR11CA0002.outlook.office365.com (2603:10b6:5:190::15) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9343.16 via Frontend Transport; Sun, 23 Nov 2025 07:24:10 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by DS2PEPF00003445.mail.protection.outlook.com (10.167.17.72) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9366.7 via Frontend Transport; Sun, 23 Nov 2025 07:24:10 +0000 Received: from rnnvmail202.nvidia.com (10.129.68.7) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Sat, 22 Nov 2025 23:24:01 -0800 Received: from rnnvmail201.nvidia.com (10.129.68.8) by rnnvmail202.nvidia.com (10.129.68.7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Sat, 22 Nov 2025 23:24:00 -0800 Received: from vdi.nvidia.com (10.127.8.10) by mail.nvidia.com (10.129.68.8) with Microsoft SMTP Server id 15.2.2562.20 via Frontend Transport; Sat, 22 Nov 2025 23:23:55 -0800 From: Tariq Toukan To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Donald Hunter , Jiri Pirko , Jonathan Corbet , Saeed Mahameed , "Leon Romanovsky" , Tariq Toukan , Mark Bloch , , , , , Gal Pressman , Moshe Shemesh , Carolina Jubran , Cosmin Ratiu , Jiri Pirko Subject: [PATCH net-next V2 08/14] devlink: Allow rate node parents from other devlinks Date: Sun, 23 Nov 2025 09:22:54 +0200 Message-ID: <1763882580-1295213-9-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1763882580-1295213-1-git-send-email-tariqt@nvidia.com> References: <1763882580-1295213-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF00003445:EE_|DM4PR12MB8522:EE_ X-MS-Office365-Filtering-Correlation-Id: eaf6e33f-255e-418f-c0e1-08de2a614bb0 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|376014|7416014|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?I72igR2jUgf4Kp4QxP2L2Q5pf1zct7kLbNbIHXsUUq0N3tqOmatW4xe3fiCN?= =?us-ascii?Q?I5gWqiiPwcrzeTu+X438r+ENmLqIjWnu84DiRqIPu7qBMq1v/bc8VGv5CRBB?= =?us-ascii?Q?TMluLTvtMZU6/7MVEypwmIqTgFjWK2okHvikwOsZL+I38uT62XDePdQT6KnD?= =?us-ascii?Q?jnOT2kuVhtSO8Gxc7fm4HEx8nznXnaLmF7S1xMNEwe1vdNGlxNnb1s1D5PMu?= =?us-ascii?Q?kFarbQdTSkB/a79KEP1UjAqYwLmC+mSOQGfCpnBH9/l9Np+X8dohRAK2ZOUu?= =?us-ascii?Q?+4ibFjo1mJXuq2WECONUtGr4u+BKQela0RTuFcNXxHh8pCTBtvrxGLYj9BqU?= =?us-ascii?Q?yPfd2CX2Pc1rfK094U5rU6D19yVvGkUyX3wHMGeC/0f2M7tpnyhtpfOeD/Gj?= =?us-ascii?Q?f/2RIYd+xxk17StLsjCuGbOu6g9dTD3x0BJ0OxxKfv6alMQrPhJUVOC35Enb?= =?us-ascii?Q?Yly5kQl9IW6VRtpZfxTeyuqGOLM6nIMzDFLuz2ZIvQh9SniCfZ70qVjPZ49O?= =?us-ascii?Q?6RwnD4ZD4vAa4q7leFrEukIB3b7FKyxeCvwldlYJPo267PLfQHoJyCr9TFrS?= =?us-ascii?Q?tnjDqzEjhEGP60Kq46IbpjyCQrDCHS01tf9GwpLqNiHMOuVmQW9qqGOnjxw1?= =?us-ascii?Q?429WfnJdcD/wa4HB9v8JG3CGGLw7TYrLa1vd/wLuYcIdLPpH3svfG7wWdYi4?= =?us-ascii?Q?3Uaq+Lejm6toOv/6a2PBky8cc+/f+aQ8CUsv1728oOqdB7Csob3ADhFdija1?= =?us-ascii?Q?HnHyN5BqxUm1dtOcskc0Sw9Zb2p5n8kwKbxeFWeaJHTdIic4h3Nu5TZe3C7Z?= =?us-ascii?Q?oYf9m4z9xRdkw+HwKldMjY6jDXKu+CIY5R1ZR5SyLF/0R8rUBaB9fYmscNID?= =?us-ascii?Q?PXFlMydEDQTgxNAD5pBHU8w0DN8PW7/6fHmKEN8OWsxfr0LroQyo6Cs45HSJ?= =?us-ascii?Q?LWKV6Szx0QfaReCz4ZpHASg2mbxcbAnFpq0PDsLk8WBdKSdh2dudl4ifsMBh?= =?us-ascii?Q?cume/pFZR43A6qyIrJERnVz9LVrx2ebnq2QoYsS7GuuTVP/zioIxfICXxeh1?= =?us-ascii?Q?vUW9Eu/cK5Qupmymli+BcwXL76Qb9mjnVhF9Og8thDjxGJS9N/8zjftT5DFV?= =?us-ascii?Q?Ti3emZn0Sli9x8snU5SnfrHcYF2+EsH7L3GVK5q8d1BDQihx2hTLu4W5alIP?= =?us-ascii?Q?SMlTSkI+vhEPVlMkPIpVCsxJC/GtmOyMKoBw8yGWPU8zyw8rlcqDaKCC3geS?= =?us-ascii?Q?b9ToTX3J9hwDCFUI8uPw0kpoaCLf0he/z7WsRhJdvaDcavEfBtlC+np4f7lO?= =?us-ascii?Q?P+eZKTqNMEA4a7iBsebMU5FKBRLcK3sFCD0Jw+PzDhqWSESOBhKkGNTd6yJg?= =?us-ascii?Q?xMNF4HEQFNbtM6TZgw7qpt5r2g0S3StcPl59cUFQh5eFlZLXFim+KS4ni2Lt?= =?us-ascii?Q?iaZm+HCBUppIWkN7nQCOa/xY3TrRxBhWXHlj70FpWEDm33cLuA3Y/zAiCV3W?= =?us-ascii?Q?aJiKo7uGvwjQ9UzeZOeFYxDh6xgnn3O654id5n5dk54ey9f6ueIAW8Hjm9KW?= =?us-ascii?Q?DRhQ4pDQE0kupvxXJEU=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(376014)(7416014)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Nov 2025 07:24:10.1744 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: eaf6e33f-255e-418f-c0e1-08de2a614bb0 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF00003445.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB8522 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Cosmin Ratiu This commit makes use of the building blocks previously added to implement cross-device rate nodes. A new 'supported_cross_device_rate_nodes' bool is added to devlink_ops which lets drivers advertise support for cross-device rate objects. If enabled and if there is a common shared devlink instance, then: - all rate objects will be stored in the top-most common nested instance and - rate objects can have parents from other devices sharing the same common instance. The parent devlink from info->user_ptr[1] is not locked, so none of its mutable fields can be used. But parent setting only requires comparing devlink pointer comparisons. Additionally, since the shared devlink is locked, other rate operations cannot concurrently happen. The rate lock/unlock functions are now exported, so that drivers implementing this can protect against concurrent modifications on any shared device structures. Signed-off-by: Cosmin Ratiu Reviewed-by: Carolina Jubran Reviewed-by: Jiri Pirko Signed-off-by: Tariq Toukan --- .../networking/devlink/devlink-port.rst | 2 + include/net/devlink.h | 5 ++ net/devlink/rate.c | 90 +++++++++++++++++-- 3 files changed, 89 insertions(+), 8 deletions(-) diff --git a/Documentation/networking/devlink/devlink-port.rst b/Documentat= ion/networking/devlink/devlink-port.rst index 5e397798a402..976bc5ca0962 100644 --- a/Documentation/networking/devlink/devlink-port.rst +++ b/Documentation/networking/devlink/devlink-port.rst @@ -417,6 +417,8 @@ API allows to configure following rate object's paramet= ers: Parent node name. Parent node rate limits are considered as additional l= imits to all node children limits. ``tx_max`` is an upper limit for children. ``tx_share`` is a total bandwidth distributed among children. + If the device supports cross-function scheduling, the parent can be from= a + different function of the same underlying device. =20 ``tc_bw`` Allow users to set the bandwidth allocation per traffic class on rate diff --git a/include/net/devlink.h b/include/net/devlink.h index df481af91473..bef89179db75 100644 --- a/include/net/devlink.h +++ b/include/net/devlink.h @@ -1585,6 +1585,11 @@ struct devlink_ops { struct devlink_rate *parent, void *priv_child, void *priv_parent, struct netlink_ext_ack *extack); + /* Indicates if cross-device rate nodes are supported. + * This also requires a shared common ancestor object all devices that + * could share rate nodes are nested in. + */ + bool supported_cross_device_rate_nodes; /** * selftests_check() - queries if selftest is supported * @devlink: devlink instance diff --git a/net/devlink/rate.c b/net/devlink/rate.c index ddbd0beec4b9..f0a2a746cf23 100644 --- a/net/devlink/rate.c +++ b/net/devlink/rate.c @@ -30,20 +30,56 @@ devlink_rate_leaf_get_from_info(struct devlink *devlink= , struct genl_info *info) return devlink_rate ?: ERR_PTR(-ENODEV); } =20 +/* Repeatedly locks the nested-in devlink instances while cross device rate + * nodes are supported. Returns the devlink instance where rates should be + * stored. + */ struct devlink *devl_rate_lock(struct devlink *devlink) { - return devlink; + struct devlink *rate_devlink =3D devlink; + + while (rate_devlink->ops && + rate_devlink->ops->supported_cross_device_rate_nodes) { + devlink =3D devlink_nested_in_get_lock(rate_devlink->rel); + if (!devlink) + break; + rate_devlink =3D devlink; + } + return rate_devlink; } +EXPORT_SYMBOL_GPL(devl_rate_lock); =20 +/* Variant of the above for when the nested-in devlink instances are alrea= dy + * locked. + */ static struct devlink * devl_get_rate_node_instance_locked(struct devlink *devlink) { - return devlink; + struct devlink *rate_devlink =3D devlink; + + while (rate_devlink->ops && + rate_devlink->ops->supported_cross_device_rate_nodes) { + devlink =3D devlink_nested_in_get_locked(rate_devlink->rel); + if (!devlink) + break; + rate_devlink =3D devlink; + } + return rate_devlink; } =20 +/* Repeatedly unlocks the nested-in devlink instances of 'devlink' while c= ross + * device nodes are supported. + */ void devl_rate_unlock(struct devlink *devlink) { + if (!devlink || !devlink->ops || + !devlink->ops->supported_cross_device_rate_nodes) + return; + + devl_rate_unlock(devlink_nested_in_get_locked(devlink->rel)); + devlink_nested_in_put_unlock(devlink->rel); } +EXPORT_SYMBOL_GPL(devl_rate_unlock); =20 static struct devlink_rate * devlink_rate_node_get_by_name(struct devlink *devlink, const char *node_na= me) @@ -120,6 +156,24 @@ static int devlink_rate_put_tc_bws(struct sk_buff *msg= , u32 *tc_bw) return -EMSGSIZE; } =20 +static int devlink_nl_rate_parent_fill(struct sk_buff *msg, + struct devlink_rate *devlink_rate) +{ + struct devlink_rate *parent =3D devlink_rate->parent; + struct devlink *devlink =3D parent->devlink; + + if (nla_put_string(msg, DEVLINK_ATTR_RATE_PARENT_NODE_NAME, + parent->name)) + return -EMSGSIZE; + + if (devlink !=3D devlink_rate->devlink && + devlink_nl_put_nested_handle(msg, devlink_net(devlink), devlink, + DEVLINK_ATTR_PARENT_DEV)) + return -EMSGSIZE; + + return 0; +} + static int devlink_nl_rate_fill(struct sk_buff *msg, struct devlink_rate *devlink_rate, enum devlink_command cmd, u32 portid, u32 seq, @@ -164,10 +218,9 @@ static int devlink_nl_rate_fill(struct sk_buff *msg, devlink_rate->tx_weight)) goto nla_put_failure; =20 - if (devlink_rate->parent) - if (nla_put_string(msg, DEVLINK_ATTR_RATE_PARENT_NODE_NAME, - devlink_rate->parent->name)) - goto nla_put_failure; + if (devlink_rate->parent && + devlink_nl_rate_parent_fill(msg, devlink_rate)) + goto nla_put_failure; =20 if (devlink_rate_put_tc_bws(msg, devlink_rate->tc_bw)) goto nla_put_failure; @@ -322,13 +375,14 @@ devlink_nl_rate_parent_node_set(struct devlink_rate *= devlink_rate, struct genl_info *info, struct nlattr *nla_parent) { - struct devlink *devlink =3D devlink_rate->devlink; + struct devlink *devlink =3D devlink_rate->devlink, *parent_devlink; const char *parent_name =3D nla_data(nla_parent); const struct devlink_ops *ops =3D devlink->ops; size_t len =3D strlen(parent_name); struct devlink_rate *parent; int err =3D -EOPNOTSUPP; =20 + parent_devlink =3D info->user_ptr[1] ? : devlink; parent =3D devlink_rate->parent; =20 if (parent && !len) { @@ -346,7 +400,13 @@ devlink_nl_rate_parent_node_set(struct devlink_rate *d= evlink_rate, refcount_dec(&parent->refcnt); devlink_rate->parent =3D NULL; } else if (len) { - parent =3D devlink_rate_node_get_by_name(devlink, parent_name); + /* parent_devlink (when different than devlink) isn't locked, + * but the rate node devlink instance is, so nobody from the + * same group of devices sharing rates could change the used + * fields or unregister the parent. + */ + parent =3D devlink_rate_node_get_by_name(parent_devlink, + parent_name); if (IS_ERR(parent)) return -ENODEV; =20 @@ -646,6 +706,13 @@ int devlink_nl_rate_set_doit(struct sk_buff *skb, stru= ct genl_info *info) goto unlock; } =20 + if (info->user_ptr[1] && info->user_ptr[1] !=3D devlink && + !ops->supported_cross_device_rate_nodes) { + NL_SET_ERR_MSG(info->extack, + "Cross-device rate parents aren't supported"); + return -EOPNOTSUPP; + } + err =3D devlink_nl_rate_set(devlink_rate, ops, info); =20 if (!err) @@ -671,6 +738,13 @@ int devlink_nl_rate_new_doit(struct sk_buff *skb, stru= ct genl_info *info) if (!devlink_rate_set_ops_supported(ops, info, DEVLINK_RATE_TYPE_NODE)) return -EOPNOTSUPP; =20 + if (info->user_ptr[1] && info->user_ptr[1] !=3D devlink && + !ops->supported_cross_device_rate_nodes) { + NL_SET_ERR_MSG(info->extack, + "Cross-device rate parents aren't supported"); + return -EOPNOTSUPP; + } + rate_devlink =3D devl_rate_lock(devlink); rate_node =3D devlink_rate_node_get_from_attrs(devlink, info->attrs); if (!IS_ERR(rate_node)) { --=20 2.31.1 From nobody Tue Dec 2 00:46:21 2025 Received: from BL0PR03CU003.outbound.protection.outlook.com (mail-eastusazon11012049.outbound.protection.outlook.com [52.101.53.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 65F5629A30A; Sun, 23 Nov 2025 07:24:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.53.49 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763882670; cv=fail; b=fL4U2boPs85ziNes9vLb4yxQIgkE+/JsaYEcTi9t5SFmr2UMS+jy64aFrfixS/QKdWhva+KhbQ8V9lpE+rc1RUeIh1tCy3mMC2poGzVMhZj0ZEZDHPTZCmlm4sIfxBhFZiEkVlLqRIDVJzmNDYp0f5LjWvEM1SDIzKUHYZrcE3E= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763882670; c=relaxed/simple; bh=6IcInnTRJCj0yAcET5rTQb1VR06ZxyPT/b1zQWPLppI=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=ansuD/kKPTxPVZusVRuOcMGt+72y84vA1T5qUhRe1LUKNgI/igtEXqU938SvZDgKRNCLc1P2k6yYWbmu+5XynWPythPCiUGfIHOZ8/qT9VZNxigKVq743YwM2rfD+ZPTkXLA3G9bydDUid3cBDEO1oIqzImBBnqDr/itLr9XAqg= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=m4cDZVGb; arc=fail smtp.client-ip=52.101.53.49 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="m4cDZVGb" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=IzqGLlV7Hgg78/4pJJmXEHz40B5yXly4VvujciqBiORy0EOeu+OOv3POdSqrv/PzkBccrSa8hSJHMInk6Cr4zgpL/y7yOIGgseo9fouVQsC6yoxzsq0ZJ48jUkHbEuBDrU0MhOFg/1VujccMCUcjiOwu9BGYWBRcV4j0+j8cUqaVjfQ2l8kf89h1c4ARStoj7jynUO6OmWylqgI0bvGb5CXH1nxnBxX3Bv1REXR3WN5QvT4EorvOdlp3s11LAYCu7h8HO69CBZy85hp3kGfqW87/ZKRXP6/HX/ADZPrgsJpVk9IAxnexUv+Eo9yZM9myhRigfCfz1cLIgYKFBvZcbA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=8kXsQQq/EzcLLFh1j35ysWyoWYfVT7TeApCinTU/kNc=; b=mQaTgMVn3r43AsDtwVQxUMoIl/PLutSZ06iIvW1AOpMGoxHzmzo/IxcCPuCGCMvs5KOYhGoY6UbwZW4YCnVYQdov38ITWPe2fDAI7tm/KOdfQ0Ntgna3HC3ferZRmBm9Njfqk1JSu64VSgs3IuN3izBTOO90bcY7B0Nw1ZqZEbIgnGMFUcNokFfFKZ0p/LReQHO8P8MKitEhdq9hwztfTQlGMukureM/UYEqhigBo17eSacKsHKhSpbuoyXW5M/SvFVZO6dBqakPH3gEEwUiQ+wIVED+1zDB6foR2FskvXRcLlxQc3xKJlnOahMzIL1JZfBjXcdh/Eu8vNuBCh1dTA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=google.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=8kXsQQq/EzcLLFh1j35ysWyoWYfVT7TeApCinTU/kNc=; b=m4cDZVGb3R+0ZgPl8s5n/LyBwo5lR+E7DYhX1ndHcOJZj0g4jRSf68Hh8tPucfV2r8TkfTu+roWHPChaQockFAm7kLADumskI25KJ7DN5hqN7gHD5okkm5RXWZQUuPq6QIkvXDjHwCJqpDOO5orJb4IpOFDPPyfHW6zN7trINNpJ+vlnmgr2sHUZbTx4Q4s815doTQny7JOxPFWdDw7IogKdInEsbJAAkSGUb1JFc5hFxfLiA/00BqFKFnUS1NqDoKQDJXNBVzlwfuPli9qoJD4YGpIiVkJW0iPQ/PT08GtDb7icvD3QQAIzWvf8QyCIbibeCtRwxNjLBY560wV85w== Received: from SA0PR11CA0068.namprd11.prod.outlook.com (2603:10b6:806:d2::13) by CY5PR12MB6621.namprd12.prod.outlook.com (2603:10b6:930:43::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9343.10; Sun, 23 Nov 2025 07:24:22 +0000 Received: from SN1PEPF000397AE.namprd05.prod.outlook.com (2603:10b6:806:d2:cafe::64) by SA0PR11CA0068.outlook.office365.com (2603:10b6:806:d2::13) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9343.16 via Frontend Transport; Sun, 23 Nov 2025 07:24:15 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by SN1PEPF000397AE.mail.protection.outlook.com (10.167.248.52) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9366.7 via Frontend Transport; Sun, 23 Nov 2025 07:24:22 +0000 Received: from rnnvmail202.nvidia.com (10.129.68.7) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Sat, 22 Nov 2025 23:24:07 -0800 Received: from rnnvmail201.nvidia.com (10.129.68.8) by rnnvmail202.nvidia.com (10.129.68.7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Sat, 22 Nov 2025 23:24:07 -0800 Received: from vdi.nvidia.com (10.127.8.10) by mail.nvidia.com (10.129.68.8) with Microsoft SMTP Server id 15.2.2562.20 via Frontend Transport; Sat, 22 Nov 2025 23:24:01 -0800 From: Tariq Toukan To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Donald Hunter , Jiri Pirko , Jonathan Corbet , Saeed Mahameed , "Leon Romanovsky" , Tariq Toukan , Mark Bloch , , , , , Gal Pressman , Moshe Shemesh , Carolina Jubran , Cosmin Ratiu , Jiri Pirko Subject: [PATCH net-next V2 09/14] net/mlx5: Introduce shared devlink instance for PFs on same chip Date: Sun, 23 Nov 2025 09:22:55 +0200 Message-ID: <1763882580-1295213-10-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1763882580-1295213-1-git-send-email-tariqt@nvidia.com> References: <1763882580-1295213-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000397AE:EE_|CY5PR12MB6621:EE_ X-MS-Office365-Filtering-Correlation-Id: 63b42825-0d2d-4144-8cad-08de2a615319 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|30052699003|1800799024|7416014|376014|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?XtHgbUTDpx5GF3972GKK6NVnoz1Zv0sA9Fc6U905P5Y4Xj1chbnhqbkXGgiQ?= =?us-ascii?Q?mBwkwtG1LTuhw6YCfLV8ugPJHLeeCkL9e26SZPPyL7eQbBe0/Qa5xxKJZy4g?= =?us-ascii?Q?4kqwbCnVJx0AkZj0ZfUAEUD+Y3ruLRujaNTuIiY3H8HlgebdXexIXO+h+RnG?= =?us-ascii?Q?p0kQSA8chAc0SjmcGhtz5Ta65c1snPV/M2vcasu2S/wxiBJu6E392oF4XyrW?= =?us-ascii?Q?BvQYjBplXCS8+6tbhim65kHJRUWr7ZEWgu559gkvgffm4neGheudOxvtp7vF?= =?us-ascii?Q?CpnnokofBRccgDNZ7Zc1/Z4LXiuUvQc9jJYVv548UcrJ+ZTmJ4acghdAS323?= =?us-ascii?Q?0A8pllFieWT+a10/0dcdcuJubNvj6qFzAUyvkNxs3f24+Gsfr/cbtt8LswZG?= =?us-ascii?Q?pHYuOiICqIlhM9P4MEzoO6hwbtEb5cIQkPOvDdr082lo0nwSv4w7oDSOKFsw?= =?us-ascii?Q?psDiQ3/fwTF/SE86gAyRVRgoczq6SRWlfFidD5gZWYKyR5zZaucjMIJSMa8A?= =?us-ascii?Q?C4AFriHCQ5eqRChSCmdImKa4QrohDe3Dx6sToAkGWWbmHzDiCCcyi70LL1hj?= =?us-ascii?Q?AQFA5TZ+NE3ziZzNZeiKphIzXlUezE2yv+Au/3FHcGSGdzQgXu7f0UziuEEn?= =?us-ascii?Q?IrROs8bobD0+6Nlkb373zvvII/zYaBU67P3xopWCMCGQYr3FQZxU/hU8f4aR?= =?us-ascii?Q?/qE3PSDWMEIo32OBnf+BztV1EdNeBBoaqIPmd6n+1QlQ4YJWpi7cm8waGUzy?= =?us-ascii?Q?VctRbvntNCmBZd3DYmr5NDrlp8uUzn8xanXum1gN9A1d9FFIZpALXYwwLri+?= =?us-ascii?Q?FdvONMf5P8nf/8PN98mFVW5HP3BlGDP0fyQNPAs1cLkHX8q7t6qAciGcAbYD?= =?us-ascii?Q?qmi8/lMphQRN3q5l8kO9ZJehH9V5YEUwDojmhg7/42l3F5/8GDFfKcuSYE2d?= =?us-ascii?Q?uTEB0M3IOJUAhvDv/BNB6qU0x5hVMR0SYvAU7sYahCNB+vEv2d5arFERzvkW?= =?us-ascii?Q?1UgBbLgooHrDhBzV9q3nuyTr0vDz1NFcmnr3rsEg5B9fv+ehFhyFNBzw0/wz?= =?us-ascii?Q?LXScxb0HrVmOYw3gw3gCTLCVhn9eRpIODgtc4rokCu/TSH/5YRxDX8PvGdT5?= =?us-ascii?Q?G5jq54Y2JaoUr5mbYgZligxnv/yDlrmoP6b4DTwIrSIoDUQ88slESCsg35lK?= =?us-ascii?Q?yG/1v7oBdA1JdScMbAQ6Iuhwy0JdTATQWeshrid8R0IAeK/CPs8rQJpWJklY?= =?us-ascii?Q?tN1jNNR5hDieV6UfHK6dewylMTcRShVF4a0+h/hqxcaPtDY6oeqU2dScVge5?= =?us-ascii?Q?CpxqtSVgQY8W2wdHOO62GUgnv0mppIwojWjM2T4pkghyhRGCPA9N2ysJoVLV?= =?us-ascii?Q?c9U0aSdhfBbnAphYzYM1S8q83/JZM072D//COViZnZWMe5Ztz1zuXgS38kwJ?= =?us-ascii?Q?eRbw3pzsO7AlEhT3JZvccJWqtA07n1SlLk/M6CQpDqTNXncv/GxinbQv6tfU?= =?us-ascii?Q?bPWWAwnZHfM/au8GJc8SzG9B51thQtZxMN92cNmxdipxYjFKt+OR1vkQ8fp5?= =?us-ascii?Q?GWLCDlz08HnwJWEC7uI=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(30052699003)(1800799024)(7416014)(376014)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Nov 2025 07:24:22.6134 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 63b42825-0d2d-4144-8cad-08de2a615319 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000397AE.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6621 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Jiri Pirko Multiple PFs may reside on the same physical chip, running a single firmware. Some of the resources and configurations may be shared among these PFs. Currently, there is not good object to pin the configuration knobs on. Introduce a shared devlink, instantiated upon probe of the first PF, removed during remove of the last PF. Back this shared devlink instance by faux device, as there is no PCI device related to it. Make the PF devlink instances nested in this shared devlink instance. Example: $ devlink dev pci/0000:08:00.0: nested_devlink: auxiliary/mlx5_core.eth.0 faux/mlx5_core_83013c12b77faa1a30000c82a1045c91: nested_devlink: pci/0000:08:00.0 pci/0000:08:00.1 auxiliary/mlx5_core.eth.0 pci/0000:08:00.1: nested_devlink: auxiliary/mlx5_core.eth.1 auxiliary/mlx5_core.eth.1 Signed-off-by: Jiri Pirko Reviewed-by: Cosmin Ratiu Signed-off-by: Tariq Toukan --- .../net/ethernet/mellanox/mlx5/core/Makefile | 5 +- .../net/ethernet/mellanox/mlx5/core/main.c | 18 ++ .../ethernet/mellanox/mlx5/core/sh_devlink.c | 166 ++++++++++++++++++ .../ethernet/mellanox/mlx5/core/sh_devlink.h | 13 ++ include/linux/mlx5/driver.h | 5 + 5 files changed, 205 insertions(+), 2 deletions(-) create mode 100644 drivers/net/ethernet/mellanox/mlx5/core/sh_devlink.c create mode 100644 drivers/net/ethernet/mellanox/mlx5/core/sh_devlink.h diff --git a/drivers/net/ethernet/mellanox/mlx5/core/Makefile b/drivers/net= /ethernet/mellanox/mlx5/core/Makefile index 8ffa286a18f5..d39fe9c4a87c 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/Makefile +++ b/drivers/net/ethernet/mellanox/mlx5/core/Makefile @@ -16,8 +16,9 @@ mlx5_core-y :=3D main.o cmd.o debugfs.o fw.o eq.o uar.o p= agealloc.o \ transobj.o vport.o sriov.o fs_cmd.o fs_core.o pci_irq.o \ fs_counters.o fs_ft_pool.o rl.o lag/debugfs.o lag/lag.o dev.o events.o w= q.o lib/gid.o \ lib/devcom.o lib/pci_vsc.o lib/dm.o lib/fs_ttc.o diag/fs_tracepoint.o \ - diag/fw_tracer.o diag/crdump.o devlink.o diag/rsc_dump.o diag/reporter_v= nic.o \ - fw_reset.o qos.o lib/tout.o lib/aso.o wc.o fs_pool.o lib/nv_param.o + diag/fw_tracer.o diag/crdump.o devlink.o sh_devlink.o diag/rsc_dump.o \ + diag/reporter_vnic.o fw_reset.o qos.o lib/tout.o lib/aso.o wc.o fs_pool.= o \ + lib/nv_param.o =20 # # Netdev basic diff --git a/drivers/net/ethernet/mellanox/mlx5/core/main.c b/drivers/net/e= thernet/mellanox/mlx5/core/main.c index 024339ce41f1..a8a285917688 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/main.c @@ -74,6 +74,7 @@ #include "mlx5_irq.h" #include "hwmon.h" #include "lag/lag.h" +#include "sh_devlink.h" =20 MODULE_AUTHOR("Eli Cohen "); MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX ser= ies) core driver"); @@ -1520,10 +1521,17 @@ int mlx5_init_one(struct mlx5_core_dev *dev) int err; =20 devl_lock(devlink); + if (dev->shd) { + err =3D devl_nested_devlink_set(priv_to_devlink(dev->shd), + devlink); + if (err) + goto unlock; + } devl_register(devlink); err =3D mlx5_init_one_devl_locked(dev); if (err) devl_unregister(devlink); +unlock: devl_unlock(devlink); return err; } @@ -2015,6 +2023,13 @@ static int probe_one(struct pci_dev *pdev, const str= uct pci_device_id *id) goto pci_init_err; } =20 + err =3D mlx5_shd_init(dev); + if (err) { + mlx5_core_err(dev, "mlx5_shd_init failed with error code %d\n", + err); + goto shd_init_err; + } + err =3D mlx5_init_one(dev); if (err) { mlx5_core_err(dev, "mlx5_init_one failed with error code %d\n", @@ -2026,6 +2041,8 @@ static int probe_one(struct pci_dev *pdev, const stru= ct pci_device_id *id) return 0; =20 err_init_one: + mlx5_shd_uninit(dev); +shd_init_err: mlx5_pci_close(dev); pci_init_err: mlx5_mdev_uninit(dev); @@ -2047,6 +2064,7 @@ static void remove_one(struct pci_dev *pdev) mlx5_drain_health_wq(dev); mlx5_sriov_disable(pdev, false); mlx5_uninit_one(dev); + mlx5_shd_uninit(dev); mlx5_pci_close(dev); mlx5_mdev_uninit(dev); mlx5_adev_idx_free(dev->priv.adev_idx); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/sh_devlink.c b/drivers= /net/ethernet/mellanox/mlx5/core/sh_devlink.c new file mode 100644 index 000000000000..e39a5e20e102 --- /dev/null +++ b/drivers/net/ethernet/mellanox/mlx5/core/sh_devlink.c @@ -0,0 +1,166 @@ +// SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB +/* Copyright (c) 2025, NVIDIA CORPORATION & AFFILIATES. All rights reserve= d. */ + +#include +#include +#include + +#include "sh_devlink.h" + +static LIST_HEAD(shd_list); +static DEFINE_MUTEX(shd_mutex); /* Protects shd_list and shd->list */ + +/* This structure represents a shared devlink instance, + * there is one created for PF group of the same chip. + */ +struct mlx5_shd { + /* Node in shd list */ + struct list_head list; + /* Serial number of the chip */ + const char *sn; + /* List of per-PF dev instances */ + struct list_head dev_list; + /* Related faux device */ + struct faux_device *faux_dev; +}; + +static const struct devlink_ops mlx5_shd_ops =3D { +}; + +static int mlx5_shd_faux_probe(struct faux_device *faux_dev) +{ + struct devlink *devlink; + struct mlx5_shd *shd; + + devlink =3D devlink_alloc(&mlx5_shd_ops, sizeof(struct mlx5_shd), + &faux_dev->dev); + if (!devlink) + return -ENOMEM; + shd =3D devlink_priv(devlink); + faux_device_set_drvdata(faux_dev, shd); + + devl_lock(devlink); + devl_register(devlink); + devl_unlock(devlink); + return 0; +} + +static void mlx5_shd_faux_remove(struct faux_device *faux_dev) +{ + struct mlx5_shd *shd =3D faux_device_get_drvdata(faux_dev); + struct devlink *devlink =3D priv_to_devlink(shd); + + devl_lock(devlink); + devl_unregister(devlink); + devl_unlock(devlink); + devlink_free(devlink); +} + +static const struct faux_device_ops mlx5_shd_faux_ops =3D { + .probe =3D mlx5_shd_faux_probe, + .remove =3D mlx5_shd_faux_remove, +}; + +static struct mlx5_shd *mlx5_shd_create(const char *sn) +{ + struct faux_device *faux_dev; + struct mlx5_shd *shd; + + faux_dev =3D faux_device_create(sn, NULL, &mlx5_shd_faux_ops); + if (!faux_dev) + return NULL; + shd =3D faux_device_get_drvdata(faux_dev); + if (!shd) + return NULL; + list_add_tail(&shd->list, &shd_list); + shd->sn =3D sn; + INIT_LIST_HEAD(&shd->dev_list); + shd->faux_dev =3D faux_dev; + return shd; +} + +static void mlx5_shd_destroy(struct mlx5_shd *shd) +{ + list_del(&shd->list); + kfree(shd->sn); + faux_device_destroy(shd->faux_dev); +} + +int mlx5_shd_init(struct mlx5_core_dev *dev) +{ + u8 *vpd_data __free(kfree) =3D NULL; + struct pci_dev *pdev =3D dev->pdev; + unsigned int vpd_size, kw_len; + struct mlx5_shd *shd; + const char *sn; + char *end; + int start; + int err; + + if (!mlx5_core_is_pf(dev)) + return 0; + + vpd_data =3D pci_vpd_alloc(pdev, &vpd_size); + if (IS_ERR(vpd_data)) { + err =3D PTR_ERR(vpd_data); + return err =3D=3D -ENODEV ? 0 : err; + } + start =3D pci_vpd_find_ro_info_keyword(vpd_data, vpd_size, "V3", &kw_len); + if (start < 0) { + /* Fall-back to SN for older devices. */ + start =3D pci_vpd_find_ro_info_keyword(vpd_data, vpd_size, + PCI_VPD_RO_KEYWORD_SERIALNO, &kw_len); + if (start < 0) + return -ENOENT; + } + sn =3D kstrndup(vpd_data + start, kw_len, GFP_KERNEL); + if (!sn) + return -ENOMEM; + /* Firmware may return spaces at the end of the string, strip it. */ + end =3D strchrnul(sn, ' '); + *end =3D '\0'; + + guard(mutex)(&shd_mutex); + list_for_each_entry(shd, &shd_list, list) { + if (!strcmp(shd->sn, sn)) { + kfree(sn); + goto found; + } + } + shd =3D mlx5_shd_create(sn); + if (!shd) { + kfree(sn); + return -ENOMEM; + } +found: + list_add_tail(&dev->shd_list, &shd->dev_list); + dev->shd =3D shd; + return 0; +} + +void mlx5_shd_uninit(struct mlx5_core_dev *dev) +{ + struct mlx5_shd *shd =3D dev->shd; + + if (!dev->shd) + return; + + guard(mutex)(&shd_mutex); + list_del(&dev->shd_list); + if (list_empty(&shd->dev_list)) + mlx5_shd_destroy(shd); +} + +void mlx5_shd_lock(struct mlx5_core_dev *dev) +{ + if (!dev->shd) + return; + devl_lock(priv_to_devlink(dev->shd)); +} + +void mlx5_shd_unlock(struct mlx5_core_dev *dev) +{ + if (!dev->shd) + return; + devl_unlock(priv_to_devlink(dev->shd)); +} diff --git a/drivers/net/ethernet/mellanox/mlx5/core/sh_devlink.h b/drivers= /net/ethernet/mellanox/mlx5/core/sh_devlink.h new file mode 100644 index 000000000000..54ce0389cfea --- /dev/null +++ b/drivers/net/ethernet/mellanox/mlx5/core/sh_devlink.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */ +/* Copyright (c) 2025, NVIDIA CORPORATION & AFFILIATES. All rights reserve= d. */ + +#ifndef __MLX5_SH_DEVLINK_H__ +#define __MLX5_SH_DEVLINK_H__ + +int mlx5_shd_init(struct mlx5_core_dev *dev); +void mlx5_shd_uninit(struct mlx5_core_dev *dev); +void mlx5_shd_lock(struct mlx5_core_dev *dev); +void mlx5_shd_unlock(struct mlx5_core_dev *dev); +void mlx5_shd_nested_set(struct mlx5_core_dev *dev); + +#endif /* __MLX5_SH_DEVLINK_H__ */ diff --git a/include/linux/mlx5/driver.h b/include/linux/mlx5/driver.h index 1c54aa6f74fb..29fd4dff1cd1 100644 --- a/include/linux/mlx5/driver.h +++ b/include/linux/mlx5/driver.h @@ -735,6 +735,8 @@ enum mlx5_wc_state { MLX5_WC_STATE_SUPPORTED, }; =20 +struct mlx5_shd; + struct mlx5_core_dev { struct device *device; enum mlx5_coredev_type coredev_type; @@ -798,6 +800,9 @@ struct mlx5_core_dev { enum mlx5_wc_state wc_state; /* sync write combining state */ struct mutex wc_state_lock; + /* node in shared devlink list */ + struct list_head shd_list; + struct mlx5_shd *shd; }; =20 struct mlx5_db { --=20 2.31.1 From nobody Tue Dec 2 00:46:21 2025 Received: from PH8PR06CU001.outbound.protection.outlook.com (mail-westus3azon11012063.outbound.protection.outlook.com [40.107.209.63]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6F022298CCF; Sun, 23 Nov 2025 07:24:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.209.63 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763882671; cv=fail; b=hQJuupy+1dkq4vnm7ZQ2vP2+wrj7ndmAs158fY3mYRC39OrJQYtHRVfFU8M2IkvpA7oHIbpxKIzbQhYIfAHB1/Nc/pNkh0zSJeRY00WfHkW9Ug/TVgI2VIPXMo4fySHP8R3+XxFMG89fmbU+vDbXEoQPNDoIMg+u6PwU7jCgUZc= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763882671; c=relaxed/simple; bh=WXI4mPHSLY+tAy1zXP51/Q7vhoBiJyspgV9I95XoDtI=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=HWPB8XNdbgpryRcKo6RkiOtpe8zqESiQa3bWP9Sz0pCIz3M8Mn76MLmFK0h1HGvB3tCVwlV2wiofJJCdzKlKNjMhDmTccDB0+nOA7zwMXlXRBJ0IShMrG1rYqCFjeHWC6Um6yP2M9eXhe1FK96GQpGOIlmOd0nFr0Xl5KiSpIzs= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=j5r9L52E; arc=fail smtp.client-ip=40.107.209.63 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="j5r9L52E" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=Sk7eaBmCOzbSdYEhDTQq7ofzb0zdhsrYqDgjKHjbjIggCBU7EMTUO+kizsNlKVAEJuM0bnMXgaVmDvXBSmAKWF4nKQVc3steluUnI5+n85sXY9PSmM52YoM8itb6z9rWNL3V7NKy43Jw9veN8Bst/Rp6mqNk1Ffx1i5oqIqS3/QW5+9LyQtclqPdYUZWxRnhsWEODcgCGusFhI2HOq2SObz2bVDR1U8O04zaa2YEO+YMyjH5RBaeNmjbqSv9ipcvGd/czDPaEErdu7oOJwyiJkucEcUnbHRjBHl2XuZsyK0F+rF6pRGWK+13a2QlI8L0uZkLdEs5dOBhBYC3J0BP+g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=JzoiUfphuvJ+T4Osz72JuZLn5FICLxZtgg522pJbcV8=; b=dJomSGuRNd+4XZ9IkQgwJ1TJyk2t/3HL7KrOGV+Pf+3P1LOrQodYgxtyNG8Z1xXTzTCvAZnaRKj9A/JolOTLdpbr2p4s83ettLrlReNgRepONoKVOeUAQlOSunEFxLfjwpaflKwvqAxfQnekjAl8wW9BUvr8e+gbJCC92D3om3I+MamFRwUgFudi9RgQYhakTIIfUWE6OpaHUcxICIy8Zn3F2blZrR+aH6YvtlaHUs5yb5C/wNBMkQSoFSEZqPcJoexwWtEz2UEZf9jDp7BUefJCPqf4n3ZF7iEYbWTgv9X/DQ7Ga7IZhjVicM/MWlUPsueGFflQ5ZNSiUUBWcdMhg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=google.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=JzoiUfphuvJ+T4Osz72JuZLn5FICLxZtgg522pJbcV8=; b=j5r9L52ELYoys7uVOgxnuqIkRrStRMVgADwDwsYQIm3Xkms2OHAuKHovMhpz11FLpnPJI9pRnKNagqSXcfcPhJ3m3q/kYJmtefqxB0FJK4AreptpugnvEBSGhUGrPtxaFyAnhnQzJ+3vjb23XAVpS4WicqkuXcsofA2w419ayoOqYKQbbZZvyWAiOFpqpbOjSsaOQcWUgZIcrp0A92n7bQA8Canh2d2hdZDCvXqQ4upI1euNrXjNRdaaVWoZfFcJckMB9yKea/W+LCM5irY+LqgHZzJ24NPUPtOGHArmTiyUVW9RblLQ6rEm+xqgqNybQhRjyQEtFHe28EimZoJDwQ== Received: from DM6PR17CA0023.namprd17.prod.outlook.com (2603:10b6:5:1b3::36) by PH8PR12MB6770.namprd12.prod.outlook.com (2603:10b6:510:1c5::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9343.14; Sun, 23 Nov 2025 07:24:24 +0000 Received: from DS2PEPF00003446.namprd04.prod.outlook.com (2603:10b6:5:1b3:cafe::2) by DM6PR17CA0023.outlook.office365.com (2603:10b6:5:1b3::36) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9343.15 via Frontend Transport; Sun, 23 Nov 2025 07:24:22 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by DS2PEPF00003446.mail.protection.outlook.com (10.167.17.73) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9366.7 via Frontend Transport; Sun, 23 Nov 2025 07:24:24 +0000 Received: from rnnvmail202.nvidia.com (10.129.68.7) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Sat, 22 Nov 2025 23:24:14 -0800 Received: from rnnvmail201.nvidia.com (10.129.68.8) by rnnvmail202.nvidia.com (10.129.68.7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Sat, 22 Nov 2025 23:24:13 -0800 Received: from vdi.nvidia.com (10.127.8.10) by mail.nvidia.com (10.129.68.8) with Microsoft SMTP Server id 15.2.2562.20 via Frontend Transport; Sat, 22 Nov 2025 23:24:07 -0800 From: Tariq Toukan To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Donald Hunter , Jiri Pirko , Jonathan Corbet , Saeed Mahameed , "Leon Romanovsky" , Tariq Toukan , Mark Bloch , , , , , Gal Pressman , Moshe Shemesh , Carolina Jubran , Cosmin Ratiu , Jiri Pirko Subject: [PATCH net-next V2 10/14] net/mlx5: Expose a function to clear a vport's parent Date: Sun, 23 Nov 2025 09:22:56 +0200 Message-ID: <1763882580-1295213-11-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1763882580-1295213-1-git-send-email-tariqt@nvidia.com> References: <1763882580-1295213-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF00003446:EE_|PH8PR12MB6770:EE_ X-MS-Office365-Filtering-Correlation-Id: e3add27b-7298-45f0-c6dd-08de2a61541f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|82310400026|1800799024|7416014|376014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?XPiVybYHHBuEOERgR+E+9YJdYfDEQMBesz417RuJS4OWisbG1uyVfGAzl4tE?= =?us-ascii?Q?wG45AktyUlJfvOrg6tOSUPrhNYADrKsfCG6OmKAX+dyv3CGue5bwjMnDTfJw?= =?us-ascii?Q?r07+sPY5FCJdfms2P1Ffv5W6TsbcO9oW9p9MV3FCcHKKXxVaQhBDtzTSRtZL?= =?us-ascii?Q?OzDJ/bGlEuNcQHk/4vszuEkdetPar6ga/Bh/aK8euPeQyn812FHVqF6fhZ0Z?= =?us-ascii?Q?kKN/H3Cz2ihyZeWQ6BWyHIeu9cACVBJ1XqLWpunbCCsgi/V8xw86lMNKEq5w?= =?us-ascii?Q?eGk+Nk698X27uKACesYD3PHJiCBb0bQs8CQfX6mP9c3YD/N+Rr+n/py5wjXb?= =?us-ascii?Q?aJstqYN7eanwGe3AjHK9rLA7ic0DauS7Ks3McbX7ocsuZ/3WaCY6iLWUf/tN?= =?us-ascii?Q?0vzGu3StweLv8RGHOc2qrhqPJjTpFmDURW/Ipbm3dXk78fQjyH8S6OX52AYG?= =?us-ascii?Q?ncLNR+0iHjCzWJ+gWU+LetZcHA4hToeFbFjKwLi6EGkkaOvMLobDa6Nm35p0?= =?us-ascii?Q?P+YZ0Tr1lJUfGvP+PzzUWrLogkTrKgHCAdNcZnK1EE+DXTIO3LyGdeb1nNL2?= =?us-ascii?Q?1qIQSDfmKlubypmHINhkQKgGWhd12g8eDUkqgQXMfmyrs5sbQsANmCjX1ccK?= =?us-ascii?Q?QvwA29yDE4vD1mhGLxvHp4d1X9A/qOu3EaY0JXcOjIFnCqdem8wpcAmSCMvm?= =?us-ascii?Q?YG5aZFbsrJB4KW2fLl7GEyNe6YI+wGJPCgYfLl3hKkYiufpsn1lE/tx5A32U?= =?us-ascii?Q?zPOmEUkGkQVDmS4Ny4vhK8LO2tgStSurWMIKDILQOZt+jYzSVsVW6V1egBuo?= =?us-ascii?Q?0Ic+wOgDyscBYrPKTqkNQV3L1oX/tthdszjR/BlRYrbflXfYgGNLQwdjPLSH?= =?us-ascii?Q?2st2mZV8gSh8lFygpGs9zB3IVfGnWasqNtlhI77tPMpvKawxZ3XVOp92oQDy?= =?us-ascii?Q?gg9MMEeRC5R9c32GXEcpuQNKFG/I40/FKBTbOkArlS029ocpRZgPxdV6oUmg?= =?us-ascii?Q?PTlCm/4o+HXug9EEdnYqzewkwlGJv90rzbEjcvcF4oGhWXiu1a+wuqoBcN+D?= =?us-ascii?Q?1oP4tcO0CSLrYQZ9Z8YpI5+04cXeaVj9ESv3bAFnlCZwsZ9Ts1EMKK18sTuC?= =?us-ascii?Q?M5g73e2xcH19FvW3aHae/Z15i7KC34OeKb5c6+SFaJd2OJNvfOPoxxU6CpRW?= =?us-ascii?Q?2gEaAkzNt6yuXSz8r7U5sM1xp68EwdvgyJkIo/Q5pcG0XoaLlIhig5dJD2xy?= =?us-ascii?Q?5OZJtjAXuY90yPsEvF0yjWJ2qhr0PZfBSwO50m3nEX/jLSngKYpshSUXnyUk?= =?us-ascii?Q?aOEFknxBMM51UiOKUMNS1z3vrvuTNm9wdKw0iuAbWFYYfE2VA+6SlQefwCfN?= =?us-ascii?Q?yM097YDi5m8Irwa7BFwIAHd69gt92Fr3kwrh/6WIU71c2jGeZVu4GpNXOz8B?= =?us-ascii?Q?L1OAcTVCxXKCEb0UaSdWY4k5kDBpTs4V8qppvefLeY07EKdMGo2Kty7YeCe7?= =?us-ascii?Q?lWLCxQMBQ231lWrC4bS0YKg/FYiZ3XjQrzdVsedCjHyiNEPQrJoarIiLs2Vy?= =?us-ascii?Q?v4vM1SCBp9QLz/kN1s4=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(82310400026)(1800799024)(7416014)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Nov 2025 07:24:24.3452 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e3add27b-7298-45f0-c6dd-08de2a61541f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF00003446.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB6770 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Cosmin Ratiu Currently, clearing a vport's parent happens with a call that looks like this: mlx5_esw_qos_vport_update_parent(vport, NULL, NULL); Change that to something nicer that looks like this: mlx5_esw_qos_vport_clear_parent(vport); Signed-off-by: Cosmin Ratiu Reviewed-by: Carolina Jubran Signed-off-by: Tariq Toukan --- .../ethernet/mellanox/mlx5/core/esw/devlink_port.c | 2 +- drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c | 11 +++++++++-- drivers/net/ethernet/mellanox/mlx5/core/eswitch.h | 3 +-- 3 files changed, 11 insertions(+), 5 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/esw/devlink_port.c b/d= rivers/net/ethernet/mellanox/mlx5/core/esw/devlink_port.c index 89a58dee50b3..31704ea9cdb4 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/esw/devlink_port.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/esw/devlink_port.c @@ -202,7 +202,7 @@ void mlx5_esw_offloads_devlink_port_unregister(struct m= lx5_vport *vport) return; dl_port =3D vport->dl_port; =20 - mlx5_esw_qos_vport_update_parent(vport, NULL, NULL); + mlx5_esw_qos_vport_clear_parent(vport); devl_rate_leaf_destroy(&dl_port->dl_port); =20 devl_port_unregister(&dl_port->dl_port); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/esw/qos.c index 4278bcb04c72..8c3a026b8db4 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c @@ -1896,8 +1896,10 @@ int mlx5_esw_devlink_rate_node_del(struct devlink_ra= te *rate_node, void *priv, return 0; } =20 -int mlx5_esw_qos_vport_update_parent(struct mlx5_vport *vport, struct mlx5= _esw_sched_node *parent, - struct netlink_ext_ack *extack) +static int +mlx5_esw_qos_vport_update_parent(struct mlx5_vport *vport, + struct mlx5_esw_sched_node *parent, + struct netlink_ext_ack *extack) { struct mlx5_eswitch *esw =3D vport->dev->priv.eswitch; int err =3D 0; @@ -1922,6 +1924,11 @@ int mlx5_esw_qos_vport_update_parent(struct mlx5_vpo= rt *vport, struct mlx5_esw_s return err; } =20 +void mlx5_esw_qos_vport_clear_parent(struct mlx5_vport *vport) +{ + mlx5_esw_qos_vport_update_parent(vport, NULL, NULL); +} + int mlx5_esw_devlink_rate_leaf_parent_set(struct devlink_rate *devlink_rat= e, struct devlink_rate *parent, void *priv, void *parent_priv, diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h b/drivers/ne= t/ethernet/mellanox/mlx5/core/eswitch.h index ad1073f7b79f..20cf9dd542a1 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h @@ -452,8 +452,7 @@ int mlx5_eswitch_set_vport_trust(struct mlx5_eswitch *e= sw, u16 vport_num, bool setting); int mlx5_eswitch_set_vport_rate(struct mlx5_eswitch *esw, u16 vport, u32 max_rate, u32 min_rate); -int mlx5_esw_qos_vport_update_parent(struct mlx5_vport *vport, struct mlx5= _esw_sched_node *node, - struct netlink_ext_ack *extack); +void mlx5_esw_qos_vport_clear_parent(struct mlx5_vport *vport); int mlx5_eswitch_set_vepa(struct mlx5_eswitch *esw, u8 setting); int mlx5_eswitch_get_vepa(struct mlx5_eswitch *esw, u8 *setting); int mlx5_eswitch_get_vport_config(struct mlx5_eswitch *esw, --=20 2.31.1 From nobody Tue Dec 2 00:46:21 2025 Received: from SN4PR0501CU005.outbound.protection.outlook.com (mail-southcentralusazon11011000.outbound.protection.outlook.com [40.93.194.0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 93704268C42; Sun, 23 Nov 2025 07:24:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.93.194.0 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763882681; cv=fail; b=el50xRwe5+grZVEiBjE9VURiYWsk1EfS4wNGuc+Aj+FnOK2lM/ARlK1ScpM65X75mWL5vvQOY6sUbfT7H5w8kWqAebfY2zr8Ew5yErB+n7Tpnt3K8vTYD6rFuhSl/72xD9+VYtRrAMZzgeJCbXaV5sDxKggjhiaYXT143vGe2Bg= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763882681; c=relaxed/simple; bh=laqhXYcSE5aLkYc7pF2bt4DbzfCrooj7Lr3PO4a3cOw=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=pomM3yJjERWEdsUkSrv/lQp/9SB6S+6+WBvOg8DO9KD1HEbX9OC3b5LaYN9hifIt7jjYVJmDJ9mbLits3lQDQI8MnhyzlXlTXqp+7m5Ujs6++QKOBkc5PiecSaybGlTXRxFuKy0P/LshO+NEoOPy56vycLXqFy8CJ8CoMjv4JLU= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=fC8UljVG; arc=fail smtp.client-ip=40.93.194.0 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="fC8UljVG" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=Bmid4jejYOaCLyXJFuGNa3HZV7L4bu0fF7STKDCWJtpKPrktW+R0KAuCIEAtD7QwdNaC4YkKvZpUzkEQ6Gu2OIlAjJrwbJpW2R8KcH4rcCwvg/jWAIqsJkl3dkJLXX64mF3utuWeXbmOqibGxnJnccO7E1eG2p+X4Te9mXI3Wd0MZZlKDUo/t7lsZAsBrmROk2zwf86pmaLam47ORIMu8As1Mv5/njNeWxyZF/e2kh86AkIvpE83ROzyiRRlz2ADjsFT4GTI3QVrdSLw5LWa2KqbXPm4YHu9Hi6IX0kozECoi5YRJIPH51cj5kZJ02d6bb58Wvd17i9xg3/Bif4dsQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=0oMWPq9284fuT06yzYfZBkh46RG0wxVIVqeQ4t6rLNM=; b=qP5mYbvmtzSNglk+4suol1GS6nialE9mxxKgu6QWdwMDa0UrEa8tNizvZkO0qjWSxLyfyRQdRVtWNumnsERg3Q419eYgEbwj+Y2dt96p9cZsZ8UVMUdrw1xcVqnHPVaxZiDNagfmCX08cc/idEg0YPwMF+ZxyMRmVDg9Es3ldbYt4UVLqkWkdrVta+AMOyECD9FV3VkJeu0ZilrhviSxxf+QwgQgzczTolDQDP73piI+1wmQqV67tn05w1vExB5eYmjd6J9W3opzTEE1cQ1J4zN3noN55mGxSr22KOxZEulVHsIHKyPQvvw6XBFsTQKJYJM61+Rno+HknItjzLxWeg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=google.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=0oMWPq9284fuT06yzYfZBkh46RG0wxVIVqeQ4t6rLNM=; b=fC8UljVG6olh8cXRHjMsvdp9KA//9e11JcjR36gyw2W+ezFFXQywsCbBPwUS6p3gkgV271uHfMXngP1Abje1ZGCozMbPmt3doYDJ6S6ih5gEhS6qC5LxYPgYiKvXvoPeUbiuHb6tITAOqXRl1ZfqDx72s6TSXyQx1u//oAwTOu2ezqpMV4DIdwRjER2sfGm2HehY0hKRMFw8w2QA+c2vX7gzhJF1Nn4twwTwp8781U+W2UG3HsxB5d0dHaqKn7oFR3zSIosVJZFl6R+2aqQ7cTokZPZvk8Nq7dbE1WRmWVsp6U1XjKJcxelohr5/2MszsUjtCg0iberAyQ2Ts91Jog== Received: from SN1PR12CA0081.namprd12.prod.outlook.com (2603:10b6:802:21::16) by DS4PR12MB9659.namprd12.prod.outlook.com (2603:10b6:8:27f::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9343.15; Sun, 23 Nov 2025 07:24:29 +0000 Received: from SN1PEPF000397AF.namprd05.prod.outlook.com (2603:10b6:802:21:cafe::ca) by SN1PR12CA0081.outlook.office365.com (2603:10b6:802:21::16) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9343.16 via Frontend Transport; Sun, 23 Nov 2025 07:24:29 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by SN1PEPF000397AF.mail.protection.outlook.com (10.167.248.53) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9366.7 via Frontend Transport; Sun, 23 Nov 2025 07:24:29 +0000 Received: from rnnvmail203.nvidia.com (10.129.68.9) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Sat, 22 Nov 2025 23:24:20 -0800 Received: from rnnvmail201.nvidia.com (10.129.68.8) by rnnvmail203.nvidia.com (10.129.68.9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Sat, 22 Nov 2025 23:24:19 -0800 Received: from vdi.nvidia.com (10.127.8.10) by mail.nvidia.com (10.129.68.8) with Microsoft SMTP Server id 15.2.2562.20 via Frontend Transport; Sat, 22 Nov 2025 23:24:14 -0800 From: Tariq Toukan To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Donald Hunter , Jiri Pirko , Jonathan Corbet , Saeed Mahameed , "Leon Romanovsky" , Tariq Toukan , Mark Bloch , , , , , Gal Pressman , Moshe Shemesh , Carolina Jubran , Cosmin Ratiu , Jiri Pirko Subject: [PATCH net-next V2 11/14] net/mlx5: Store QoS sched nodes in the sh_devlink Date: Sun, 23 Nov 2025 09:22:57 +0200 Message-ID: <1763882580-1295213-12-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1763882580-1295213-1-git-send-email-tariqt@nvidia.com> References: <1763882580-1295213-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000397AF:EE_|DS4PR12MB9659:EE_ X-MS-Office365-Filtering-Correlation-Id: 43a4de11-4a46-483d-d894-08de2a6156ec X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|7416014|376014|82310400026|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?h9zBO40R/TRYwyQFrmuyBNb2BXTCd6HvnvKfqoqs8EYf30Xcfo+riYFnIVQH?= =?us-ascii?Q?xaersDuR4Z4298FZHcyYMgumoZvlL2mEtUidBDV48F/lhSnTs6RDzqXYfx9M?= =?us-ascii?Q?GSDSh+CXedqCcW/0/ac9LExJ7+5yHlg1PO+lJnLVFuW+jbqy+AcqC7X1UcTt?= =?us-ascii?Q?z0hIFX6QmTTUl27b9Uzfd/96dNGGcoBBtUitDT+z/d/i2fi/aX4+1nph9cwh?= =?us-ascii?Q?XIe07PDGdSbFFqcfM7EWB7pM0b8L9MRuaFd61oo8QpJpJ5/SHDk9jIopx2bG?= =?us-ascii?Q?fD6E3Hm7laHPtE3q/odsgpUdlZo6d9pkcXW2BRlJPxDhbydviZUUHgA8MgtH?= =?us-ascii?Q?6D2gofvZJunJ3N+s9TIhj0V/6JtZp5QRM66L1fI/AQBzaHaEZ0NIrHob2/qy?= =?us-ascii?Q?xEqTGbAScnoN+mFhwPyt2oiQTMVbIKqwTAH2x4ZYttGv6oGsXfOELxyykkrW?= =?us-ascii?Q?Lo/BqJMp7oYcg71KF7Ob22YXfqORWzlSWctqfPLzAfEeMxyeKhbszDhQCMkd?= =?us-ascii?Q?3Jz6egH5Dhh85oXD72H2Wljdm6tpynmN8hyDQbYA/11rpasdNs/bo/RjsXy4?= =?us-ascii?Q?Na8hKpxs5T51p+bi3reDrK/gUsLiSzNpVoDVo1VOuObmO6RFkU8hZJs2yaHk?= =?us-ascii?Q?hp8OhwbpdYyG7KSy76nqNU1Rkfp+jXag1rGzZt2qZ/2zSmXBxBpa6ZwhyaLG?= =?us-ascii?Q?KTHrrDIypf7PXdHQXBhtzz/dFm0FNWK/yF9W6WcuQED+CbgOyXqpFvJTjeFL?= =?us-ascii?Q?oPrLtRU2tpULibWm+5YreuO5vwEzJHgQ0BvUNEAnMgykCmj3ff0lBifxgAvE?= =?us-ascii?Q?+N0IjipINO6lMzc0r4fCQOsVT7d/JjWldQB2Tx/NczQhk8cCWVrIMfWSRH65?= =?us-ascii?Q?ha5ikRIqNv+8H8XRSQUPkzAMJH2NM5MLUp92tvooIgC1UhMswTQHNfyRUN/3?= =?us-ascii?Q?2ck6SLD8TO607A7j1lljIbk1hLVjVzqGCH9xe+J996OLrxusWu/5FJ6L53VT?= =?us-ascii?Q?lCRNiUXwLPmqC+dUcDcajSskOqk5WBiUdV2KlTylYG3ngr5Eyiap6F2hLhbw?= =?us-ascii?Q?qPdQnJF5QVvI5Hzp/SL7HyGdFPX46t32W/BrUQafNZeWcWpm1edikmsO30l7?= =?us-ascii?Q?EI8TDzr4ULU3VsEDVme9iMLzqGJY0QUm2dMj5tqRQOm/emHhOSCFKeFMMXxv?= =?us-ascii?Q?i+PDd6AhGMyjzPhZD4CoEBn3zFIp+1HVaV5mT273iXez0cRSTOgnMswNOGUO?= =?us-ascii?Q?pIrZ8/Dqq3P2qo6ftsiDxQm9i7chqCOny0doYGNlsjPL+79uAS2WKw+UQJcY?= =?us-ascii?Q?R7L4xMJrkNrep/Tlh0DBoz/2fggfKf4FNZDhy0rtjB1ZM2GbDTaJmTeaWB6T?= =?us-ascii?Q?r0gI4JE6D8TUJ1h9On5gQeJLbbAGJaBBFJ9CEu3gekvOC6chrfBrlwSm/e/R?= =?us-ascii?Q?iLpkvnDTPAsL8nZA/9XccM3jtwfMJWBcA0wCsu6qJBiQ93r7uqwgD8j4oBlW?= =?us-ascii?Q?LNquwnpeSD38rtkudHoh9GmYxmk3X79ov3bmxt7RpVz3uBrGD5fsAEGJ5iFp?= =?us-ascii?Q?+fIa07QJfiBvMxjjYFNrriUqB1xE318z8DypMxAO?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(7416014)(376014)(82310400026)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Nov 2025 07:24:29.0577 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 43a4de11-4a46-483d-d894-08de2a6156ec X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000397AF.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS4PR12MB9659 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Cosmin Ratiu In order to support cross-esw scheduling, the nodes for all devices need to be accessible from the same place so that normalization can work. Store them in the shared devlink instance and provide an accessor for them. Protecting against concurrent QoS modifications is now done with the shd lock. All calls originating from devlink rate already have the shd lock held so only the additional entry points into QoS need to acquire it. As part of this change, the E-Switch qos domain concept was removed. E-Switch QoS domains were added with the intention of eventually implementing shared qos domains to support cross-esw scheduling in the previous approach ([1]), but they are no longer necessary in the new approach. [1] https://lore.kernel.org/netdev/20250213180134.323929-1-tariqt@nvidia.co= m/ Signed-off-by: Cosmin Ratiu Reviewed-by: Carolina Jubran Signed-off-by: Tariq Toukan --- .../net/ethernet/mellanox/mlx5/core/esw/qos.c | 201 +++++------------- .../net/ethernet/mellanox/mlx5/core/esw/qos.h | 3 - .../net/ethernet/mellanox/mlx5/core/eswitch.c | 9 +- .../net/ethernet/mellanox/mlx5/core/eswitch.h | 11 +- .../ethernet/mellanox/mlx5/core/sh_devlink.c | 17 ++ .../ethernet/mellanox/mlx5/core/sh_devlink.h | 3 + 6 files changed, 76 insertions(+), 168 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/esw/qos.c index 8c3a026b8db4..f86d7c50db42 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c @@ -5,60 +5,16 @@ #include "lib/mlx5.h" #include "esw/qos.h" #include "en/port.h" +#include "sh_devlink.h" #define CREATE_TRACE_POINTS #include "diag/qos_tracepoint.h" =20 /* Minimum supported BW share value by the HW is 1 Mbit/sec */ #define MLX5_MIN_BW_SHARE 1 =20 -/* Holds rate nodes associated with an E-Switch. */ -struct mlx5_qos_domain { - /* Serializes access to all qos changes in the qos domain. */ - struct mutex lock; - /* List of all mlx5_esw_sched_nodes. */ - struct list_head nodes; -}; - -static void esw_qos_lock(struct mlx5_eswitch *esw) -{ - mutex_lock(&esw->qos.domain->lock); -} - -static void esw_qos_unlock(struct mlx5_eswitch *esw) -{ - mutex_unlock(&esw->qos.domain->lock); -} - static void esw_assert_qos_lock_held(struct mlx5_eswitch *esw) { - lockdep_assert_held(&esw->qos.domain->lock); -} - -static struct mlx5_qos_domain *esw_qos_domain_alloc(void) -{ - struct mlx5_qos_domain *qos_domain; - - qos_domain =3D kzalloc(sizeof(*qos_domain), GFP_KERNEL); - if (!qos_domain) - return NULL; - - mutex_init(&qos_domain->lock); - INIT_LIST_HEAD(&qos_domain->nodes); - - return qos_domain; -} - -static int esw_qos_domain_init(struct mlx5_eswitch *esw) -{ - esw->qos.domain =3D esw_qos_domain_alloc(); - - return esw->qos.domain ? 0 : -ENOMEM; -} - -static void esw_qos_domain_release(struct mlx5_eswitch *esw) -{ - kfree(esw->qos.domain); - esw->qos.domain =3D NULL; + mlx5_shd_assert_locked(esw->dev); } =20 enum sched_node_type { @@ -111,7 +67,8 @@ static void esw_qos_node_attach_to_parent(struct mlx5_es= w_sched_node *node) if (!node->parent) { /* Root children are assigned a depth level of 2. */ node->level =3D 2; - list_add_tail(&node->entry, &node->esw->qos.domain->nodes); + list_add_tail(&node->entry, + mlx5_shd_get_qos_nodes(node->esw->dev)); } else { node->level =3D node->parent->level + 1; list_add_tail(&node->entry, &node->parent->children); @@ -324,14 +281,15 @@ static int esw_qos_create_rate_limit_element(struct m= lx5_esw_sched_node *node, static u32 esw_qos_calculate_min_rate_divider(struct mlx5_eswitch *esw, struct mlx5_esw_sched_node *parent) { - struct list_head *nodes =3D parent ? &parent->children : &esw->qos.domain= ->nodes; u32 fw_max_bw_share =3D MLX5_CAP_QOS(esw->dev, max_tsar_bw_share); struct mlx5_esw_sched_node *node; + struct list_head *nodes; u32 max_guarantee =3D 0; =20 /* Find max min_rate across all nodes. * This will correspond to fw_max_bw_share in the final bw_share calculat= ion. */ + nodes =3D parent ? &parent->children : mlx5_shd_get_qos_nodes(esw->dev); list_for_each_entry(node, nodes, entry) { if (node->esw =3D=3D esw && node->ix !=3D esw->qos.root_tsar_ix && node->min_rate > max_guarantee) @@ -372,10 +330,11 @@ static void esw_qos_normalize_min_rate(struct mlx5_es= witch *esw, struct mlx5_esw_sched_node *parent, struct netlink_ext_ack *extack) { - struct list_head *nodes =3D parent ? &parent->children : &esw->qos.domain= ->nodes; u32 divider =3D esw_qos_calculate_min_rate_divider(esw, parent); struct mlx5_esw_sched_node *node; + struct list_head *nodes; =20 + nodes =3D parent ? &parent->children : mlx5_shd_get_qos_nodes(esw->dev); list_for_each_entry(node, nodes, entry) { if (node->esw !=3D esw || node->ix =3D=3D esw->qos.root_tsar_ix) continue; @@ -715,7 +674,7 @@ __esw_qos_create_vports_sched_node(struct mlx5_eswitch = *esw, struct mlx5_esw_sch goto err_alloc_node; } =20 - list_add_tail(&node->entry, &esw->qos.domain->nodes); + list_add_tail(&node->entry, mlx5_shd_get_qos_nodes(esw->dev)); esw_qos_normalize_min_rate(esw, NULL, extack); trace_mlx5_esw_node_qos_create(esw->dev, node, node->ix); =20 @@ -1108,7 +1067,8 @@ static int mlx5_esw_qos_vport_enable(struct mlx5_vpor= t *vport, enum sched_node_t return -ENOMEM; } if (!parent) - list_add_tail(&sched_node->entry, &esw->qos.domain->nodes); + list_add_tail(&sched_node->entry, + mlx5_shd_get_qos_nodes(esw->dev)); =20 sched_node->max_rate =3D max_rate; sched_node->min_rate =3D min_rate; @@ -1143,7 +1103,7 @@ void mlx5_esw_qos_vport_disable(struct mlx5_vport *vp= ort) struct mlx5_esw_sched_node *parent; =20 lockdep_assert_held(&esw->state_lock); - esw_qos_lock(esw); + mlx5_shd_lock(esw->dev); if (!vport->qos.sched_node) goto unlock; =20 @@ -1152,7 +1112,7 @@ void mlx5_esw_qos_vport_disable(struct mlx5_vport *vp= ort) =20 mlx5_esw_qos_vport_disable_locked(vport); unlock: - esw_qos_unlock(esw); + mlx5_shd_unlock(esw->dev); } =20 static int mlx5_esw_qos_set_vport_max_rate(struct mlx5_vport *vport, u32 m= ax_rate, @@ -1191,26 +1151,25 @@ int mlx5_esw_qos_set_vport_rate(struct mlx5_vport *= vport, u32 max_rate, u32 min_ struct mlx5_eswitch *esw =3D vport->dev->priv.eswitch; int err; =20 - esw_qos_lock(esw); + mlx5_shd_lock(esw->dev); err =3D mlx5_esw_qos_set_vport_min_rate(vport, min_rate, NULL); if (!err) err =3D mlx5_esw_qos_set_vport_max_rate(vport, max_rate, NULL); - esw_qos_unlock(esw); + mlx5_shd_unlock(esw->dev); return err; } =20 bool mlx5_esw_qos_get_vport_rate(struct mlx5_vport *vport, u32 *max_rate, = u32 *min_rate) { - struct mlx5_eswitch *esw =3D vport->dev->priv.eswitch; bool enabled; =20 - esw_qos_lock(esw); + mlx5_shd_lock(vport->dev); enabled =3D !!vport->qos.sched_node; if (enabled) { *max_rate =3D vport->qos.sched_node->max_rate; *min_rate =3D vport->qos.sched_node->min_rate; } - esw_qos_unlock(esw); + mlx5_shd_unlock(vport->dev); return enabled; } =20 @@ -1576,9 +1535,9 @@ int mlx5_esw_qos_modify_vport_rate(struct mlx5_eswitc= h *esw, u16 vport_num, u32 return err; } =20 - esw_qos_lock(esw); + mlx5_shd_lock(esw->dev); err =3D mlx5_esw_qos_set_vport_max_rate(vport, rate_mbps, NULL); - esw_qos_unlock(esw); + mlx5_shd_unlock(esw->dev); =20 return err; } @@ -1667,44 +1626,24 @@ static void esw_vport_qos_prune_empty(struct mlx5_v= port *vport) mlx5_esw_qos_vport_disable_locked(vport); } =20 -int mlx5_esw_qos_init(struct mlx5_eswitch *esw) -{ - if (esw->qos.domain) - return 0; /* Nothing to change. */ - - return esw_qos_domain_init(esw); -} - -void mlx5_esw_qos_cleanup(struct mlx5_eswitch *esw) -{ - if (esw->qos.domain) - esw_qos_domain_release(esw); -} - /* Eswitch devlink rate API */ =20 int mlx5_esw_devlink_rate_leaf_tx_share_set(struct devlink_rate *rate_leaf= , void *priv, u64 tx_share, struct netlink_ext_ack *extack) { struct mlx5_vport *vport =3D priv; - struct mlx5_eswitch *esw; int err; =20 - esw =3D vport->dev->priv.eswitch; - if (!mlx5_esw_allowed(esw)) + if (!mlx5_esw_allowed(vport->dev->priv.eswitch)) return -EPERM; =20 err =3D esw_qos_devlink_rate_to_mbps(vport->dev, "tx_share", &tx_share, e= xtack); if (err) return err; =20 - esw_qos_lock(esw); err =3D mlx5_esw_qos_set_vport_min_rate(vport, tx_share, extack); - if (err) - goto out; - esw_vport_qos_prune_empty(vport); -out: - esw_qos_unlock(esw); + if (!err) + esw_vport_qos_prune_empty(vport); return err; } =20 @@ -1712,24 +1651,18 @@ int mlx5_esw_devlink_rate_leaf_tx_max_set(struct de= vlink_rate *rate_leaf, void * u64 tx_max, struct netlink_ext_ack *extack) { struct mlx5_vport *vport =3D priv; - struct mlx5_eswitch *esw; int err; =20 - esw =3D vport->dev->priv.eswitch; - if (!mlx5_esw_allowed(esw)) + if (!mlx5_esw_allowed(vport->dev->priv.eswitch)) return -EPERM; =20 err =3D esw_qos_devlink_rate_to_mbps(vport->dev, "tx_max", &tx_max, extac= k); if (err) return err; =20 - esw_qos_lock(esw); err =3D mlx5_esw_qos_set_vport_max_rate(vport, tx_max, extack); - if (err) - goto out; - esw_vport_qos_prune_empty(vport); -out: - esw_qos_unlock(esw); + if (!err) + esw_vport_qos_prune_empty(vport); return err; } =20 @@ -1740,34 +1673,30 @@ int mlx5_esw_devlink_rate_leaf_tc_bw_set(struct dev= link_rate *rate_leaf, { struct mlx5_esw_sched_node *vport_node; struct mlx5_vport *vport =3D priv; - struct mlx5_eswitch *esw; bool disable; int err =3D 0; =20 - esw =3D vport->dev->priv.eswitch; - if (!mlx5_esw_allowed(esw)) + if (!mlx5_esw_allowed(vport->dev->priv.eswitch)) return -EPERM; =20 disable =3D esw_qos_tc_bw_disabled(tc_bw); - esw_qos_lock(esw); =20 if (!esw_qos_vport_validate_unsupported_tc_bw(vport, tc_bw)) { NL_SET_ERR_MSG_MOD(extack, "E-Switch traffic classes number is not supported"); - err =3D -EOPNOTSUPP; - goto unlock; + return -EOPNOTSUPP; } =20 vport_node =3D vport->qos.sched_node; if (disable && !vport_node) - goto unlock; + return 0; =20 if (disable) { if (vport_node->type =3D=3D SCHED_NODE_TYPE_TC_ARBITER_TSAR) err =3D esw_qos_vport_update(vport, SCHED_NODE_TYPE_VPORT, vport_node->parent, extack); esw_vport_qos_prune_empty(vport); - goto unlock; + return err; } =20 if (!vport_node) { @@ -1782,8 +1711,6 @@ int mlx5_esw_devlink_rate_leaf_tc_bw_set(struct devli= nk_rate *rate_leaf, } if (!err) esw_qos_set_tc_arbiter_bw_shares(vport_node, tc_bw, extack); -unlock: - esw_qos_unlock(esw); return err; } =20 @@ -1793,28 +1720,22 @@ int mlx5_esw_devlink_rate_node_tc_bw_set(struct dev= link_rate *rate_node, struct netlink_ext_ack *extack) { struct mlx5_esw_sched_node *node =3D priv; - struct mlx5_eswitch *esw =3D node->esw; bool disable; int err; =20 - if (!esw_qos_validate_unsupported_tc_bw(esw, tc_bw)) { + if (!esw_qos_validate_unsupported_tc_bw(node->esw, tc_bw)) { NL_SET_ERR_MSG_MOD(extack, "E-Switch traffic classes number is not supported"); return -EOPNOTSUPP; } =20 disable =3D esw_qos_tc_bw_disabled(tc_bw); - esw_qos_lock(esw); - if (disable) { - err =3D esw_qos_node_disable_tc_arbitration(node, extack); - goto unlock; - } + if (disable) + return esw_qos_node_disable_tc_arbitration(node, extack); =20 err =3D esw_qos_node_enable_tc_arbitration(node, extack); if (!err) esw_qos_set_tc_arbiter_bw_shares(node, tc_bw, extack); -unlock: - esw_qos_unlock(esw); return err; } =20 @@ -1822,17 +1743,14 @@ int mlx5_esw_devlink_rate_node_tx_share_set(struct = devlink_rate *rate_node, void u64 tx_share, struct netlink_ext_ack *extack) { struct mlx5_esw_sched_node *node =3D priv; - struct mlx5_eswitch *esw =3D node->esw; int err; =20 - err =3D esw_qos_devlink_rate_to_mbps(esw->dev, "tx_share", &tx_share, ext= ack); + err =3D esw_qos_devlink_rate_to_mbps(node->esw->dev, "tx_share", + &tx_share, extack); if (err) return err; =20 - esw_qos_lock(esw); - err =3D esw_qos_set_node_min_rate(node, tx_share, extack); - esw_qos_unlock(esw); - return err; + return esw_qos_set_node_min_rate(node, tx_share, extack); } =20 int mlx5_esw_devlink_rate_node_tx_max_set(struct devlink_rate *rate_node, = void *priv, @@ -1846,10 +1764,7 @@ int mlx5_esw_devlink_rate_node_tx_max_set(struct dev= link_rate *rate_node, void * if (err) return err; =20 - esw_qos_lock(esw); - err =3D esw_qos_sched_elem_config(node, tx_max, node->bw_share, extack); - esw_qos_unlock(esw); - return err; + return esw_qos_sched_elem_config(node, tx_max, node->bw_share, extack); } =20 int mlx5_esw_devlink_rate_node_new(struct devlink_rate *rate_node, void **= priv, @@ -1857,30 +1772,23 @@ int mlx5_esw_devlink_rate_node_new(struct devlink_r= ate *rate_node, void **priv, { struct mlx5_esw_sched_node *node; struct mlx5_eswitch *esw; - int err =3D 0; =20 esw =3D mlx5_devlink_eswitch_get(rate_node->devlink); if (IS_ERR(esw)) return PTR_ERR(esw); =20 - esw_qos_lock(esw); if (esw->mode !=3D MLX5_ESWITCH_OFFLOADS) { NL_SET_ERR_MSG_MOD(extack, "Rate node creation supported only in switchdev mode"); - err =3D -EOPNOTSUPP; - goto unlock; + return -EOPNOTSUPP; } =20 node =3D esw_qos_create_vports_sched_node(esw, extack); - if (IS_ERR(node)) { - err =3D PTR_ERR(node); - goto unlock; - } + if (IS_ERR(node)) + return PTR_ERR(node); =20 *priv =3D node; -unlock: - esw_qos_unlock(esw); - return err; + return 0; } =20 int mlx5_esw_devlink_rate_node_del(struct devlink_rate *rate_node, void *p= riv, @@ -1889,10 +1797,9 @@ int mlx5_esw_devlink_rate_node_del(struct devlink_ra= te *rate_node, void *priv, struct mlx5_esw_sched_node *node =3D priv; struct mlx5_eswitch *esw =3D node->esw; =20 - esw_qos_lock(esw); __esw_qos_destroy_node(node, extack); esw_qos_put(esw); - esw_qos_unlock(esw); + return 0; } =20 @@ -1909,7 +1816,6 @@ mlx5_esw_qos_vport_update_parent(struct mlx5_vport *v= port, return -EOPNOTSUPP; } =20 - esw_qos_lock(esw); if (!vport->qos.sched_node && parent) { enum sched_node_type type; =20 @@ -1920,13 +1826,15 @@ mlx5_esw_qos_vport_update_parent(struct mlx5_vport = *vport, } else if (vport->qos.sched_node) { err =3D esw_qos_vport_update_parent(vport, parent, extack); } - esw_qos_unlock(esw); + return err; } =20 void mlx5_esw_qos_vport_clear_parent(struct mlx5_vport *vport) { + mlx5_shd_lock(vport->dev); mlx5_esw_qos_vport_update_parent(vport, NULL, NULL); + mlx5_shd_unlock(vport->dev); } =20 int mlx5_esw_devlink_rate_leaf_parent_set(struct devlink_rate *devlink_rat= e, @@ -1939,13 +1847,8 @@ int mlx5_esw_devlink_rate_leaf_parent_set(struct dev= link_rate *devlink_rate, int err; =20 err =3D mlx5_esw_qos_vport_update_parent(vport, node, extack); - if (!err) { - struct mlx5_eswitch *esw =3D vport->dev->priv.eswitch; - - esw_qos_lock(esw); + if (!err) esw_vport_qos_prune_empty(vport); - esw_qos_unlock(esw); - } =20 return err; } @@ -2071,14 +1974,12 @@ static int mlx5_esw_qos_node_update_parent(struct m= lx5_esw_sched_node *node, struct netlink_ext_ack *extack) { struct mlx5_esw_sched_node *curr_parent; - struct mlx5_eswitch *esw =3D node->esw; int err; =20 err =3D mlx5_esw_qos_node_validate_set_parent(node, parent, extack); if (err) return err; =20 - esw_qos_lock(esw); curr_parent =3D node->parent; if (node->type =3D=3D SCHED_NODE_TYPE_TC_ARBITER_TSAR) { err =3D esw_qos_tc_arbiter_node_update_parent(node, parent, @@ -2088,15 +1989,11 @@ static int mlx5_esw_qos_node_update_parent(struct m= lx5_esw_sched_node *node, } =20 if (err) - goto out; - - esw_qos_normalize_min_rate(esw, curr_parent, extack); - esw_qos_normalize_min_rate(esw, parent, extack); - -out: - esw_qos_unlock(esw); + return err; =20 - return err; + esw_qos_normalize_min_rate(node->esw, curr_parent, extack); + esw_qos_normalize_min_rate(node->esw, parent, extack); + return 0; } =20 int mlx5_esw_devlink_rate_node_parent_set(struct devlink_rate *devlink_rat= e, diff --git a/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.h b/drivers/ne= t/ethernet/mellanox/mlx5/core/esw/qos.h index 0a50982b0e27..f275e850d2c9 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.h @@ -6,9 +6,6 @@ =20 #ifdef CONFIG_MLX5_ESWITCH =20 -int mlx5_esw_qos_init(struct mlx5_eswitch *esw); -void mlx5_esw_qos_cleanup(struct mlx5_eswitch *esw); - int mlx5_esw_qos_set_vport_rate(struct mlx5_vport *evport, u32 max_rate, u= 32 min_rate); bool mlx5_esw_qos_get_vport_rate(struct mlx5_vport *vport, u32 *max_rate, = u32 *min_rate); void mlx5_esw_qos_vport_disable(struct mlx5_vport *vport); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/eswitch.c index 4b7a1ce7f406..51eacc286cbb 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c @@ -49,6 +49,7 @@ #include "ecpf.h" #include "en/mod_hdr.h" #include "en_accel/ipsec.h" +#include "sh_devlink.h" =20 enum { MLX5_ACTION_NONE =3D 0, @@ -1618,10 +1619,6 @@ int mlx5_eswitch_enable_locked(struct mlx5_eswitch *= esw, int num_vfs) MLX5_NB_INIT(&esw->nb, eswitch_vport_event, NIC_VPORT_CHANGE); mlx5_eq_notifier_register(esw->dev, &esw->nb); =20 - err =3D mlx5_esw_qos_init(esw); - if (err) - goto err_esw_init; - if (esw->mode =3D=3D MLX5_ESWITCH_LEGACY) { err =3D esw_legacy_enable(esw); } else { @@ -2028,9 +2025,6 @@ int mlx5_eswitch_init(struct mlx5_core_dev *dev) goto reps_err; =20 esw->mode =3D MLX5_ESWITCH_LEGACY; - err =3D mlx5_esw_qos_init(esw); - if (err) - goto reps_err; =20 mutex_init(&esw->offloads.encap_tbl_lock); hash_init(esw->offloads.encap_tbl); @@ -2080,7 +2074,6 @@ void mlx5_eswitch_cleanup(struct mlx5_eswitch *esw) =20 esw_info(esw->dev, "cleanup\n"); =20 - mlx5_esw_qos_cleanup(esw); destroy_workqueue(esw->work_queue); WARN_ON(refcount_read(&esw->qos.refcnt)); mutex_destroy(&esw->state_lock); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h b/drivers/ne= t/ethernet/mellanox/mlx5/core/eswitch.h index 20cf9dd542a1..d145591b3434 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h @@ -224,8 +224,9 @@ struct mlx5_vport { =20 struct mlx5_vport_info info; =20 - /* Protected with the E-Switch qos domain lock. The Vport QoS can - * either be disabled (sched_node is NULL) or in one of three states: + /* Protected by mlx5_shd_lock(). + * The Vport QoS can either be disabled (sched_node is NULL) or in one + * of three states: * 1. Regular QoS (sched_node is a vport node). * 2. TC QoS enabled on the vport (sched_node is a TC arbiter). * 3. TC QoS enabled on the vport's parent node @@ -356,7 +357,6 @@ enum { }; =20 struct dentry; -struct mlx5_qos_domain; =20 struct mlx5_eswitch { struct mlx5_core_dev *dev; @@ -383,12 +383,13 @@ struct mlx5_eswitch { struct rw_semaphore mode_lock; atomic64_t user_count; =20 - /* Protected with the E-Switch qos domain lock. */ + /* The QoS tree is stored in mlx5_shd. + * QoS changes are serialized with mlx5_shd_lock(). + */ struct { /* Initially 0, meaning no QoS users and QoS is disabled. */ refcount_t refcnt; u32 root_tsar_ix; - struct mlx5_qos_domain *domain; } qos; =20 struct mlx5_esw_bridge_offloads *br_offloads; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/sh_devlink.c b/drivers= /net/ethernet/mellanox/mlx5/core/sh_devlink.c index e39a5e20e102..ef073cc53f8e 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/sh_devlink.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/sh_devlink.c @@ -22,6 +22,8 @@ struct mlx5_shd { struct list_head dev_list; /* Related faux device */ struct faux_device *faux_dev; + /* List of esw qos nodes. */ + struct list_head qos_nodes; }; =20 static const struct devlink_ops mlx5_shd_ops =3D { @@ -76,6 +78,7 @@ static struct mlx5_shd *mlx5_shd_create(const char *sn) shd->sn =3D sn; INIT_LIST_HEAD(&shd->dev_list); shd->faux_dev =3D faux_dev; + INIT_LIST_HEAD(&shd->qos_nodes); return shd; } =20 @@ -164,3 +167,17 @@ void mlx5_shd_unlock(struct mlx5_core_dev *dev) return; devl_unlock(priv_to_devlink(dev->shd)); } + +void mlx5_shd_assert_locked(struct mlx5_core_dev *dev) +{ + if (dev->shd) + devl_assert_locked(priv_to_devlink(dev->shd)); +} + +struct list_head *mlx5_shd_get_qos_nodes(struct mlx5_core_dev *dev) +{ + if (!dev->shd) + return NULL; + mlx5_shd_assert_locked(dev); + return &dev->shd->qos_nodes; +} diff --git a/drivers/net/ethernet/mellanox/mlx5/core/sh_devlink.h b/drivers= /net/ethernet/mellanox/mlx5/core/sh_devlink.h index 54ce0389cfea..56ead7e11756 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/sh_devlink.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/sh_devlink.h @@ -8,6 +8,9 @@ int mlx5_shd_init(struct mlx5_core_dev *dev); void mlx5_shd_uninit(struct mlx5_core_dev *dev); void mlx5_shd_lock(struct mlx5_core_dev *dev); void mlx5_shd_unlock(struct mlx5_core_dev *dev); +void mlx5_shd_assert_locked(struct mlx5_core_dev *dev); void mlx5_shd_nested_set(struct mlx5_core_dev *dev); =20 +struct list_head *mlx5_shd_get_qos_nodes(struct mlx5_core_dev *dev); + #endif /* __MLX5_SH_DEVLINK_H__ */ --=20 2.31.1 From nobody Tue Dec 2 00:46:21 2025 Received: from PH8PR06CU001.outbound.protection.outlook.com (mail-westus3azon11012066.outbound.protection.outlook.com [40.107.209.66]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 01595296BBF; Sun, 23 Nov 2025 07:24:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.209.66 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763882682; cv=fail; b=lr0tlJww59jGtFtmAov8kKnY9alb5hlFR5Uqz8RgIrlvPcL4ZS7hsG8OXza0dssgJaj7l8NDE8/AN3ne6DHcuZr17qUPFloByuMk9BMoMykQSBS3p33cL+fW00rLjd0QWF+FHhFfnnWp4aoODYOvJEa1/MHxC/QBXsv6035lLLE= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763882682; c=relaxed/simple; bh=U36XFRQKma578uT1QkEf2v87DJbed/6ShXc7asbeyP8=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=uJPLA5tSNu9j/ETsDrqIOdsfZOQxXkupHiPgnrVY+Nx12V8dOuicKPqWXJ4MkWoFQQSDPH3Y0+0CXj9KI8jVvhS5fl2FfqGBIyPBs7yLlMP6yhPdQX8Y7nnsn1BONf5180Rph49sYbKoX96emKFTCImJHrjGDjpftQDFvAMWTP4= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=dc30qGvu; arc=fail smtp.client-ip=40.107.209.66 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="dc30qGvu" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=dPZ84UQ47cSD87j9lOcMcG+Kmvyjx+XJGvUr9n2tN9vZ+XDvxBlXwNptvOrzYDoIhgksxq5fpUYvpWbwJETSAwe9pCvKA8PhD0DgkcxfoDHtKxKPL3leuTltxnR7x1DztGIGcEouTk8t9G6VGmXPAFLnqmIiAKmWywJ28gfdBl/tlsk/HtwTs5jnM2v/vUpvZ3GN+jY7aLToN9DW7Vfrjjrs104dN36f3zajrQTtssPfi7mIp1GQSRKuoLvomSMZ2k5AYpbDwBKlHM0yuc5NSooZ0XY3jkInMO8KMt7v4/EtsSLwhNe9S8ysBzej6wJI3EySDWXZDY7f1R7Su8l/FA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=AkAo1WA+IHZyE4a32jxwkjwBJAj50MNSpTK0tDiJPFs=; b=D9rJRDSbBPQEFHLNzGUs4jYZ5GhRlA+ZcnaUO17+tYxA2/Pp3IsJjRryTnBVIFgTMUTDg9Qvnj/K30mvx5wL3pvaw/HkmGG2zzmOhsu0K/PsUXXxvF3LBqKj+lEd1xud3sndUwlRVsniA1YO5fs4n94+Wwd96JBSvBvWxZAntE52kslYS7glIpgMm2P67aFGJwTm+xiH9SK7kOFJeyAhuQCvzwJozzcvWIzqEtaYlH66RkKKBsDlI3vGZPIKbataEw/nVqLsHDpAdK9NQjhqYiuqIN60B9VQjDTGIbdkAMblAaZg1yshQ+gkz81c2jdeceo7snq/YBZW5fXba5bd6A== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=google.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=AkAo1WA+IHZyE4a32jxwkjwBJAj50MNSpTK0tDiJPFs=; b=dc30qGvu7GdZP7ok8Velhqgy1YNdocjm7UOvDyyVLpm6zEAQyROL7bjw1N1EPfrVjOU3+mkb7S7K+ZRPJZ7FQ7DUrWvnV0r1Ph06xRs1CyazpimoFrdxoUlz8tbgubMRkBe+oNi4bEi6ch/NmV/FaIqdCQGfPd+Q1b1vM72482vHW1moii6LYI3mOTGnLE8rSeVjja6CKYmCuMlDPpTlPUnrQ7c1P48pm3S8G0CX07yTzf2wLMhv8svXR5MlsXlUV2M71YiLJ0ikqaxyV1Wnf4gQi/8R/5HQyr+QumY9PJ0Ti6OC6fLFp7VEYga+dHZb2fDGFAGHLQh0d9gpb0Avsg== Received: from DM6PR11CA0015.namprd11.prod.outlook.com (2603:10b6:5:190::28) by IA1PR12MB7616.namprd12.prod.outlook.com (2603:10b6:208:427::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9343.12; Sun, 23 Nov 2025 07:24:35 +0000 Received: from DS2PEPF00003445.namprd04.prod.outlook.com (2603:10b6:5:190:cafe::28) by DM6PR11CA0015.outlook.office365.com (2603:10b6:5:190::28) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9343.15 via Frontend Transport; Sun, 23 Nov 2025 07:24:35 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by DS2PEPF00003445.mail.protection.outlook.com (10.167.17.72) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9366.7 via Frontend Transport; Sun, 23 Nov 2025 07:24:35 +0000 Received: from rnnvmail203.nvidia.com (10.129.68.9) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Sat, 22 Nov 2025 23:24:26 -0800 Received: from rnnvmail201.nvidia.com (10.129.68.8) by rnnvmail203.nvidia.com (10.129.68.9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Sat, 22 Nov 2025 23:24:26 -0800 Received: from vdi.nvidia.com (10.127.8.10) by mail.nvidia.com (10.129.68.8) with Microsoft SMTP Server id 15.2.2562.20 via Frontend Transport; Sat, 22 Nov 2025 23:24:20 -0800 From: Tariq Toukan To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Donald Hunter , Jiri Pirko , Jonathan Corbet , Saeed Mahameed , "Leon Romanovsky" , Tariq Toukan , Mark Bloch , , , , , Gal Pressman , Moshe Shemesh , Carolina Jubran , Cosmin Ratiu , Jiri Pirko Subject: [PATCH net-next V2 12/14] net/mlx5: qos: Support cross-device tx scheduling Date: Sun, 23 Nov 2025 09:22:58 +0200 Message-ID: <1763882580-1295213-13-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1763882580-1295213-1-git-send-email-tariqt@nvidia.com> References: <1763882580-1295213-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF00003445:EE_|IA1PR12MB7616:EE_ X-MS-Office365-Filtering-Correlation-Id: 2b32c8e2-a9f9-4ce9-78f4-08de2a615a99 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|376014|7416014|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?0jdIJrQt6MhQhmOyKNUwoEg0lbhE+rBQms190BofQraczDvr9MCytQPf2g3h?= =?us-ascii?Q?tTlwk7x87232u6gour+uDhh3gBQ4TtVflHUinCn2NjQyGDsQsMktyhSVPupo?= =?us-ascii?Q?HdbeOgM+uqiAeik048e+ZuwtEgDELN3XAzhKcHdgrxwzUqDMR7eADXCwK9jd?= =?us-ascii?Q?ZY04i8uacKBIGnZBHVnRh0/kYvs/aVpqt0FgHJbyaedJLEj/jSL7OZEsM4zY?= =?us-ascii?Q?o0ALxTbE4bEClzYIb2C2k8c9WIjWgDtmTVsUdOY10l7wjKaz2WdAne5s+0Hp?= =?us-ascii?Q?B94zj0PcRiPp6LtLt9esIgB4M/wmChkrrwrwXyzhzldlaGxO6xlM8ZH2OeSA?= =?us-ascii?Q?N4nkEYshIPEyzv+OjY7FWsyVOgSBwgcp5TLIP8krTNnJsz2N6yb4xLacuM3j?= =?us-ascii?Q?rsUfzs/0yC0QUsv8diN/pr/1NslxJhT+MLDGaopvl0WoDABM7oUute/3SKFK?= =?us-ascii?Q?IpsFDS9WDI7sqZ3tZUBrRYFZq2w2lRlKo3l1BSuDpZ8wiget8ibvvxk4B4Jm?= =?us-ascii?Q?B/tKA3n+POjod/XDsDxg/KDh1eGA83AqoQTzgGQzWWmoPmw+NPoLaaVthNXH?= =?us-ascii?Q?/L+UxSSxqd603PmzCVV6jZiV0MSSovplCiweqw6PsKOa0Jjb5QMgpKRgZBnO?= =?us-ascii?Q?t0erFYHXl3TT8x9cBM7wdl0ZhzZZ/NvS/fluE+2O2WiQpPgGb45XnbVlezhq?= =?us-ascii?Q?7jkaiHALmEx8FR4SvMPEkU7g7BCIkdOB1vAdRbTRQ6+HLeL4brg61wwbmiVa?= =?us-ascii?Q?E6vzxFKU3uEcnYSkTFITIeXkLI1feWKBqnd7Wu3FQcWcj+d+WPgxApd2J1qG?= =?us-ascii?Q?VtJN/IB29QbvwDWGhE+4zmMAk4BvX6pNknnal1O2r2MqkhmwJUc0BnoQWV1c?= =?us-ascii?Q?jPXY9UjeYXLgbsCYPX9A4mwGzj7DAQkOC0cX1Oo5vqyU8HsOdlNvKg9/VR+n?= =?us-ascii?Q?jXVMW6adCRqtI0UklzMltqLE/Q6kwBnUfA1hSjuE1xYjCkATlwvOrtUP2vGz?= =?us-ascii?Q?R397qXgt9aBv/OYrCYMxz51BLvxnT5WYeZBVKyXNiVZMngK1BFXd/wnMhElR?= =?us-ascii?Q?6hEXrVw/48I6SvwzpNeEbIyKkgA2TDEHAS0UIFS/gkEjNNmntDLohNtjhdo7?= =?us-ascii?Q?u1ZA5kVIwhiIvOoOBHLrPSYi8NDseso+rkoukAEsOlyYwKAa3eWmc7GIXSY7?= =?us-ascii?Q?hbdwPM2ZcttejcmIrUdf4WGkKnxD7PKx6WaRe1Zc55WkkZGFVugIMb6lK87t?= =?us-ascii?Q?VWr+2ziKjDaaat0N/9M1ZaJfu7Kx6NNsuNmCFv4CKh44J7lqZY9QWxh6Q/5v?= =?us-ascii?Q?clbk87HXe0ySFt+YblfhK5xdMTkKs69vOM4VOO93TItqv8h+MAnhFmESwDk5?= =?us-ascii?Q?KNftD89apze/t1mv1oK3wzL+TzC1t6GKdjkQE5sTJIjNJCBE0niVLRBi5dPr?= =?us-ascii?Q?atZd1qytn0OfJ+n2/M4lJbTical7HW+026YRQU9GGN77mbJRcxA6pszA4Px/?= =?us-ascii?Q?U5NPAN/fFxNH1DKaz4ztkM44+wIP9YRyZWGgmRas+vW0BkasouCbDusq9WFd?= =?us-ascii?Q?GqjIhgQBIZK1xz66o8k=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(1800799024)(376014)(7416014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Nov 2025 07:24:35.1937 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2b32c8e2-a9f9-4ce9-78f4-08de2a615a99 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF00003445.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB7616 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Cosmin Ratiu Up to now, rate groups could only contain vports from the same E-Switch. This patch relaxes that restriction if the device supports it (HCA_CAP.esw_cross_esw_sched =3D=3D true) and the right conditions are met: - Link Aggregation (LAG) is enabled. - The E-Switches are from the same shared devlink device. This patch does not yet enable cross-esw scheduling, it's just the last preparatory patch. Signed-off-by: Cosmin Ratiu Reviewed-by: Carolina Jubran Signed-off-by: Tariq Toukan --- .../net/ethernet/mellanox/mlx5/core/esw/qos.c | 114 +++++++++++++----- 1 file changed, 81 insertions(+), 33 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/esw/qos.c index f86d7c50db42..3c8716b0644b 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c @@ -50,7 +50,9 @@ struct mlx5_esw_sched_node { enum sched_node_type type; /* The eswitch this node belongs to. */ struct mlx5_eswitch *esw; - /* The children nodes of this node, empty list for leaf nodes. */ + /* The children nodes of this node, empty list for leaf nodes. + * Can be from multiple E-Switches. + */ struct list_head children; /* Valid only if this node is associated with a vport. */ struct mlx5_vport *vport; @@ -419,6 +421,7 @@ esw_qos_vport_create_sched_element(struct mlx5_esw_sche= d_node *vport_node, struct mlx5_esw_sched_node *parent =3D vport_node->parent; u32 sched_ctx[MLX5_ST_SZ_DW(scheduling_context)] =3D {}; struct mlx5_core_dev *dev =3D vport_node->esw->dev; + struct mlx5_vport *vport =3D vport_node->vport; void *attr; =20 if (!mlx5_qos_element_type_supported( @@ -430,11 +433,18 @@ esw_qos_vport_create_sched_element(struct mlx5_esw_sc= hed_node *vport_node, MLX5_SET(scheduling_context, sched_ctx, element_type, SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT); attr =3D MLX5_ADDR_OF(scheduling_context, sched_ctx, element_attributes); - MLX5_SET(vport_element, attr, vport_number, vport_node->vport->vport); + MLX5_SET(vport_element, attr, vport_number, vport->vport); MLX5_SET(scheduling_context, sched_ctx, parent_element_id, parent ? parent->ix : vport_node->esw->qos.root_tsar_ix); MLX5_SET(scheduling_context, sched_ctx, max_average_bw, vport_node->max_rate); + if (vport->dev !=3D dev) { + /* The port is assigned to a node on another eswitch. */ + MLX5_SET(vport_element, attr, eswitch_owner_vhca_id_valid, + true); + MLX5_SET(vport_element, attr, eswitch_owner_vhca_id, + MLX5_CAP_GEN(vport->dev, vhca_id)); + } =20 return esw_qos_node_create_sched_element(vport_node, sched_ctx, extack); } @@ -446,6 +456,7 @@ esw_qos_vport_tc_create_sched_element(struct mlx5_esw_s= ched_node *vport_tc_node, { u32 sched_ctx[MLX5_ST_SZ_DW(scheduling_context)] =3D {}; struct mlx5_core_dev *dev =3D vport_tc_node->esw->dev; + struct mlx5_vport *vport =3D vport_tc_node->vport; void *attr; =20 if (!mlx5_qos_element_type_supported( @@ -457,8 +468,7 @@ esw_qos_vport_tc_create_sched_element(struct mlx5_esw_s= ched_node *vport_tc_node, MLX5_SET(scheduling_context, sched_ctx, element_type, SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC); attr =3D MLX5_ADDR_OF(scheduling_context, sched_ctx, element_attributes); - MLX5_SET(vport_tc_element, attr, vport_number, - vport_tc_node->vport->vport); + MLX5_SET(vport_tc_element, attr, vport_number, vport->vport); MLX5_SET(vport_tc_element, attr, traffic_class, vport_tc_node->tc); MLX5_SET(scheduling_context, sched_ctx, max_bw_obj_id, rate_limit_elem_ix); @@ -466,6 +476,13 @@ esw_qos_vport_tc_create_sched_element(struct mlx5_esw_= sched_node *vport_tc_node, vport_tc_node->parent->ix); MLX5_SET(scheduling_context, sched_ctx, bw_share, vport_tc_node->bw_share); + if (vport->dev !=3D dev) { + /* The port is assigned to a node on another eswitch. */ + MLX5_SET(vport_tc_element, attr, eswitch_owner_vhca_id_valid, + true); + MLX5_SET(vport_tc_element, attr, eswitch_owner_vhca_id, + MLX5_CAP_GEN(vport->dev, vhca_id)); + } =20 return esw_qos_node_create_sched_element(vport_tc_node, sched_ctx, extack); @@ -1194,6 +1211,29 @@ static int esw_qos_vport_tc_check_type(enum sched_no= de_type curr_type, return 0; } =20 +static bool esw_qos_validate_unsupported_tc_bw(struct mlx5_eswitch *esw, + u32 *tc_bw) +{ + int i, num_tcs =3D esw_qos_num_tcs(esw->dev); + + for (i =3D num_tcs; i < DEVLINK_RATE_TCS_MAX; i++) + if (tc_bw[i]) + return false; + + return true; +} + +static bool esw_qos_vport_validate_unsupported_tc_bw(struct mlx5_vport *vp= ort, + u32 *tc_bw) +{ + struct mlx5_esw_sched_node *node =3D vport->qos.sched_node; + struct mlx5_eswitch *esw =3D vport->dev->priv.eswitch; + + esw =3D (node && node->parent) ? node->parent->esw : esw; + + return esw_qos_validate_unsupported_tc_bw(esw, tc_bw); +} + static int esw_qos_vport_update(struct mlx5_vport *vport, enum sched_node_type type, struct mlx5_esw_sched_node *parent, @@ -1227,6 +1267,12 @@ static int esw_qos_vport_update(struct mlx5_vport *v= port, if (curr_type =3D=3D SCHED_NODE_TYPE_TC_ARBITER_TSAR && curr_type =3D=3D = type) { esw_qos_set_tc_arbiter_bw_shares(vport_node, curr_tc_bw, extack); + if (!esw_qos_validate_unsupported_tc_bw(parent->esw, + curr_tc_bw)) { + NL_SET_ERR_MSG_MOD(extack, + "Unsupported traffic classes on the new device"); + return -EOPNOTSUPP; + } } =20 return err; @@ -1575,30 +1621,6 @@ static int esw_qos_devlink_rate_to_mbps(struct mlx5_= core_dev *mdev, const char * return 0; } =20 -static bool esw_qos_validate_unsupported_tc_bw(struct mlx5_eswitch *esw, - u32 *tc_bw) -{ - int i, num_tcs =3D esw_qos_num_tcs(esw->dev); - - for (i =3D num_tcs; i < DEVLINK_RATE_TCS_MAX; i++) { - if (tc_bw[i]) - return false; - } - - return true; -} - -static bool esw_qos_vport_validate_unsupported_tc_bw(struct mlx5_vport *vp= ort, - u32 *tc_bw) -{ - struct mlx5_esw_sched_node *node =3D vport->qos.sched_node; - struct mlx5_eswitch *esw =3D vport->dev->priv.eswitch; - - esw =3D (node && node->parent) ? node->parent->esw : esw; - - return esw_qos_validate_unsupported_tc_bw(esw, tc_bw); -} - static bool esw_qos_tc_bw_disabled(u32 *tc_bw) { int i; @@ -1803,18 +1825,44 @@ int mlx5_esw_devlink_rate_node_del(struct devlink_r= ate *rate_node, void *priv, return 0; } =20 +static int +mlx5_esw_validate_cross_esw_scheduling(struct mlx5_eswitch *esw, + struct mlx5_esw_sched_node *parent, + struct netlink_ext_ack *extack) +{ + if (!parent || esw =3D=3D parent->esw) + return 0; + + if (!MLX5_CAP_QOS(esw->dev, esw_cross_esw_sched)) { + NL_SET_ERR_MSG_MOD(extack, + "Cross E-Switch scheduling is not supported"); + return -EOPNOTSUPP; + } + if (esw->dev->shd !=3D parent->esw->dev->shd) { + NL_SET_ERR_MSG_MOD(extack, + "Cannot add vport to a parent belonging to a different device"); + return -EOPNOTSUPP; + } + if (!mlx5_lag_is_active(esw->dev)) { + NL_SET_ERR_MSG_MOD(extack, + "Cross E-Switch scheduling requires LAG to be activated"); + return -EOPNOTSUPP; + } + + return 0; +} + static int mlx5_esw_qos_vport_update_parent(struct mlx5_vport *vport, struct mlx5_esw_sched_node *parent, struct netlink_ext_ack *extack) { struct mlx5_eswitch *esw =3D vport->dev->priv.eswitch; - int err =3D 0; + int err; =20 - if (parent && parent->esw !=3D esw) { - NL_SET_ERR_MSG_MOD(extack, "Cross E-Switch scheduling is not supported"); - return -EOPNOTSUPP; - } + err =3D mlx5_esw_validate_cross_esw_scheduling(esw, parent, extack); + if (err) + return err; =20 if (!vport->qos.sched_node && parent) { enum sched_node_type type; --=20 2.31.1 From nobody Tue Dec 2 00:46:21 2025 Received: from SJ2PR03CU001.outbound.protection.outlook.com (mail-westusazon11012062.outbound.protection.outlook.com [52.101.43.62]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CF3B02C0273; Sun, 23 Nov 2025 07:24:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.43.62 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763882692; cv=fail; b=JS5HSwA1t4/98LDFX1FG/DcQ6WBupnQEkUcPGpqH8DcJbwBK30+d5TX07SlCJFE8wYE/QjSzO8COH+sFuUvvLZcq/Evsa54J3b4J7SzNwHQP+AMx/qFNY6EFTQvA7LTTTZnxoVeeyN+/xhqWFfSIhF4aRvr04n9w8p5rUPgyCx0= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763882692; c=relaxed/simple; bh=eCQG3S/yOds8JQUOHWixmpPqBLMdmU/S/TtH7v9dU+k=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=DpYHTeNqngGQdywRQ69spxmYg7H6STjNVVuA/lWHCmD2dPjLB9JpOEoRQX2bOry3CYj9sZRNGo731sPljehxWzMoXJskrdCdIACOB6zZdDHm+IR2925e56/V2LRi0MxLzL/1oDNvEeFuSVAq+7hHbccqI+B23ah7GN3tWjYQWm0= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=HOtFb6/m; arc=fail smtp.client-ip=52.101.43.62 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="HOtFb6/m" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=DJE9RrlZPVLnLxHi0alk4tVLwAczBXfxMha6gOngayXURP4jZlURTXoRuM1KN4++zntVXc+emZE3C7F8mANbPOcrD9LeGKZXsuBN5p1lCKyY6M0fcKWWdxtVbC2KYLBgTF1c5Lq9e1QwYK8XS4nGRsywFmUHpTp/FMSMMsAzcivw2r/x42Owu65Hp4abHpKzUOD1BS7nNvbXxwp6HTkgXk95qd86qClvmS4xHvOjPAlXofV/+27UDYgs4OJFjpof8i1VmK0H63/mdqFN+a5Yt+/73Xh9sVgYK8+3to5UwplNEHFprCjwW3UxIbr7zm1/xfcj1m9/kZixqz9/SQ1UAA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=/pAm2wQVgo0BwkiOeplsjOGdgWjn/yXUgEfaNOjFTP0=; b=g0H0yltoBc35ke2Q1zAadmtzqzp/Q0gP/+2tpz0dmnifJobjdO15vUc3PM90CXY6DpppfOACMQqht5UtEnkl173iGrUbNV6TRSzSjPZBZ9Lk5m14ld7OCTyGAYr3u0jShoJ+9oJfVvYciIu25HcTP09BIIHrFRrchgR5WFA7ojGcvUb1sJdBMRga1B11BPWJPUub580x6z0HGx99bPa+HXLDc7PxERYdGi2AsUCQxQ3gZSoEY2ir6gd2FEBzmLRrTpOCziI6YcAenINuyyGkh6b8w+rZnUFI+ir34f0KFpfcKjaRh36mtjn9dTC8+K5gWPgCgSLK5Ybrsn9rLNN4Fg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=google.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=/pAm2wQVgo0BwkiOeplsjOGdgWjn/yXUgEfaNOjFTP0=; b=HOtFb6/mWe/SZz81xG4nRF+VGSmw4JaaMtpHyjuzuEa82zKLKUctV63ClMvqyxHOo4r/mz3a78GzlyI5VmyB1xrWevLwH+EyC5KCQSL6EGsaGU8uftCeTBpop0O7MDG/OM4iFiqTZqwb8jKXTCZJMRxjauI3hLxFWn/l3Z0G2n37h3n0i+PJPEpOnIuun5mFybJVRWj1H3hNDGPBLZM3CuXkDJQJrqOPULlpAgRbL5UksatVg6j4WISiEM9+bCdLKfLTqnRld+gu9veI4m9idsqafuaCyFSCNeurNfwNb9Pr9ZgWnbdniv9ki34s2BTTwSplIuvdfJ6aNw1UGs+g1A== Received: from SN6PR08CA0034.namprd08.prod.outlook.com (2603:10b6:805:66::47) by DM4PR12MB6109.namprd12.prod.outlook.com (2603:10b6:8:ae::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9343.11; Sun, 23 Nov 2025 07:24:41 +0000 Received: from SN1PEPF000397B1.namprd05.prod.outlook.com (2603:10b6:805:66:cafe::69) by SN6PR08CA0034.outlook.office365.com (2603:10b6:805:66::47) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9343.14 via Frontend Transport; Sun, 23 Nov 2025 07:24:43 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by SN1PEPF000397B1.mail.protection.outlook.com (10.167.248.55) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9366.7 via Frontend Transport; Sun, 23 Nov 2025 07:24:40 +0000 Received: from rnnvmail205.nvidia.com (10.129.68.10) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Sat, 22 Nov 2025 23:24:32 -0800 Received: from rnnvmail201.nvidia.com (10.129.68.8) by rnnvmail205.nvidia.com (10.129.68.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Sat, 22 Nov 2025 23:24:32 -0800 Received: from vdi.nvidia.com (10.127.8.10) by mail.nvidia.com (10.129.68.8) with Microsoft SMTP Server id 15.2.2562.20 via Frontend Transport; Sat, 22 Nov 2025 23:24:26 -0800 From: Tariq Toukan To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Donald Hunter , Jiri Pirko , Jonathan Corbet , Saeed Mahameed , "Leon Romanovsky" , Tariq Toukan , Mark Bloch , , , , , Gal Pressman , Moshe Shemesh , Carolina Jubran , Cosmin Ratiu , Jiri Pirko Subject: [PATCH net-next V2 13/14] net/mlx5: qos: Enable cross-device scheduling Date: Sun, 23 Nov 2025 09:22:59 +0200 Message-ID: <1763882580-1295213-14-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1763882580-1295213-1-git-send-email-tariqt@nvidia.com> References: <1763882580-1295213-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000397B1:EE_|DM4PR12MB6109:EE_ X-MS-Office365-Filtering-Correlation-Id: fe8a2432-fd67-422b-950a-08de2a615dfe X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|36860700013|376014|7416014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?4d+aZZeb1DAyK7GeIbXxrmt0cR12662kDMEcQOwcF+c1DjYhPPaOwTtSe0f4?= =?us-ascii?Q?JKgb1/HJGmVikyRNr3Z2WlcG4umiLid/L0Hs7bLm4RUA2OqqEvLSP8TNe8T1?= =?us-ascii?Q?GX4mrZ8WNNBmGO25/w75LmlVHcT8E5TViWL95VUA3nGi1BpxYN7kp5R5uOem?= =?us-ascii?Q?7OGeq9ss80XlN5tvMVmN5wjEPYd3rQxfKHVQjEUxDB2BsTF5HBQGni9qSsKS?= =?us-ascii?Q?sjN637uXUNt6fthUUmh5PdPKP3fwZuZiQjJbQnBd0cxDEfW/xOYCSXEthZdZ?= =?us-ascii?Q?DZhtuFvOUw2xbXDzBH2Ye04GFdCMJbb6g6RyjDabiI2+lcj0eYCdlkhqb4Qk?= =?us-ascii?Q?2feIasYkZKe49V16VOdtvy6Ygue386p4qeXGwvF8XpC0x8N0zw8dC8Rvwidw?= =?us-ascii?Q?/l98mSzmQZdRnshHErGPcvKR/hTJcGUnYgxgCJahkLMTe6BYbmtgPpCPiyW1?= =?us-ascii?Q?ijSaHZSPEMaSkUVeGlYPlCfMCh+u6Trav0UirRTf6nl7Xe2LNWmc09zfbEwl?= =?us-ascii?Q?zdnNommyBPwL372nhPDS8vPZjyUjcxG4r+y43n+rnIFKN9OSlgJd2US6AaE4?= =?us-ascii?Q?wF3NGbaDNeNA9ClwhoZLSvlmKYShORBCbsB7/l+EeCqVhQ3b+IoOBWCz4G1k?= =?us-ascii?Q?YbSxCceXMsP3KkRHHVtJc2H7Cs2PVe/uaDN6Vo58zlXk43VFmRTW4Ht4bmLL?= =?us-ascii?Q?VzYPW6qxFHfOq4RoyNRvxREMswqBUz+WeePrgK64zzmTz86UuN51iNRF9Wyo?= =?us-ascii?Q?pZyaUncwfyquSVvZ/RCSStMWywAKke2lwJT1Wt8PI0DAVCQAYFHxWTlPqKCz?= =?us-ascii?Q?WnnutG11npCtvGdL56LZGc3zibAl+u+w2T2vwl1/nm8gwwEIWF/edBE0FxKR?= =?us-ascii?Q?bWK/H+jsmQ6wsYb9d8DSoZCu7EshT5+L26QM7SwQ5Sd5rdWm21QY4wXepaBr?= =?us-ascii?Q?DrHY1M35KVFQ3ssWZMW+fDPLZRwbEzwB9eVlj66yMDu4a//tn181FlCE4xdT?= =?us-ascii?Q?+4d6jLyRer7cE07eUleBO5wmSg7azpO0Q55zUHj70I8dvFfC+K07/ih5JmuU?= =?us-ascii?Q?Hs1cRcLOrrnrDYmnxdNFIFnethQf8kq63l/JIBWga1K+63KIHoeaOzpT7b7o?= =?us-ascii?Q?8NAWfk0mBgXi9HnQvRdg0StsOKvrUC7U2wZ/6/ujOPNA9bBdQBwlF3NM69iQ?= =?us-ascii?Q?x8gx5W5f/cEG6gx4ysySd+4I1FcqRHtpVFRPRn3JC5Y8SSr5srIPL/xPiEN8?= =?us-ascii?Q?IOTVtV5RWTTbEbTDzk7UN8QgTIn9WaN3+L5p2Vi338DWBu6ekS4fcsCObTOW?= =?us-ascii?Q?vTlm6Q35rH6f8EMGMSDuJ5G0ycAZTy0gjxUstic9E0mIaQceCjkRVBuniGVE?= =?us-ascii?Q?7ZERq0G1Yv5yy/g/zEamjRl5UqX50aRX1CUIHTTdJ6jGKga4yUDxtN/PXv7Q?= =?us-ascii?Q?X6TP4SGG6tNSWuA8n9fkN0XwowaeDeJ4aIjqPQXoIagEO2LnyUdZZ5oYFWKa?= =?us-ascii?Q?lFRLazQq4sBgotJsuzCMJB6M5Vz9gaW281C4vLA3MajtlPnalv5p+jHkM46A?= =?us-ascii?Q?uNFimKewg1N1mdEI174=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(36860700013)(376014)(7416014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Nov 2025 07:24:40.8470 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fe8a2432-fd67-422b-950a-08de2a615dfe X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000397B1.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6109 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Cosmin Ratiu Enable the new devlink feature. All rate nodes will be stored in the shared device, when available. The shared instance lock will additionally be acquired by all rate manipulation code to protect against concurrent execution across different functions of the same physical device. Signed-off-by: Cosmin Ratiu Reviewed-by: Carolina Jubran Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/devlink.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/devlink.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/devlink.c index 887adf4807d1..343fb3c52fce 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/devlink.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/devlink.c @@ -380,6 +380,7 @@ static const struct devlink_ops mlx5_devlink_ops =3D { .rate_node_del =3D mlx5_esw_devlink_rate_node_del, .rate_leaf_parent_set =3D mlx5_esw_devlink_rate_leaf_parent_set, .rate_node_parent_set =3D mlx5_esw_devlink_rate_node_parent_set, + .supported_cross_device_rate_nodes =3D true, #endif #ifdef CONFIG_MLX5_SF_MANAGER .port_new =3D mlx5_devlink_sf_port_new, --=20 2.31.1 From nobody Tue Dec 2 00:46:21 2025 Received: from BYAPR05CU005.outbound.protection.outlook.com (mail-westusazon11010053.outbound.protection.outlook.com [52.101.85.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 21B372D7DE1; Sun, 23 Nov 2025 07:24:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.85.53 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763882694; cv=fail; b=GcBrShM5YEzroy27NnnUk+gtMzBw26PPKI05JIBIFtuytkM4q4xTLgkzRgLYmScRxyVWkbZSewxEcVHu0cAlP2NMDVXb6M6WV1bZfHsX8FLexaCTxIuO2VoD45peoVGdKNBR35tGsddNiKbYSlrZGVGkontAk/Mk5Bn6mQIwODc= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763882694; c=relaxed/simple; bh=akdES0X+iKGn4rltOupcPwz7Jf/mU/JyeskXjIgx3P4=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=eRdf8yaN9ky/k55qF0aFMLJ+YDJthO3qZHFiQmqWylkPzjSDEG0X+KTM/gmv5D6D/v+kC+7hHPln4D3j4Bnpr1uWCJyBO1DEVcJicrPic8TP8l9pJQb4oE1OgDWxLlwHVtuWhX2/QLcAwhtRSpXxbxWhxKWp9t4U02s+WUbzZlo= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=SDse8PdG; arc=fail smtp.client-ip=52.101.85.53 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="SDse8PdG" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=k4wyaR4b6RXQaVd4skX/i3ocXQDdyUmOevS11VJmOias4+BKobZisjqVC9/D8ki05i1W2HZdZopjWfcmO/wkH+oZ7QBEijsPyjcyhQTeY6mQgeVM0hsTFY7bQv/I0MFtzX5VUtCEzf7KwHjzt/RjFMFEF1OZbzVlq4kHz6u2dnCiZsMroJQEHzNHXNI2iKe/hJyjvKor498tLO1TY7KJ1StQDMUIgNi3CM2YimNp1iQPp9gsXYoS4WH+rUHtrwmG/qS1s/g8R5fKBaMHDDWPivtz3+QqVTPfqfXVJOS+JEqU54Nqo29yhoJbMqXluCVfbygxaT3FwyyRY1HTUL8Z1g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=CTEHFT1VQ+M5GMuB3KgAYIkobtSsghZZ7vtK9OdaRq4=; b=En9rH51cN3BOvyDJvcKFxQbCCtiyC4kUrhUAnDb4RKhedEENDiUY4FeT912OTejcynMEL5yP+PHqMwSqVf7vikCru+Nm5U79JqCFxj4/Hmsng9q/EBhmVjvNThUlG9pEBBB3hndTjjvJl0JWNUAWbotPd9nNkpfpHBSPU1ihkHsXP7W2MxgvcyhiquMJdMC3uPcYWYxEEvTQxPkQPXjaOmmSpPl6DVpIWvRjuq0JK/a+a9OSZReWLVTQHHMepOj6wN1MCuN7hxRTul+M/InmQhmHiaI1jRQAVzxYBAFo1n1/ru0HEo3zb8+hLOwXC8wgbVwbPm28sebpaUkkkmoKGA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=google.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=CTEHFT1VQ+M5GMuB3KgAYIkobtSsghZZ7vtK9OdaRq4=; b=SDse8PdGEVr0Y/KUwfcyLfXq7mnmZSnCbB3t7ZLt9q53w6w5V/UZIjzV9anZbnrmVVwvDDMV4VhcFlG3y6Ng0jEU/QRJyLwBw2bdZSsryghAqWgdVvfbz+HKDtNgOZZrKEbrC4ANuIIcizs/2JNKoMvZRVOD0jVflVzrA1n8z0PHtloi1xkwS7NMhzx5KcgIqTgOVVpxL40mceY6CYiWLRNwoz6Adj9xuK/4ZuxlwCySCwmOCerDJF+07+OaOS/TXb+m4haWdtyHhg/BVu7ZME1bDo2I7wLgPyGlFqWQqH5Tt+N2LVUz8/0n7Jsf113v8nhrtP98wdrmVDI+6WIFCA== Received: from SA9PR11CA0001.namprd11.prod.outlook.com (2603:10b6:806:6e::6) by LV8PR12MB9333.namprd12.prod.outlook.com (2603:10b6:408:1fa::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9343.15; Sun, 23 Nov 2025 07:24:48 +0000 Received: from SN1PEPF000397B2.namprd05.prod.outlook.com (2603:10b6:806:6e:cafe::42) by SA9PR11CA0001.outlook.office365.com (2603:10b6:806:6e::6) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9343.15 via Frontend Transport; Sun, 23 Nov 2025 07:24:48 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by SN1PEPF000397B2.mail.protection.outlook.com (10.167.248.56) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9366.7 via Frontend Transport; Sun, 23 Nov 2025 07:24:48 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Sat, 22 Nov 2025 23:24:39 -0800 Received: from rnnvmail201.nvidia.com (10.129.68.8) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Sat, 22 Nov 2025 23:24:38 -0800 Received: from vdi.nvidia.com (10.127.8.10) by mail.nvidia.com (10.129.68.8) with Microsoft SMTP Server id 15.2.2562.20 via Frontend Transport; Sat, 22 Nov 2025 23:24:32 -0800 From: Tariq Toukan To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Donald Hunter , Jiri Pirko , Jonathan Corbet , Saeed Mahameed , "Leon Romanovsky" , Tariq Toukan , Mark Bloch , , , , , Gal Pressman , Moshe Shemesh , Carolina Jubran , Cosmin Ratiu , Jiri Pirko Subject: [PATCH net-next V2 14/14] net/mlx5: Document devlink rates Date: Sun, 23 Nov 2025 09:23:00 +0200 Message-ID: <1763882580-1295213-15-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1763882580-1295213-1-git-send-email-tariqt@nvidia.com> References: <1763882580-1295213-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000397B2:EE_|LV8PR12MB9333:EE_ X-MS-Office365-Filtering-Correlation-Id: 5c57bc89-6e17-4bc6-60e3-08de2a616268 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|82310400026|1800799024|7416014|376014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?uqQUtUSgk+0jaaPaN9/rXpgKx3aFHkGMoqlq9gOyjMi1ASwwI4oEWkBLIyvY?= =?us-ascii?Q?uU+n1edqbWTD19bBFfHaB1wqQRGAx51D/e7SHhdoN0jENWgW3R8HLOz64pwb?= =?us-ascii?Q?QftRiG7fu05S1eFeeZIuLuN6QFxsj6gzF10vYkdBTRPtf4ljvTdcWXu8e5WE?= =?us-ascii?Q?B2TTkqf4EN6g921rlYFajNM7p035L/JjfEIZCcpYPvUJ/HoeE4qfH51OMGiO?= =?us-ascii?Q?4ZabWJp7pOSFyGdGpgOsQMFqjc733lfUqJeEMFhFqCup+1ll7DsUpboLGiJA?= =?us-ascii?Q?A5lWQrhKLIqv4Qd2iDwN9n3QWhpzoogR+iJlbDeAmt0My0c1Q5DR36BkSNoV?= =?us-ascii?Q?/LkrhvE8uWi1/vOHzShg+KujkvcTrG8aF3bAPBmwsP6bPm7thJSCJgeIPdJH?= =?us-ascii?Q?JaS3cKoxtsocayfnnIXdRxFDQBHFNseJQRbKvjq13opjLjcPms6alLFfnb7D?= =?us-ascii?Q?HksUEq/D6HMOKXy8ifIKc2aYvLbyWb/IRjtWyBryg1E3mzqtmfo4hY0fEv24?= =?us-ascii?Q?W99wu7a7UX4qeviarf+KM09ax72k6nI8hUXU3sQx5TmNTKLCjnYOpAGIZA6S?= =?us-ascii?Q?c6kkdmBkWiis0N+XzLCFNw6t+Ip3A4IqvNX4p4rJA8HT6rHzc1PJum4OwBuh?= =?us-ascii?Q?cbnpY9RdP8mvz9bEKmhkBVp58cEtZB7vfepxmNWoYyo8GMlSpPj3L2/nvypz?= =?us-ascii?Q?DGEaAI86SUJoZQ9HPvczwLGtpNkLhuIG+lAuo0g4/c2FB8K2l7UBYDTRCUfI?= =?us-ascii?Q?W2vw1YYEdIWCmO3wl9TRWumvZv2Z8JpxjX+JAdfmWTNhW1GqwXlMV8BUAPXk?= =?us-ascii?Q?/QQDXJF/UEreNRFLcyv4wjsDsMRY/n/IIm/HIip5G9IpUl1OyPRuVp0sFzCT?= =?us-ascii?Q?lRFwQB9iONm1eKxzwyaAO5xaeg0tq7dtP1Topd9trmZTHKQ3oKqmj6PJEpuJ?= =?us-ascii?Q?Qol6Jgjwij4VxkKlBHmg4nolbC51pHx6wj8P2y8P1cyVRTp6frWfytbm7vXj?= =?us-ascii?Q?lPnXYCxWMCLdUhaKwCHEeVOkXCVsAivezVsaMxwNIpjkfsG328fbi0aeOA/m?= =?us-ascii?Q?0FFeLVxj4vjqErXOfeIHgpI89Q86lS0SnU+9xngu8Or/ALxLQ2DBVYQB+OOx?= =?us-ascii?Q?LsuuIHrO4vdkhHiam8ROeOCtEQ5UD5wdeVcv9eriy6LsCibrIP5ntke4+mZN?= =?us-ascii?Q?TaT7Vr8VuTJRz/vfKN61c2Nt6oBzxX1b2kPfL2rlB7OUzTgftJ4GxzV5JeMz?= =?us-ascii?Q?BbxLJUQK38vrLKuGGLimVA+kPLtGcCnr8pKOlVUb2ihTqe8ZRitSWAUIQI8m?= =?us-ascii?Q?dxCoNq3A/6LEvvH9VijPj0GJImNsDRDUBY433tMRTWbhcQAPqntRQuz5ErdY?= =?us-ascii?Q?SdljXUUcPqAkcRFv43PyRPor1YEW53YvYDJ66+Yomkr4SDFdWE9iCMVsylfz?= =?us-ascii?Q?CyD7ednZpSdNEhMfRZRp6gcCPaUxDG+W0y5MW0TKgptxOs5bKX6aKoBa54S6?= =?us-ascii?Q?/P8snJfac5hlN09FQ2I1PSHjnyP8h88EYwvXUrnqU6nraX3iG/3qMnIby1DD?= =?us-ascii?Q?jzDdKbKKrjCPBJR6rB4=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(82310400026)(1800799024)(7416014)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Nov 2025 07:24:48.2764 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5c57bc89-6e17-4bc6-60e3-08de2a616268 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000397B2.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV8PR12MB9333 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Cosmin Ratiu It seems rates were not documented in the mlx5-specific file, so add examples on how to limit VFs and groups and also provide an example of the intended way to achieve cross-esw scheduling. Signed-off-by: Cosmin Ratiu Reviewed-by: Carolina Jubran Signed-off-by: Tariq Toukan --- Documentation/networking/devlink/mlx5.rst | 33 +++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/Documentation/networking/devlink/mlx5.rst b/Documentation/netw= orking/devlink/mlx5.rst index 4bba4d780a4a..62c4d7bf0877 100644 --- a/Documentation/networking/devlink/mlx5.rst +++ b/Documentation/networking/devlink/mlx5.rst @@ -419,3 +419,36 @@ User commands examples: =20 .. note:: This command can run over all interfaces such as PF/VF and representor = ports. + +Rates +=3D=3D=3D=3D=3D + +mlx5 devices can limit transmission of individual VFs or a group of them v= ia +the devlink-rate API in switchdev mode. + +User commands examples: + +- Print the existing rates:: + + $ devlink port function rate show + +- Set a max tx limit on traffic from VF0:: + + $ devlink port function rate set pci/0000:82:00.0/1 tx_max 10Gbit + +- Create a rate group with a max tx limit and adding two VFs to it:: + + $ devlink port function rate add pci/0000:82:00.0/group1 tx_max 10Gbit + $ devlink port function rate set pci/0000:82:00.0/1 parent group1 + $ devlink port function rate set pci/0000:82:00.0/2 parent group1 + +- Same scenario, with a min guarantee of 20% of the bandwidth for the firs= t VFs:: + + $ devlink port function rate add pci/0000:82:00.0/group1 tx_max 10Gbit + $ devlink port function rate set pci/0000:82:00.0/1 parent group1 tx_s= hare 2Gbit + $ devlink port function rate set pci/0000:82:00.0/2 parent group1 + +- Cross-device scheduling:: + + $ devlink port function rate add pci/0000:82:00.0/group1 tx_max 10Gbit + $ devlink port function rate set pci/0000:82:00.1/32769 parent pci/000= 0:82:00.0/group1 --=20 2.31.1