From nobody Tue Dec 2 02:52:38 2025 Received: from SN4PR2101CU001.outbound.protection.outlook.com (mail-southcentralusazon11012018.outbound.protection.outlook.com [40.93.195.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 07919325717; Mon, 17 Nov 2025 21:43:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.93.195.18 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763415789; cv=fail; b=KttenMSt6sICyfp3dfOCSf+qALfmoIwjzOPjDI4nLrMjFLxJNpUEYPl18Ctf+PSs197kMfvTD7NYqzIQXFP4NvHXTn+NpLKSdS6Ffb9tU7T1SCemeloEuskdMPDbvB9zPmaAYBTPTLUZB+IoL7+ksJCeC+gYTuSFLpmvmxZLZhM= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763415789; c=relaxed/simple; bh=mOqHjlwl7XO7g5OXvr6Vs1Q8nqDlt5tP8TI5NG0KZcw=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=pfw+xakHVEGE9l3CN4KDQD24dP4jZceOxW/O+Kd2vBDEf7EWa+hGqUGaCqZwY6eGuGlE1nJrR/qFY7NvoMRZk/kVVtIbEPLdH6S/xSKF3dmIkbCC3o8A1f0WtS7EP/enAzWFSUGCqOQkTSSXXSDjDxAyU6MHxDEXNfNJRGhwUwQ= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=nIysa2DA; arc=fail smtp.client-ip=40.93.195.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="nIysa2DA" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=lcCMVCxXUrk+u7rwyrJcAqaD7MTOWrCeWqUCh4jokuqra0RlGPKV/sUK5pRajl1Yz+s6x5rnrBsFVqOR17iCvvTiFJT0mHWqLO2uF0suNaAZKeM2v84SvEBwzfLci5/8Q5ZML8Lw8XtPB2JbO+NidaEH93gJkYFKbx/bAdy01h4U9PWmG43OvMa17IjHiTmtGd0f/9riBlAF4I0REZV52PpH/+5zGKq3GNOGvhZ8lTLmJ6hmY9BWQS1AvLHX6icg+501V4DeYfdlwhvRfLKdXJLAvXNv0U19s/ap38Bh5r6uF5U4yLOGalauXe4vs0A+mmnr1S+9plTlPFPfGA9SIw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=QtxXQLkTB0Rf0inSpjertTEfhB8JvQ+yLRMQ+XCD5Ek=; b=hjDevVU+hRyqarYF2cKh/W4jbskXMoGA0b9DCtsuNGsXAwtYsdYecP2UbBdojYsLGlGtQn+Y0Ntqtlt4pyt48vv8nZdtylrL6EEFhm+O/enldxqdmFdyb0NrdJaIJOXpoCQ5JKXZfdiMIsiq3x/5GXFeMUAHv6cC+llmqIO6/l4yiRWRXErs4Qd0F6kupFHmqI7R4TwLghUp880ORPmvenazvG8zd8oomReNKj1ruczYSvGfp3uCaUq8AMlj3Yy04qj42VUzmgJCyAHFHGE/EW3Kg8yXErJpK8C+I6x4WDO6Rqq8LURBG+6TMRVfJor8Di6n08lZNVM0bj0wE7/zvQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=google.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=QtxXQLkTB0Rf0inSpjertTEfhB8JvQ+yLRMQ+XCD5Ek=; b=nIysa2DA8DjV40985mjp4lspK79RNT+UG5BaWJAhdek4mC3jp2vpPruyHWMbG0X3KlPvZk39kp88pOfP9VYBS66qsiP/JTfsbUqNzJzGMATlPO0N6SbYk9Utq3R9r/VVePYTNC0GEOG3yU6W7oQi9c3S0SHiIPA5pq8k+OKjKzm0xxocWjnfPD2eb+/JuJb/3Dl9ldX1Ln5DSy7Ab2rDLkh93GaAAAIl/R/zKU4ce05R8X9LZ8cf8ExOHTPJB4KI83jWk/rDwHl/Mki8vSXDxlgnuDzTCr/i6Ej7OOrjDI1R5R0zdwOLHmoP+8TxvN/m9kL68PY37bskfda/9ZKzXg== Received: from SJ0PR05CA0143.namprd05.prod.outlook.com (2603:10b6:a03:33d::28) by MN2PR12MB4144.namprd12.prod.outlook.com (2603:10b6:208:15f::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9320.22; Mon, 17 Nov 2025 21:43:00 +0000 Received: from SJ1PEPF00001CEA.namprd03.prod.outlook.com (2603:10b6:a03:33d:cafe::fb) by SJ0PR05CA0143.outlook.office365.com (2603:10b6:a03:33d::28) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9343.10 via Frontend Transport; Mon, 17 Nov 2025 21:42:55 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by SJ1PEPF00001CEA.mail.protection.outlook.com (10.167.242.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9343.9 via Frontend Transport; Mon, 17 Nov 2025 21:42:58 +0000 Received: from rnnvmail204.nvidia.com (10.129.68.6) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Mon, 17 Nov 2025 13:42:36 -0800 Received: from rnnvmail201.nvidia.com (10.129.68.8) by rnnvmail204.nvidia.com (10.129.68.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Mon, 17 Nov 2025 13:42:35 -0800 Received: from vdi.nvidia.com (10.127.8.10) by mail.nvidia.com (10.129.68.8) with Microsoft SMTP Server id 15.2.2562.20 via Frontend Transport; Mon, 17 Nov 2025 13:42:31 -0800 From: Tariq Toukan To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , "Richard Cochran" , , , , Gal Pressman , Moshe Shemesh , Dragos Tatulea , Matthew W Carlis Subject: [PATCH net-next 1/5] net/mlx5: Refactor EEPROM query error handling to return status separately Date: Mon, 17 Nov 2025 23:42:05 +0200 Message-ID: <1763415729-1238421-2-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1763415729-1238421-1-git-send-email-tariqt@nvidia.com> References: <1763415729-1238421-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00001CEA:EE_|MN2PR12MB4144:EE_ X-MS-Office365-Filtering-Correlation-Id: 6c0d805b-673a-4ccf-dcd6-08de26224684 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|1800799024|82310400026|36860700013|13003099007; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?r4iarcYX575NbToy3qX5GkgnVs4smoCZgJ9P7kcV0I0FGfEvcQZVH0JsYDSE?= =?us-ascii?Q?0m8zqoBIvuY537CUTG9HaaOlf2dSx9f+z9XYZ2w2ygEme5wrvWeYdcASayiK?= =?us-ascii?Q?VUJeY7lS07AnZdzoXjoQas46ALXoxjnj3390Xjgg3r0zafIDTD7eC/tg7BC/?= =?us-ascii?Q?3VWX4IWoMuq38DUTWh7DnCLVlny+yS6A/MchJi0Bx04K0zYOZKfI1W3pFE3H?= =?us-ascii?Q?eDHAGewqsYCNuTR/Uen6vInnqtlC4lzKjsDPx0ch8N8316rl+rkYiGQ4eOtX?= =?us-ascii?Q?kRzo3hVGvPvZBbgMGBnGtEBTroCS5W0VkGR00ZgEnrvldZQCRQkXBmF7AMlf?= =?us-ascii?Q?ricLT97FAqP25xc6FmJJ1WsjUQjV0xHw+KfgJp5rzEUR5isPfjAMSl1af8Aw?= =?us-ascii?Q?fkT6onwzXCmA/jh6azLRU2YrXr0R36K/9x/u0/c/6+LBHZ6hmeIAflpsqWH9?= =?us-ascii?Q?6uyICgnYSDUFP6Gx6UbrkFL3hlR2c6ru0i9L/fi6OmRhjOprC0T3T2e+3aM/?= =?us-ascii?Q?XqkKaEcwzxauAMlxSEthjktNIkgvWIkLX3e1vEeQ2WBtD+SuyAgQDEUjDwLa?= =?us-ascii?Q?IUILfik4t8i2xm0K9RGZ1V3mK4GNzXdpxWBJAUZoJeoxJzTzWlBkDrEbQhg/?= =?us-ascii?Q?55h5GwEqr+IMuvmoYYqnKOxCnfXDMMhzf2UhW9XlthWBBEgt1e8OGwtxhfrh?= =?us-ascii?Q?AZnYuG1ogNcR2AgV9FWZBmA1vkriDPyGgMzjiE18AmNEWAOQQBCZaG9gceXS?= =?us-ascii?Q?12duf7i3eH6HFo5MCwrx+vip+HZCm5WU1Zlp3jITSQ0vhKCg1skRFbux6O1Q?= =?us-ascii?Q?oNg72P0Ydzknpj7y1sQuJoTaeAvN8wSigHPBo0VfW+SuZgHGfa2Cd2cQcyRf?= =?us-ascii?Q?4dtFzqaW7grxywNfS6pmCrRVcU7X1DlqmQlrn5IcoAtFRx9LiAYQfxSVhRLZ?= =?us-ascii?Q?6tG8aiDKtRVucEXwwZ4BSuzuEkUsloPH4s9zc+k1niG83di6/KMsNM/8dG4r?= =?us-ascii?Q?mEfl3cR/Ui0ySGYHHPRnsFTplw4S/T/7SqZttIGaezkhsuHWt7oNG0xLXDbt?= =?us-ascii?Q?WPyLmEr5IvpTxx11DqdJHQ7K85YG5l7Kh54aJtvdnk+4CeX26zzonyLVlsFn?= =?us-ascii?Q?wDEsEwG1h/ipaKdCXJgaP+Xxs2IqsXkR9v4LZ3LMvSMUQ1yPet8f2777IzpC?= =?us-ascii?Q?hZzXhfdXLLXZnbu2qP0DhAAqj6/Gw7scESJv3B1QhUxE8qzrm0f3gx27aqyn?= =?us-ascii?Q?CF0tPxRaTHmOcbmSKlVCKq9/pE1TxjNsWTSjDGNUavh/RVpZ2ex9XydcCm1u?= =?us-ascii?Q?6PNf5ivQH3Sx7RyHj7GpIJ1Wzp+s5LbHT9OqJ8Hx2h7dABF+XSf8E/Rh7GEM?= =?us-ascii?Q?h0Wlm09iHUjNY+37TAqJT6i7CKIWyJ7q8u6Vl6vsGwbiwl/Bxuhm64fPUNuD?= =?us-ascii?Q?yhjIIuu7/IwigxAaW1qZeuUFj9AgEw5m1JnHWIdOqMagzMES9e6RUnPOFLac?= =?us-ascii?Q?gGt+32B9/sDkjFA807ZLWiZEqBB77hw/RPqPM0N9u4rvPGaPg27uIsmQgNei?= =?us-ascii?Q?vrSnnbTc/AMXjZltDLI=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(7416014)(376014)(1800799024)(82310400026)(36860700013)(13003099007);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Nov 2025 21:42:58.6771 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6c0d805b-673a-4ccf-dcd6-08de26224684 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CEA.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4144 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Gal Pressman Matthew and Jakub reported [1] issues where inventory automation tools are calling EEPROM query repeatedly on a port that doesn't have an SFP connected, resulting in millions of error prints. Move MCIA register status extraction from the query functions to the callers, allowing use of extack reporting instead of a dmesg print when using the netlink API. [1] https://lore.kernel.org/netdev/20251028194011.39877-1-mattc@purestorage= .com/ Cc: Matthew W Carlis Cc: Jakub Kicinski Signed-off-by: Gal Pressman Reviewed-by: Jianbo Liu Signed-off-by: Tariq Toukan --- .../ethernet/mellanox/mlx5/core/en_ethtool.c | 19 +++++----- .../ethernet/mellanox/mlx5/core/mlx5_core.h | 4 +-- .../net/ethernet/mellanox/mlx5/core/port.c | 35 +++++++++---------- 3 files changed, 30 insertions(+), 28 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c b/drivers= /net/ethernet/mellanox/mlx5/core/en_ethtool.c index 01b8f05a23db..7cf2ec8543f6 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c @@ -2027,7 +2027,7 @@ static int mlx5e_get_module_info(struct net_device *n= etdev, int size_read =3D 0; u8 data[4] =3D {0}; =20 - size_read =3D mlx5_query_module_eeprom(dev, 0, 2, data); + size_read =3D mlx5_query_module_eeprom(dev, 0, 2, data, NULL); if (size_read < 2) return -EIO; =20 @@ -2069,6 +2069,7 @@ static int mlx5e_get_module_eeprom(struct net_device = *netdev, struct mlx5_core_dev *mdev =3D priv->mdev; int offset =3D ee->offset; int size_read; + u8 status =3D 0; int i =3D 0; =20 if (!ee->len) @@ -2078,15 +2079,15 @@ static int mlx5e_get_module_eeprom(struct net_devic= e *netdev, =20 while (i < ee->len) { size_read =3D mlx5_query_module_eeprom(mdev, offset, ee->len - i, - data + i); - + data + i, &status); if (!size_read) /* Done reading */ return 0; =20 if (size_read < 0) { - netdev_err(priv->netdev, "%s: mlx5_query_eeprom failed:0x%x\n", - __func__, size_read); + netdev_err(netdev, + "%s: mlx5_query_eeprom failed:0x%x, status %u\n", + __func__, size_read, status); return size_read; } =20 @@ -2106,6 +2107,7 @@ static int mlx5e_get_module_eeprom_by_page(struct net= _device *netdev, struct mlx5_core_dev *mdev =3D priv->mdev; u8 *data =3D page_data->data; int size_read; + u8 status =3D 0; int i =3D 0; =20 if (!page_data->length) @@ -2119,7 +2121,8 @@ static int mlx5e_get_module_eeprom_by_page(struct net= _device *netdev, query.page =3D page_data->page; while (i < page_data->length) { query.size =3D page_data->length - i; - size_read =3D mlx5_query_module_eeprom_by_page(mdev, &query, data + i); + size_read =3D mlx5_query_module_eeprom_by_page(mdev, &query, + data + i, &status); =20 /* Done reading, return how many bytes was read */ if (!size_read) @@ -2128,8 +2131,8 @@ static int mlx5e_get_module_eeprom_by_page(struct net= _device *netdev, if (size_read < 0) { NL_SET_ERR_MSG_FMT_MOD( extack, - "Query module eeprom by page failed, read %u bytes, err %d", - i, size_read); + "Query module eeprom by page failed, read %u bytes, err %d, status %u", + i, size_read, status); return size_read; } =20 diff --git a/drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h b/drivers/= net/ethernet/mellanox/mlx5/core/mlx5_core.h index acef7d0ffa09..cfebc110c02f 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h @@ -357,11 +357,11 @@ int mlx5_set_port_fcs(struct mlx5_core_dev *mdev, u8 = enable); void mlx5_query_port_fcs(struct mlx5_core_dev *mdev, bool *supported, bool *enabled); int mlx5_query_module_eeprom(struct mlx5_core_dev *dev, - u16 offset, u16 size, u8 *data); + u16 offset, u16 size, u8 *data, u8 *status); int mlx5_query_module_eeprom_by_page(struct mlx5_core_dev *dev, struct mlx5_module_eeprom_query_params *params, - u8 *data); + u8 *data, u8 *status); =20 int mlx5_query_port_dcbx_param(struct mlx5_core_dev *mdev, u32 *out); int mlx5_set_port_dcbx_param(struct mlx5_core_dev *mdev, u32 *in); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/port.c b/drivers/net/e= thernet/mellanox/mlx5/core/port.c index aa9f2b0a77d3..e4b1dfafb41f 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/port.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/port.c @@ -289,11 +289,11 @@ int mlx5_query_module_num(struct mlx5_core_dev *dev, = int *module_num) } =20 static int mlx5_query_module_id(struct mlx5_core_dev *dev, int module_num, - u8 *module_id) + u8 *module_id, u8 *status) { u32 in[MLX5_ST_SZ_DW(mcia_reg)] =3D {}; u32 out[MLX5_ST_SZ_DW(mcia_reg)]; - int err, status; + int err; u8 *ptr; =20 MLX5_SET(mcia_reg, in, i2c_device_address, MLX5_I2C_ADDR_LOW); @@ -308,12 +308,12 @@ static int mlx5_query_module_id(struct mlx5_core_dev = *dev, int module_num, if (err) return err; =20 - status =3D MLX5_GET(mcia_reg, out, status); - if (status) { - mlx5_core_err(dev, "query_mcia_reg failed: status: 0x%x\n", - status); + if (MLX5_GET(mcia_reg, out, status)) { + if (status) + *status =3D MLX5_GET(mcia_reg, out, status); return -EIO; } + ptr =3D MLX5_ADDR_OF(mcia_reg, out, dword_0); =20 *module_id =3D ptr[0]; @@ -370,13 +370,14 @@ static int mlx5_mcia_max_bytes(struct mlx5_core_dev *= dev) } =20 static int mlx5_query_mcia(struct mlx5_core_dev *dev, - struct mlx5_module_eeprom_query_params *params, u8 *data) + struct mlx5_module_eeprom_query_params *params, + u8 *data, u8 *status) { u32 in[MLX5_ST_SZ_DW(mcia_reg)] =3D {}; u32 out[MLX5_ST_SZ_DW(mcia_reg)]; - int status, err; void *ptr; u16 size; + int err; =20 size =3D min_t(int, params->size, mlx5_mcia_max_bytes(dev)); =20 @@ -392,12 +393,9 @@ static int mlx5_query_mcia(struct mlx5_core_dev *dev, if (err) return err; =20 - status =3D MLX5_GET(mcia_reg, out, status); - if (status) { - mlx5_core_err(dev, "query_mcia_reg failed: status: 0x%x\n", - status); + *status =3D MLX5_GET(mcia_reg, out, status); + if (*status) return -EIO; - } =20 ptr =3D MLX5_ADDR_OF(mcia_reg, out, dword_0); memcpy(data, ptr, size); @@ -406,7 +404,7 @@ static int mlx5_query_mcia(struct mlx5_core_dev *dev, } =20 int mlx5_query_module_eeprom(struct mlx5_core_dev *dev, - u16 offset, u16 size, u8 *data) + u16 offset, u16 size, u8 *data, u8 *status) { struct mlx5_module_eeprom_query_params query =3D {0}; u8 module_id; @@ -416,7 +414,8 @@ int mlx5_query_module_eeprom(struct mlx5_core_dev *dev, if (err) return err; =20 - err =3D mlx5_query_module_id(dev, query.module_number, &module_id); + err =3D mlx5_query_module_id(dev, query.module_number, &module_id, + status); if (err) return err; =20 @@ -441,12 +440,12 @@ int mlx5_query_module_eeprom(struct mlx5_core_dev *de= v, query.size =3D size; query.offset =3D offset; =20 - return mlx5_query_mcia(dev, &query, data); + return mlx5_query_mcia(dev, &query, data, status); } =20 int mlx5_query_module_eeprom_by_page(struct mlx5_core_dev *dev, struct mlx5_module_eeprom_query_params *params, - u8 *data) + u8 *data, u8 *status) { int err; =20 @@ -460,7 +459,7 @@ int mlx5_query_module_eeprom_by_page(struct mlx5_core_d= ev *dev, return -EINVAL; } =20 - return mlx5_query_mcia(dev, params, data); + return mlx5_query_mcia(dev, params, data, status); } =20 static int mlx5_query_port_pvlc(struct mlx5_core_dev *dev, u32 *pvlc, --=20 2.31.1 From nobody Tue Dec 2 02:52:38 2025 Received: from BYAPR05CU005.outbound.protection.outlook.com (mail-westusazon11010011.outbound.protection.outlook.com [52.101.85.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 876972C178E; Mon, 17 Nov 2025 21:43:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.85.11 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763415789; cv=fail; b=YY8sSY9XTLtpHeO6Jp1HrwFfBjXEOJCxkUSHGf8sEZcUhktVybQepgEltkVfJdIiwtX4KY2q8vdb9/gWBY+RNA6SMb9A86DnL4G5Y/LPtda32wQ4DI3QsJgmUKRakaNaK/mv7Qwk1PcB4jmMSJ/NcDGXGNnnzcY6mprDG80c8Sk= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763415789; c=relaxed/simple; bh=OkNWMBTwQBpKm0X0Tms+CoCOJ/ReinGPhohC7RETALc=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=PmZvc/8fPJ9FHXyy7WXxoxx+i83mi6d7bUUd+1NCUckocWL7p0/UuSTwJ9t1lyoxIIt4AJ3cO+QkJaJf6znU7+uV8RpDC5TOltDoK36A4mrsX9K+TxhTVdZm4TB1GUKITU5SeuDilE3wCsDvvu/0C2NGWvqIN8J0VOB/XEjonh8= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=t9kRD1w1; arc=fail smtp.client-ip=52.101.85.11 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="t9kRD1w1" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=ji0JFycW5UQmAhGd5ILPUEcAJR51sjp4WxUS2bqxTuXR7IAPVPp9oEogIvMc3SOWPLOEjdCxFzT4vwJWl2BjsQLuLT9yIwIyxc5OUyYce5FdD1W7KLzDTTUkUU4+0bDVXH8TBuR9CtvMxGv/SmuMBfcAkyxBCyKgiEOopK97QjtEjA6Xj2BjJPkDUj1Z/StDdIJLNZ3H39KloW35EmnitwWz3O5R6rpIQcqYoo/9jNc2tBbcskjV3Tv1E9VSle4JIPRcOSbVHEk+fehfn7T8igzilP6DODL+7hxc43f+zBk9+3kIpLCZ5cjSjpg5L5ulRFRmNPUge4WV9P6PEjfT7Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=3pyg2gw5QpQs3djxuy7tGJedam/2PCyfCltUP/ZOeyg=; b=fryEHvzNrgAShGt2QO+wHcBCgk/8b61TrnTGgzVs7mf/3peCMfm+LCLxgmzxaoAJq30qqqcOwj1diB4cOSA1cemtdrJ+XBUHuW2IhoFCeTYXOPiN5jz4osCWRutDz47SKMkVhxqMIJoLwnjesOqhsb54yPOVVoOYxwcJZNvO2cLQeq3SCq249jeCYT+/agWx/WWEABzPc0JMJok1FEjUeap7Xl1vcYbBVX7rBQ62pihEx92ryJvGDuEs6uYy7ZpL1/LeSpR1+VzJSvaExq5fYszPtBWaQTtgoHuN4xwuXw7fGUeA2bCXEgJkDo/uUsNX9r2Nk1qZFPdqadYWh57cAw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=google.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=3pyg2gw5QpQs3djxuy7tGJedam/2PCyfCltUP/ZOeyg=; b=t9kRD1w1mpOefOyJRobguz8zaEf8O7YkMQ6elLei6f6FWtvsIhtXd+037XUA0AmsJHiQNhfNLrogm8mQ2ZRNraxfgds2EApIIMLgPMtIkz3TXuRtnDjrytD5yNps7Ybf426kw8AEQ43IzL82QbRTWgXYdoIjaup3p0NO6X51h3SHeiw/ZT2qAtih5WRIHxYdSE9eBX8HT58U66Ema/uXF17uZmTZex46mCW/iUvk6ZfvrKaimnXFGYHgPdy/a2qoaU+n9gxKPcAi/Rg5QLtBK3lEyXFVCcB+FHZrPdzzATup8LuD7Rtx3uLwh2viqU604n2ZkeDJAbk8vVdkg7DP6Q== Received: from CH2PR14CA0040.namprd14.prod.outlook.com (2603:10b6:610:56::20) by BL4PR12MB9508.namprd12.prod.outlook.com (2603:10b6:208:58e::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9320.18; Mon, 17 Nov 2025 21:43:00 +0000 Received: from CH2PEPF0000013D.namprd02.prod.outlook.com (2603:10b6:610:56:cafe::c8) by CH2PR14CA0040.outlook.office365.com (2603:10b6:610:56::20) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9320.22 via Frontend Transport; Mon, 17 Nov 2025 21:43:01 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by CH2PEPF0000013D.mail.protection.outlook.com (10.167.244.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9343.9 via Frontend Transport; Mon, 17 Nov 2025 21:43:00 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Mon, 17 Nov 2025 13:42:41 -0800 Received: from rnnvmail201.nvidia.com (10.129.68.8) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Mon, 17 Nov 2025 13:42:40 -0800 Received: from vdi.nvidia.com (10.127.8.10) by mail.nvidia.com (10.129.68.8) with Microsoft SMTP Server id 15.2.2562.20 via Frontend Transport; Mon, 17 Nov 2025 13:42:36 -0800 From: Tariq Toukan To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , "Richard Cochran" , , , , Gal Pressman , Moshe Shemesh , Dragos Tatulea , Carolina Jubran Subject: [PATCH net-next 2/5] net/mlx5e: Recover SQ on excessive PTP TX timestamp delta Date: Mon, 17 Nov 2025 23:42:06 +0200 Message-ID: <1763415729-1238421-3-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1763415729-1238421-1-git-send-email-tariqt@nvidia.com> References: <1763415729-1238421-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF0000013D:EE_|BL4PR12MB9508:EE_ X-MS-Office365-Filtering-Correlation-Id: 94086160-0cc1-4bad-ff00-08de262247b2 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|82310400026|7416014|36860700013|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?O5Lpq4bFS7BUb1nUU5bQ/F1WDInfuQ4PuIZAjSyUAsSkJNqu0/Q5bwzYFrG1?= =?us-ascii?Q?qubdoHfXDP3+RwGxmGVDF/Q/NBshh7mR4U+qnm4h99FfsPSEnszPzLn53XIh?= =?us-ascii?Q?YzHnCWGJfZL1eaqBhq/a7940qpXFg868/yk4jhn98GrY6FLexQlzhNDLVpr8?= =?us-ascii?Q?hkqCE6kOMCvsjwSOJ/nJAnypfE++kOmu0h4x+qv8jmkqfG/R213PFm3bW+fR?= =?us-ascii?Q?idVmFUccXZGNR+UOiZZDYkHbtvoIFBkc2eVo43Od3HmRVW6HKffU8qk4tKJB?= =?us-ascii?Q?QZuAsLPKt+V4Ps23qtHr/IUSwR9CQCtAhgyBu4KGXQUtG67fgS3RLpncneM+?= =?us-ascii?Q?csEJWhzPRWhW+q9e4M6enlzUzVZ56JNaDbdPW+1wzrx4rCrDPkTg8tCGFFkk?= =?us-ascii?Q?S6CBjjEcC5aE15JPy01BTh+ge1t8YgRCf+YN9LzABgNGbSZaSYu/NThzANaq?= =?us-ascii?Q?KeTBUQL9Ssa0OXxz3ZSuvqMv07+2+tEFSbM5WsVV/Sm5gI5GQWMF7bQBJ74N?= =?us-ascii?Q?yX3cKaESlJNQa2a/gkqjFMcksicZtZom2CHQxIfsWhyWOdu6rUPqrkNXNBpC?= =?us-ascii?Q?7DGw8XVQxHLLLZCjLwfvTGwPjn7BwuoLwMzlhr4pMn0WcqTtfVTKKDo6gKAw?= =?us-ascii?Q?e0a6EiGckIpHh1mA3CbTC3lMmq6xNY4UGUH5C5EswhfK4nCUeuUbVEBfafk6?= =?us-ascii?Q?ccptMh9EjpxD1wHPZpWRBPizmdAydiyZcQerLapWVrCEa8F7xOBuk1XCJ+2D?= =?us-ascii?Q?z9ZNrtzqahuRa2T7V6rMvMnLLaVU+AEBG9ya4U7mWZ5Jjha44LwRVJoFGkIa?= =?us-ascii?Q?hB5woLPicWSdO32VMP+TIpzwE1VTxN1A2beByRhJ9JgMIJnCGRsUQThwYk/o?= =?us-ascii?Q?moKKYZSP8lyRRvrVN/Mz++WsTuEQftpWQvndV2kl0XZZvWTz95ie2QJaWUTr?= =?us-ascii?Q?5s1ZEUk3rDBXIk42L0kA0ssrfMMuzEZgRpmPLgRWxeXNsl2NB3Q74ZmOaOW1?= =?us-ascii?Q?uWVMArjh1VV+mGfh1E54ScxA6qUSX+VLDfpt0bWhQc6JkDW0s2/rO5AP4Sda?= =?us-ascii?Q?tR7Mf/47XGqy49zgDP8+nKarn0dJTHrNg4EkH/94a8Mo+b6vm6d/jvKVNKuL?= =?us-ascii?Q?bg/Kfu+5cgHQzGFdVR6wt+q5SD2v2Y2xHCpe2auCnSpCaEG85u/RxzD1XnXQ?= =?us-ascii?Q?aqbGIS5XzJkeCvFaD4jXU9QFTfmdfM/JUS3neX/wJthLrQE+X5Sbev099n13?= =?us-ascii?Q?1XUo9ckXOMG1NwHhGKNK2DQ5hap8aQLB/I8cPkp2Xbn5q5bAinfz6vr6F3j/?= =?us-ascii?Q?ra5mzJdH5qRuUCQOzkP3Gzb+w0vpB1kLtW7iR4lp3j6FG5QiwPV6dXaMSldN?= =?us-ascii?Q?4nelyfMidqFJkgEQzrINGZrpzqEI5UcmaecY7ZoTMthihuC7I/aSveVXxw36?= =?us-ascii?Q?EyvOE597NtjYOeYVTv5liG9QDe1ODOe+oXaDjc6mUBhNQbd3Mu/ktNNL9Ris?= =?us-ascii?Q?yQSKEe3u4cIbN6ZGW4JbJhg9BRNqtp37oi/jupxnzGM40mtlpVyUMx0KMtRn?= =?us-ascii?Q?78aBKxrXFYumztY2wyc=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(82310400026)(7416014)(36860700013)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Nov 2025 21:43:00.5272 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 94086160-0cc1-4bad-ff00-08de262247b2 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF0000013D.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL4PR12MB9508 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Carolina Jubran Extend the TX timestamp handler to recover the SQ when the difference between the port and CQE TX timestamps is abnormally large. The current logic aborts timestamp delivery if the delta exceeds 1/128 seconds, which matches the maximum expected packet interval in ptp4l. A larger delta makes the timestamps unreliable. This change adds recovery if the delta exceeds 0.5 seconds. Such a large gap should not occur in normal operation and indicates that firmware is stuck or metadata tracking is out of sync, leading to stale or mismatched timestamps. Recovering the SQ ensures forward progress and avoids silently dropping invalid timestamps. The timestamp handler now takes mlx5e_ptpsq directly to access both CQ stats and the recovery state. Signed-off-by: Carolina Jubran Reviewed-by: Shahar Shitrit Signed-off-by: Tariq Toukan --- .../net/ethernet/mellanox/mlx5/core/en/ptp.c | 21 +++++++++++++------ .../net/ethernet/mellanox/mlx5/core/en/ptp.h | 2 +- .../net/ethernet/mellanox/mlx5/core/en_tx.c | 2 +- 3 files changed, 17 insertions(+), 8 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/ptp.c b/drivers/net= /ethernet/mellanox/mlx5/core/en/ptp.c index 12e10feb30f0..424f8a2728a3 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/ptp.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/ptp.c @@ -82,7 +82,7 @@ static struct mlx5e_skb_cb_hwtstamp *mlx5e_skb_cb_get_hwt= s(struct sk_buff *skb) } =20 static void mlx5e_skb_cb_hwtstamp_tx(struct sk_buff *skb, - struct mlx5e_ptp_cq_stats *cq_stats) + struct mlx5e_ptpsq *ptpsq) { struct skb_shared_hwtstamps hwts =3D {}; ktime_t diff; @@ -92,8 +92,17 @@ static void mlx5e_skb_cb_hwtstamp_tx(struct sk_buff *skb, =20 /* Maximal allowed diff is 1 / 128 second */ if (diff > (NSEC_PER_SEC >> 7)) { - cq_stats->abort++; - cq_stats->abort_abs_diff_ns +=3D diff; + struct mlx5e_txqsq *sq =3D &ptpsq->txqsq; + + ptpsq->cq_stats->abort++; + ptpsq->cq_stats->abort_abs_diff_ns +=3D diff; + if (diff > (NSEC_PER_SEC >> 1) && + !test_and_set_bit(MLX5E_SQ_STATE_RECOVERING, &sq->state)) { + netdev_warn(sq->channel->netdev, + "PTP TX timestamp difference between CQE and port exceeds threshol= d: %lld ns, recovering SQ %u\n", + (s64)diff, sq->sqn); + queue_work(sq->priv->wq, &ptpsq->report_unhealthy_work); + } return; } =20 @@ -103,7 +112,7 @@ static void mlx5e_skb_cb_hwtstamp_tx(struct sk_buff *sk= b, =20 void mlx5e_skb_cb_hwtstamp_handler(struct sk_buff *skb, int hwtstamp_type, ktime_t hwtstamp, - struct mlx5e_ptp_cq_stats *cq_stats) + struct mlx5e_ptpsq *ptpsq) { switch (hwtstamp_type) { case (MLX5E_SKB_CB_CQE_HWTSTAMP): @@ -121,7 +130,7 @@ void mlx5e_skb_cb_hwtstamp_handler(struct sk_buff *skb,= int hwtstamp_type, !mlx5e_skb_cb_get_hwts(skb)->port_hwtstamp) return; =20 - mlx5e_skb_cb_hwtstamp_tx(skb, cq_stats); + mlx5e_skb_cb_hwtstamp_tx(skb, ptpsq); memset(skb->cb, 0, sizeof(struct mlx5e_skb_cb_hwtstamp)); } =20 @@ -209,7 +218,7 @@ static void mlx5e_ptp_handle_ts_cqe(struct mlx5e_ptpsq = *ptpsq, =20 hwtstamp =3D mlx5e_cqe_ts_to_ns(sq->ptp_cyc2time, sq->clock, get_cqe_ts(c= qe)); mlx5e_skb_cb_hwtstamp_handler(skb, MLX5E_SKB_CB_PORT_HWTSTAMP, - hwtstamp, ptpsq->cq_stats); + hwtstamp, ptpsq); ptpsq->cq_stats->cqe++; =20 mlx5e_ptpsq_mark_ts_cqes_undelivered(ptpsq, hwtstamp); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/ptp.h b/drivers/net= /ethernet/mellanox/mlx5/core/en/ptp.h index 1c0e0a86a9ac..2a457a2ed707 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/ptp.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/ptp.h @@ -147,7 +147,7 @@ enum { =20 void mlx5e_skb_cb_hwtstamp_handler(struct sk_buff *skb, int hwtstamp_type, ktime_t hwtstamp, - struct mlx5e_ptp_cq_stats *cq_stats); + struct mlx5e_ptpsq *ptpsq); =20 void mlx5e_skb_cb_hwtstamp_init(struct sk_buff *skb); #endif /* __MLX5_EN_PTP_H__ */ diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_tx.c b/drivers/net/= ethernet/mellanox/mlx5/core/en_tx.c index 2702b3885f06..14884b9ea7f3 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_tx.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_tx.c @@ -755,7 +755,7 @@ static void mlx5e_consume_skb(struct mlx5e_txqsq *sq, s= truct sk_buff *skb, hwts.hwtstamp =3D mlx5e_cqe_ts_to_ns(sq->ptp_cyc2time, sq->clock, ts); if (sq->ptpsq) { mlx5e_skb_cb_hwtstamp_handler(skb, MLX5E_SKB_CB_CQE_HWTSTAMP, - hwts.hwtstamp, sq->ptpsq->cq_stats); + hwts.hwtstamp, sq->ptpsq); } else { skb_tstamp_tx(skb, &hwts); sq->stats->timestamps++; --=20 2.31.1 From nobody Tue Dec 2 02:52:38 2025 Received: from CH5PR02CU005.outbound.protection.outlook.com (mail-northcentralusazon11012032.outbound.protection.outlook.com [40.107.200.32]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C476034B68A; Mon, 17 Nov 2025 21:43:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.200.32 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763415793; cv=fail; b=QT/FDHXv5RNVlqduHcT4Ey1N/HucucOS4NKn/ubRShQb+uVy/VWMkxnK9KJ1b0S3nXslnfDCYiF6BtuPfqqCvvu21aBmLIFsEo3tqKgeOz9zLxC9o8HF5mMv0PGTpc89LToA+mhUbuLDBIcFDlV485LmETeg3+COzz5wDKzNuww= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763415793; c=relaxed/simple; bh=1ZCnOinGwlXlElnb6vK6LnlfZQYB53g66XMHPkEVCCc=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=eSCo4dUGh8r/3cxjClyUQQqIqhAYk4LTesVHz8pnJ5r/bMKzNbhlcQR7MSK455thyKhozSGPvuifXyeYHRSFPkDAj3otdW+KEqbOujAip4kYRDRVlZk3qj72sw9haYmOQ1qT0WwYNQaEnyDYkR4IRIsXUzbQK14NgwhWKUgqMCQ= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=n2QfTi/B; arc=fail smtp.client-ip=40.107.200.32 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="n2QfTi/B" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=N5d3ZP3qESFIoqQjdSGjRMlFPAHpkilyfeARhoL0AF49ku09kLLEba1VAUba0/E/H3aFVZviUQ1bBAthkl5e7Ru0H1TgzPjvcsMjtmNOJFBBXqWIxqX+lsjAdaY46UOZ8ABRKK3gJ5NYRU3S3QJd6IDYlHah5WcVOlSbyNJuqaLUYLNwngmbGhY14fFGT6Y4d0vlzhPN1JSZjTJ7M843PrIaQlyCHq0n0VT0D26/eRoZ8/fxUGYFchK1FE8PgjoZzvJoa/hiL37Pj3/wu3TAn54p1Hks09CrjBkR2tdD9EtMNA5bNIUiM9aZCjfIPMktMgDahM4NmkqK5yKtTuOSiQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=TbLKW+WYkENtZXUccWCyj6pVheQXZQpppf7a0kIsoz8=; b=DINyOLiqNYKVZDdBvnn2R4kLIl3nFvi+osUOgITPGCme3U5GkJ2Am3moIxlCueW1d3F2k4uKRcUOH7rU7Oy9NfoM+C3YWKdbZvAadLThCshs6AswBMN2vzCov1ynJMsysiwYpulgnr+DwCqG9489yxKEQRdLqlyGGGD/UkCCbvG1/GqfE6dvUfSb0D/Ot3PGETXj7jRhi9f84ah01/T3Uph+u4Z00jn0YqGolzY6bBenQwUflrGm044sn0UwG9gcKjAD1aco2NDwcw0rP8KsnY6XsXXq47cWbDrsdtqzznJV2tL20WcCetCJ/ddm0A8ALDAhzCzd9BLD0X9+w0JxtA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=google.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=TbLKW+WYkENtZXUccWCyj6pVheQXZQpppf7a0kIsoz8=; b=n2QfTi/B9GETvLmNcAi7VheZzvvTzw/kcIU1ddDut+JpX428B0yHh+5WAsJEPuEsZQ5v0baTvCvR+TYvszUQiZiL1xpl1FA/+mvPe0iYxi1Nk22b2yN5yi1CTG8jraMYzNJYbAOQIyNYTqifIYVX1vHcwJNAJP3NwBT14ZKjQi0YpGYM+D/74xcb6DRC8eeAkPxbQ2Fn2kKFvuzzevmwXB8U418dHAogFg8xpvIpvms9IhMvGdtj0CGsJTQtL2MBknWm+zzmkMjBFvna+OW21wOhQ0l/LOcVudO2OMGyxL7kHRPuwzwOBnN/sFxQAy+fmohZGQgpuiB5YSY4B1G+7A== Received: from CH0PR03CA0406.namprd03.prod.outlook.com (2603:10b6:610:11b::14) by MW4PR12MB7285.namprd12.prod.outlook.com (2603:10b6:303:22e::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9320.22; Mon, 17 Nov 2025 21:43:04 +0000 Received: from CH2PEPF0000013B.namprd02.prod.outlook.com (2603:10b6:610:11b:cafe::2e) by CH0PR03CA0406.outlook.office365.com (2603:10b6:610:11b::14) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9320.22 via Frontend Transport; Mon, 17 Nov 2025 21:42:45 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by CH2PEPF0000013B.mail.protection.outlook.com (10.167.244.68) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9343.9 via Frontend Transport; Mon, 17 Nov 2025 21:43:04 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Mon, 17 Nov 2025 13:42:46 -0800 Received: from rnnvmail201.nvidia.com (10.129.68.8) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Mon, 17 Nov 2025 13:42:45 -0800 Received: from vdi.nvidia.com (10.127.8.10) by mail.nvidia.com (10.129.68.8) with Microsoft SMTP Server id 15.2.2562.20 via Frontend Transport; Mon, 17 Nov 2025 13:42:41 -0800 From: Tariq Toukan To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , "Richard Cochran" , , , , Gal Pressman , Moshe Shemesh , Dragos Tatulea , Carolina Jubran Subject: [PATCH net-next 3/5] net/mlx5: Remove redundant bw_share minimal value assignment Date: Mon, 17 Nov 2025 23:42:07 +0200 Message-ID: <1763415729-1238421-4-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1763415729-1238421-1-git-send-email-tariqt@nvidia.com> References: <1763415729-1238421-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF0000013B:EE_|MW4PR12MB7285:EE_ X-MS-Office365-Filtering-Correlation-Id: 3d735b3c-7a76-459f-3444-08de26224a2d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|82310400026|7416014|376014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?P3j/N+8YyH/Kw8d+M1ci5fOd9zIlgKYCoXmb+xTy2YwijI+/rwK9AgRtq41z?= =?us-ascii?Q?2YeZRR4nMusx0e7WbkpQ16XbSZlJUGlYzrV1oLxNPDQ5DYUKkzkLVMkKvkct?= =?us-ascii?Q?9h3SXaXUv0ZQP0bpP0XckDRhDAl1Ibu6ZbCMexEgqZK9BsUVZ8B7bAnvpm8E?= =?us-ascii?Q?wV7XsLhd3J3E5YuuJmDTL6Df+IEjjuzeaz5VjLUVNOrvZyXeuxtnP475Z2Nx?= =?us-ascii?Q?qPKd48A8gXhZfvHd1WOhJSxn/jfym8SBouTzhGrVC2qNf4KaeXWCqYoyTmMz?= =?us-ascii?Q?/gmS9yyN0U/fzABicCoPmrHNSMh1gUsowGq4q6kk1qseqrDt8jDjU/BXaQfl?= =?us-ascii?Q?krtfmYXkOhlvGNg3UDfUj6ZQuMSEA+zqf7QdIIlR3Jem412NKidJvosk369S?= =?us-ascii?Q?5boxKwoUTQ662nJOHbI/EhHTOyR+OiVjUu/WBCl6YNKesMzLBWjFs5bI+qIy?= =?us-ascii?Q?h1I4TarcPB0XZPbUbLOwfQCZarXKJ6L3eEJ212cXEBMeuiXwdDDvCxWbn3Rx?= =?us-ascii?Q?KUx0F3Q6cfkq6wtmTn6Hru2nAH7+IHuwLKr55+v/vmafkMVLIrrZ+xujFX6H?= =?us-ascii?Q?I2s0Kh8OlUBRtpcHLsK8DhmiY4v8lDzTMN5PlmuuBQK1Y1HAZlK52QGsh8bM?= =?us-ascii?Q?i7uxdLwq2kv5NfpAa7nG9gYWBzHDx6HZgI0CYgdHX0+m+UY+jIxD2vF/O5NK?= =?us-ascii?Q?oMddLMPdPh/84M0xneRVmUpY7Cf0S0YJW7/LimQMPqaptaq69qCZO9UzOVIM?= =?us-ascii?Q?MWUcTq3jKplCD0FkRXeEmQmBcm69mIYaSnOoxxLZc4mgen12QHYsX2GZ8Tbg?= =?us-ascii?Q?w8UWGy0IGkP87MU+wBNlk/Kytq0PIAJ94rrpHHxnEEBA0pKytowvEwV3ByMJ?= =?us-ascii?Q?Uih5B43Gs8e8Kfm2JA53rc600wfNKJO+KJinhbVROSmK1dS9UJ4Qu9+OZfI3?= =?us-ascii?Q?nGOx3Ev122TyqA7yvBy8wSxCprmKtwY4puhHabdUWKQxtUkFuuE3oXWIJJyR?= =?us-ascii?Q?ORHBpeBL5b112/to+6vrAyPyuulKIjizT8tv3pO91Ml2d8xgtZxesHEf7Cq+?= =?us-ascii?Q?2YpgxdhnXdcSV0zHig1pIs58nDb/eGBUHGdWA5uaTbhWAVhXedGFIwF3Zpql?= =?us-ascii?Q?lX5dMiv/1Us4dKhzV3c0c0strUQ9ZecMlDPHLPQplwHtzghjLIC/0d7NuX2v?= =?us-ascii?Q?rsWcjfhS6nG2IpZIPEMHcsu7cbMfUKU+83q+S5vNJ/jsMqxiQtj9/1tn8U4s?= =?us-ascii?Q?CJc6XIXbWHSwFjuX01atfSePDJLSYz8S8IziTmfxIODu9zsU9KI/8MLZofHl?= =?us-ascii?Q?ymaT6IB82S4vlrxfBeZW0hTzCipSVeVTV805cvyoGN0WYKTni/LtqbQ7Dtmg?= =?us-ascii?Q?W9Jy1YBLYBCihtfWxB2F975WZyiN7/kWb0tsFzglAVFvw2a3c+pQedRYUybo?= =?us-ascii?Q?jpzTNLmzNpZ6NUyIMqAeVDlVJDGN+BxVv3Rd3iH9tiV2raUAw0sXchey+7rc?= =?us-ascii?Q?zd3X3DzQdSIQ8g/m+RvKa0YpNbFLLLKxTHzmoTuoEzJrIaL6lbpB/20wgum0?= =?us-ascii?Q?IzjtWXq0D3rnFw/mP9w=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(1800799024)(82310400026)(7416014)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Nov 2025 21:43:04.6793 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3d735b3c-7a76-459f-3444-08de26224a2d X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF0000013B.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB7285 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Carolina Jubran Remove unnecessary logic that sets bw_share to minimal value, when parent has bw_share configured but nodes don't have min_rate. This check is redundant because the parent bandwidth acts as the upper bound regardless, and the firmware always enforces the topmost bandwidth constraint. Signed-off-by: Carolina Jubran Reviewed-by: Cosmin Ratiu Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c | 7 ------- 1 file changed, 7 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/esw/qos.c index 56e6f54b1e2e..4278bcb04c72 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c @@ -341,13 +341,6 @@ static u32 esw_qos_calculate_min_rate_divider(struct m= lx5_eswitch *esw, if (max_guarantee) return max_t(u32, max_guarantee / fw_max_bw_share, 1); =20 - /* If nodes max min_rate divider is 0 but their parent has bw_share - * configured, then set bw_share for nodes to minimal value. - */ - - if (parent && parent->bw_share) - return 1; - /* If the node nodes has min_rate configured, a divider of 0 sets all * nodes' bw_share to 0, effectively disabling min guarantees. */ --=20 2.31.1 From nobody Tue Dec 2 02:52:38 2025 Received: from MW6PR02CU001.outbound.protection.outlook.com (mail-westus2azon11012038.outbound.protection.outlook.com [52.101.48.38]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CE6C534D4F6; Mon, 17 Nov 2025 21:43:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.48.38 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763415798; cv=fail; b=oiJX2IHjiwf9j7K6bWkV23fv2XHS3be1YDG/I6k4E7JOG78e/DUqdU2TVlvWteTr8wx0CK+8EvfBGpIAoOMEJltDJV9VaaPD7GAIGctK8+FykCMP5jTsc6g2Smf2mDl75QFg5o6SoKpzCJo5+aQ2mgCttX3fOtYe/Mn3H2caa0o= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763415798; c=relaxed/simple; bh=mBzenU6+UmtBTZgWnPg79nrGY7MaJW76iY3OSjAcb28=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=riQoXELSkcAFTAEIo1N0B3jpi3aU+PO1ur28RK6yLsEdmuIW00+3ZcbcHuEQl22x3gbcaLJ8MReve/Rea50z1sxtV8lJZ/ztNxwydlEI/aMVdSUCPELgg/8IsjnKXrqNpA20ipif71sdC+ecnZ4jyyTI1IO4yS+bl6BN4dDRSuc= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=k5gQDIEF; arc=fail smtp.client-ip=52.101.48.38 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="k5gQDIEF" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=eHwlcLwB9lv7QwO3JIVkrikaq7Ka9uPddftVsrOCRxSc6+J0DUM1hqB3EnB4vjkCxKT6EXblvRGnagDp8hU9O6Rl6Tx6+RwwI3ZpTXWSkFM+uEXsvCQhWl1gtSn+RNFqwEUaOkEVL3ppdJ2Wx991sUlGr2d9hbOINObu4IB9m5yZxIW+SDSl7PZ3Sj/LKbojysEjFPLDv/cf+qZxyJe/p7QQVGWAY32dmhfvc77yw6xgrUQAnXVyatrJQWVzhM5Cqy0A0UCKQ9RxXvWeQQsAmaGlEIrb6oOh8VmwvoTNZL9h7jrVX4wjHwCfbEJpNFbs/O/HijKk3BxFH4oeWaiWmw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=/WvAqr7BUrrbqovFddm0f2AKGgd9UEed4IsqEoP4RZI=; b=lmI7eWTP48Hxjs7uPIWJhd+ARfW5+/ybVqsGYRw4a7vjch3Mnxc0XUdjQD35Kj/jZn32k+vSMz/mUoDfqwkaKOD+bTT8HYu5d8GasGihsV7ltCzoOaDsPqzzo7hMkvTW2YiJTk4qrDQSEryKg6kurekzbHLVtFWtdUHGOZ3rrlvILrqCCHrjlW2EGUhkrkYbAkeY3GI9h1AK94ej1F7eEJPdYWDilu55omu0wCKp+aVv4BkDmRNV8gDVZkBIIKrSTBgUX+gTGzEupyH3aM6li0aaODpbHwVFtleU1uqPVxbDLf53je0rxno0Nfe3WEF+P+kFFJD16HLxEmNGJj/8NA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=google.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=/WvAqr7BUrrbqovFddm0f2AKGgd9UEed4IsqEoP4RZI=; b=k5gQDIEFkUnzLszp3YBtA2gXFB5BVy7grcOrigohQ+3l9DPzU2nNydf2ESW1lZOlch+5M+fz2eLS1wnv1bbhYKB36VSVTb8DDabfBpDNcZ/2kUYz0znv/l8Mv0WHIjvJQB2F5uf/K//AFh4GDPFoyKW0tgFJImO1EzZgM6iWu5Y0kTfpV2ik1CsFJBWCLlscLpiuRqQkcckW0HOKBqFS9S9FSLrR/34x84CGoYFuBJMrgJ//bV1QOEc/9jrT5p1trOgdWZn7CeenDBtseEpvwNBgeMsPBmlo5qfc7hin8PuCXvBm+F7OOgqz/R2Mvm87h6g3K2UUfN3HmngNm3FgXg== Received: from SJ0P220CA0030.NAMP220.PROD.OUTLOOK.COM (2603:10b6:a03:41b::6) by CH1PPFF5B95D789.namprd12.prod.outlook.com (2603:10b6:61f:fc00::62a) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9320.21; Mon, 17 Nov 2025 21:43:12 +0000 Received: from SJ1PEPF00001CE8.namprd03.prod.outlook.com (2603:10b6:a03:41b:cafe::86) by SJ0P220CA0030.outlook.office365.com (2603:10b6:a03:41b::6) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9320.22 via Frontend Transport; Mon, 17 Nov 2025 21:43:03 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by SJ1PEPF00001CE8.mail.protection.outlook.com (10.167.242.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9343.9 via Frontend Transport; Mon, 17 Nov 2025 21:43:11 +0000 Received: from rnnvmail203.nvidia.com (10.129.68.9) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Mon, 17 Nov 2025 13:42:51 -0800 Received: from rnnvmail201.nvidia.com (10.129.68.8) by rnnvmail203.nvidia.com (10.129.68.9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Mon, 17 Nov 2025 13:42:50 -0800 Received: from vdi.nvidia.com (10.127.8.10) by mail.nvidia.com (10.129.68.8) with Microsoft SMTP Server id 15.2.2562.20 via Frontend Transport; Mon, 17 Nov 2025 13:42:46 -0800 From: Tariq Toukan To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , "Richard Cochran" , , , , Gal Pressman , Moshe Shemesh , Dragos Tatulea Subject: [PATCH net-next 4/5] net/mlx5: Abort new commands if all command slots are stalled Date: Mon, 17 Nov 2025 23:42:08 +0200 Message-ID: <1763415729-1238421-5-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1763415729-1238421-1-git-send-email-tariqt@nvidia.com> References: <1763415729-1238421-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00001CE8:EE_|CH1PPFF5B95D789:EE_ X-MS-Office365-Filtering-Correlation-Id: 2d35d66b-a471-44a0-167d-08de26224e6d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|82310400026|7416014|376014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?iYRif6fawsdSFsfhK3XK0sx7acQLbNqO/oRi6Pkm5Nt7TZruaZaZnyxQAkHJ?= =?us-ascii?Q?ZrfPlPH5SbbVfWkhYdyZPHFfXgAKXGmaFotPqOuTiAhekt6kSRdvx8J0cenw?= =?us-ascii?Q?6/DYLklPkB1WHTAawDvOo3cBabNJ2bEOLX8jmdV4CgGKKqQvjS7wyT2g/ik1?= =?us-ascii?Q?23xee7jLWmraSlOOUj3kbtI9CX51lMbwTNZ1wEhkvG0tw7AQiCKccz9T6WKn?= =?us-ascii?Q?wdJ9iulhPsFEhwKAaqat72CUNC4ptIfMRfT20ODEX7Xl371f43fmw7LBK1wd?= =?us-ascii?Q?2sqWmkk/ClQMV6AdrfXpi7Fk4kxIoiCpoIZIHW466hgFeSvvfytnUvme8IL1?= =?us-ascii?Q?0KI3QY/6UYeNGCF1F1gkyZQ0GNERjZdR2jCN+7ChbJg2t6JK8A0UvCzafFU5?= =?us-ascii?Q?p8RqeEJjTEjyHWEla2qNSqYd/3qiXil0qN+EJpwVrd+NYJ0W78dtnc4JoAI+?= =?us-ascii?Q?7FKtJ36EZAybYn/tYpOT2DKbDjkpl7MUI5HFKxd9/pUDU8nTx0lCaGksyaUZ?= =?us-ascii?Q?j5iiIHJ5r0r7DvM/+4YTzZpHjPUB4eZBCSQv5LfPVv5UID3506lhMNlilyhT?= =?us-ascii?Q?uX6rbog7xzP/A/ylfialOWs9gtsZqaQviAW8SRRR01mUru1y6F2pH5aHf4aC?= =?us-ascii?Q?IhMd0w/STwfnh2RHPHUoUwzJ/x2npkQYtu4D4a90V9XoYUrt5eOSkoPh0TMQ?= =?us-ascii?Q?g1UzcCYWuQkGuKy/QPybKGSSIwy54JvHSItp85jZ5P9ZaxhyBdPqAD84yqhb?= =?us-ascii?Q?g4rwnylFd0R9AjdoTUIlWaEaYf+V7cVw5h7Bxx3wrMefrTLuV1v1M/ZhSYxh?= =?us-ascii?Q?HJvqfbmhR5DLwzKgcxzoQMJWw4/u0fcVzu++MDqjozCLZawkbtYPLrkRFzJe?= =?us-ascii?Q?OJmPVyzT1xvmGLz3/oe2QyGNHs2vvyr3wX2KWe/dzLVTcpHaw8Xb+yGgPIPm?= =?us-ascii?Q?L9bjHo9vEn5IkvbYZGLPmbfEnbV4hgO0pGuK9MdYH5GiKQMT/RP1rJKDgomk?= =?us-ascii?Q?jeQyIyhTC/1odEfXzG7iQq0Sxj4fJJm0ZYDJGfSYR5hJVCMEa2GvZObTyfJS?= =?us-ascii?Q?pL4gn4Pih9bUXQ4kEAn51lOda5uZTHUjE6F+OYCu4UcmD2aGaBuXGTMcFyYa?= =?us-ascii?Q?yoIa/eVhIx4XieI3ERKJ//DPhRLxgCY1BtfiJRYQNhegSmLk3ICV0csSWgxG?= =?us-ascii?Q?Ps650vS6e+MbAS71J7TLO2L4pKWNySU84X7NziFRBbB/iDSTo+brmj/MYmmY?= =?us-ascii?Q?7K4ng6CHfMOr0m//mERMrmVNgKUkvN0Ae17Sgl79JHIjfh2nJMErJfjdEN90?= =?us-ascii?Q?J+gvee/VJznddIFk1CKyeWMeon1Jmpy5gEG5wjGyJgrziCI4VvhQAt4HyHhU?= =?us-ascii?Q?GVE6U0rUG7ka2k6KyhVw7N4pERh9eUSUE9D5AukQ02LpT/EjW31ODEfNJkMd?= =?us-ascii?Q?8AB70pNUTgSIs0H4ytBomU7/sC04xuRmllb1TcQ0U+gE4wLH1P9id6AgccSh?= =?us-ascii?Q?80epiCbfquOtfdU0KhPYKtYKFyFJ8bGxybz6WXNMyXXezcjqwc9BS1ZWUM2n?= =?us-ascii?Q?AQwMOoO+1disVU4hINk=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(1800799024)(82310400026)(7416014)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Nov 2025 21:43:11.9284 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2d35d66b-a471-44a0-167d-08de26224e6d X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CE8.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH1PPFF5B95D789 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Saeed Mahameed In case of a FW issue, FW might be not responding to FW commands, causing kernel lockout for a long period of time, e.g. rtnl_lock held while ethtool is trying to collect stats waiting for FW to respond to multiple commands, when all of them will timeout. While there's no immediate indication of the FW lockout, we can safely assume that something is wrong when all command slots are busy and in a timeout state and no FW completion was received on any of them. In such case, start immediately failing new commands. Signed-off-by: Saeed Mahameed Reviewed-by: Moshe Shemesh Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/cmd.c | 55 +++++++++++++++++++ include/linux/mlx5/driver.h | 1 + 2 files changed, 56 insertions(+) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/cmd.c b/drivers/net/et= hernet/mellanox/mlx5/core/cmd.c index 722282cebce9..5b08e5ffe0e2 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/cmd.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/cmd.c @@ -181,6 +181,7 @@ static int cmd_alloc_index(struct mlx5_cmd *cmd, struct= mlx5_cmd_work_ent *ent) static void cmd_free_index(struct mlx5_cmd *cmd, int idx) { lockdep_assert_held(&cmd->alloc_lock); + cmd->ent_arr[idx] =3D NULL; set_bit(idx, &cmd->vars.bitmask); } =20 @@ -1200,6 +1201,44 @@ static int wait_func(struct mlx5_core_dev *dev, stru= ct mlx5_cmd_work_ent *ent) return err; } =20 +/* Check if all command slots are stalled (timed out and not recovered). + * returns true if all slots timed out on a recent command and have not be= en + * completed by FW yet. (stalled state) + * false otherwise (at least one slot is not stalled). + * + * In such odd situation "all_stalled", this serves as a protection mechan= ism + * to avoid blocking the kernel for long periods of time in case FW is not + * responding to commands. + */ +static bool mlx5_cmd_all_stalled(struct mlx5_core_dev *dev) +{ + struct mlx5_cmd *cmd =3D &dev->cmd; + bool all_stalled =3D true; + unsigned long flags; + int i; + + spin_lock_irqsave(&cmd->alloc_lock, flags); + + /* at least one command slot is free */ + if (bitmap_weight(&cmd->vars.bitmask, cmd->vars.max_reg_cmds) > 0) { + all_stalled =3D false; + goto out; + } + + for_each_clear_bit(i, &cmd->vars.bitmask, cmd->vars.max_reg_cmds) { + struct mlx5_cmd_work_ent *ent =3D dev->cmd.ent_arr[i]; + + if (!test_bit(MLX5_CMD_ENT_STATE_TIMEDOUT, &ent->state)) { + all_stalled =3D false; + break; + } + } +out: + spin_unlock_irqrestore(&cmd->alloc_lock, flags); + + return all_stalled; +} + /* Notes: * 1. Callback functions may not sleep * 2. page queue commands do not support asynchrous completion @@ -1230,6 +1269,15 @@ static int mlx5_cmd_invoke(struct mlx5_core_dev *dev= , struct mlx5_cmd_msg *in, if (callback && page_queue) return -EINVAL; =20 + if (!page_queue && mlx5_cmd_all_stalled(dev)) { + mlx5_core_err_rl(dev, + "All CMD slots are stalled, aborting command\n"); + /* there's no reason to wait and block the whole kernel if FW + * isn't currently responding to all slots, fail immediately + */ + return -EAGAIN; + } + ent =3D cmd_alloc_ent(cmd, in, out, uout, uout_size, callback, context, page_queue); if (IS_ERR(ent)) @@ -1700,6 +1748,13 @@ static void mlx5_cmd_comp_handler(struct mlx5_core_d= ev *dev, u64 vec, bool force if (test_bit(i, &vector)) { ent =3D cmd->ent_arr[i]; =20 + if (forced && ent->ret =3D=3D -ETIMEDOUT) + set_bit(MLX5_CMD_ENT_STATE_TIMEDOUT, + &ent->state); + else if (!forced) /* real FW completion */ + clear_bit(MLX5_CMD_ENT_STATE_TIMEDOUT, + &ent->state); + /* if we already completed the command, ignore it */ if (!test_and_clear_bit(MLX5_CMD_ENT_STATE_PENDING_COMP, &ent->state)) { diff --git a/include/linux/mlx5/driver.h b/include/linux/mlx5/driver.h index 046396269ccf..7aec53371cf0 100644 --- a/include/linux/mlx5/driver.h +++ b/include/linux/mlx5/driver.h @@ -819,6 +819,7 @@ typedef void (*mlx5_cmd_cbk_t)(int status, void *contex= t); =20 enum { MLX5_CMD_ENT_STATE_PENDING_COMP, + MLX5_CMD_ENT_STATE_TIMEDOUT, }; =20 struct mlx5_cmd_work_ent { --=20 2.31.1 From nobody Tue Dec 2 02:52:38 2025 Received: from CY3PR05CU001.outbound.protection.outlook.com (mail-westcentralusazon11013060.outbound.protection.outlook.com [40.93.201.60]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BE59E34D929; Mon, 17 Nov 2025 21:43:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.93.201.60 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763415804; cv=fail; b=cBTjpVPwonijgZCXFREqZQExiEKzuh2v9uhLe0k2hgMyJ6UviDbjgP3x/Gq0edqxSlWGgWecxshqJMk6TBIWosv6DSs5LlC6nvk3xqrGi99LD9Q9L3vJSxiahB0WfIr674KS15np+KuIfddw7vsKWEW2YpJCuiqW88j8l5AL5PY= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763415804; c=relaxed/simple; bh=g1StgutCFHXlR6ozNoJMmAKXUyEf+4ISbk0hAK4sxuw=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=XvbDBYwj0FAdBKc2/0oRFuI9LHhqfKQvFnWzulyADHJT1gjc07oy/csALlUv+oGPedRw0Hm5RLhSh0MijSqpYRT1acbYcZrUjgigwzcsgHAdM7E/Se0TDqLyg9oOg/c5vc56dqKkSpLyvUIwME5CODFTiRSmVUTI0MGIXfYm0cQ= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=dr5hJxX/; arc=fail smtp.client-ip=40.93.201.60 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="dr5hJxX/" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=fmk33kTvLOC530LtIdBW0JEgbz+Qrkl7O2ZM+u0hRf1d4NsNAx6mUUrr8N7oksn+PofmKPABIuY1ULKIjRg583lvF7tx24m96YOO1/aFItdRzY4d/V40kIqbspdGgXKCcVlRGoc01SdztL3q1Ofnekc4iCj49YM+ErtlWwXR7y9JfQS5h90SXyZ0loPvTJ7k71lVpMZKaMno1o82nBDsDBd6ZO8+W7Fwu873jw26kN+Gm2hzjTUhpEeyGapqXxh95ke0fYGn0/PUx37b/l0kPmLFh00tw0T6fkyKFvlswQfAvyLe+xJiReVScjBhVHNGRbVw5t+n7flJeYL6FAWc9Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=xMH59HLFc/Xy3EQHKQeBPkk4i3QPzY75r3sf9WeBCDs=; b=uIgPQoEWB+9uWLvygcednxmEYVgrS0WPn1TTkxqFtQGCWqvEn4YZ+NEZ65I5p6uBNxz5acD8PSeHdjt11R8DIFuFctbZ/xqzGBB163TA9q7JhYm+WXrCz7/H2rk6MvyznWV7sqRYWqEihyT8VWRPahvzz3mbUiNXGQ/eiuwLxBycCVLV/KleoFiMhJtYmAASYd65lb3y+9r5gtaP2VatnRjhlY8uhAE0UCn73ltLRPCbBAj+vmNVvcTOZJ7OTlCmbk1TMwQ/9f5AS9f5js+Bfj8ho2/hZ8vB/sJdQYeop9Nrq8K/CX5dwfCLXKyqlwXPH7jXIaa1NpfsmeiBUHvbMQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=google.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=xMH59HLFc/Xy3EQHKQeBPkk4i3QPzY75r3sf9WeBCDs=; b=dr5hJxX/D+ZKumqAtmPoY6OBgG0UwHVaMR+oQB2ex3C884TmyilxN8nk8lihLdDzz9qvbOP/MExKFYyQrSNSQ9zzAuVSYzY9zOejQKPFqIzh/AT7rUHH+tqseJSdsZyf8A62DyRVE7pU408lvfRIS0486gnBmnG+cwwcjDHBQ5I1wyD9DfYyY9yw5HskoT1oFDmcoW14MPUliJRuk3Xut1Us7vm0vqP93I4EL/JMT9ORhBhKOZQus6OPJXoU4jwANAmoUDdnuHfT6zl1jfaAFajNmEO/p79Ah3wWV0kguVELWoJT6J3RYEcr7kNjnxH5OWX1wBRhJj9zdA2ifUmRJg== Received: from CH2PR14CA0043.namprd14.prod.outlook.com (2603:10b6:610:56::23) by LV3PR12MB9119.namprd12.prod.outlook.com (2603:10b6:408:1a2::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9320.21; Mon, 17 Nov 2025 21:43:16 +0000 Received: from CH2PEPF0000013D.namprd02.prod.outlook.com (2603:10b6:610:56:cafe::9c) by CH2PR14CA0043.outlook.office365.com (2603:10b6:610:56::23) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9320.22 via Frontend Transport; Mon, 17 Nov 2025 21:43:13 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by CH2PEPF0000013D.mail.protection.outlook.com (10.167.244.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9343.9 via Frontend Transport; Mon, 17 Nov 2025 21:43:13 +0000 Received: from rnnvmail204.nvidia.com (10.129.68.6) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Mon, 17 Nov 2025 13:42:55 -0800 Received: from rnnvmail201.nvidia.com (10.129.68.8) by rnnvmail204.nvidia.com (10.129.68.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Mon, 17 Nov 2025 13:42:55 -0800 Received: from vdi.nvidia.com (10.127.8.10) by mail.nvidia.com (10.129.68.8) with Microsoft SMTP Server id 15.2.2562.20 via Frontend Transport; Mon, 17 Nov 2025 13:42:51 -0800 From: Tariq Toukan To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , "Richard Cochran" , , , , Gal Pressman , Moshe Shemesh , Dragos Tatulea Subject: [PATCH net-next 5/5] net/mlx5: Use EOPNOTSUPP instead of ENOTSUPP Date: Mon, 17 Nov 2025 23:42:09 +0200 Message-ID: <1763415729-1238421-6-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1763415729-1238421-1-git-send-email-tariqt@nvidia.com> References: <1763415729-1238421-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF0000013D:EE_|LV3PR12MB9119:EE_ X-MS-Office365-Filtering-Correlation-Id: 89487329-6350-48b1-da9a-08de26224f87 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|1800799024|82310400026|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?N1WMx9iP7/rtx977coY96bUBaTnMBlSJ+1nNnHJSPRSC63Ln7Ak0zjSmJ64/?= =?us-ascii?Q?AiJ60HjAwErRtJINiETkd/ZqRM7L4u80TGI5g0Z3Md38qgrkCr5SYMs5qOHA?= =?us-ascii?Q?jnf13ymJpJq28GpshvVXw9NQIzam2YAEBBBoT0Fs8xY9pqz4CoB84ykLXP6N?= =?us-ascii?Q?D0uYs0Vqf8l4xV5k4q8esJiv3zTge8xIo1j6pq/wj3OKtsR1Iw0Fn9YM62WQ?= =?us-ascii?Q?ODPA7BOnCrrPn2qtAMrLj8ApvcZEw/FXaXUJbqZzsZ1UuyStjuWrUg7rHyoK?= =?us-ascii?Q?MUeZ5gxeIsKgQRDIjyce1OPLdcxUqtds9mKNecK9qCzdBvmxnYWCfyPX4MJ2?= =?us-ascii?Q?VlazAz0SGUjVgml54kj66SVrm8TqOpuBTCoImKdiZ3+IMClMb9Gq3EVeTmG5?= =?us-ascii?Q?E61aznFMGFWXBJtvPOUhkj0+7yp+XlWZ+/u61Ij54g0wpk9vzyocBkBaug98?= =?us-ascii?Q?4DLvpa30/xjICRCQJJJ9rW/UrP+YkVUq7BoFZzfyyfKK5lUcBIGHdK+Okdal?= =?us-ascii?Q?H9Bx7EOxbknPbL+M+pZrvrg8jSzZ5h6Jt4RVuL97fbzwTUtvNbIr7AGD3h5f?= =?us-ascii?Q?QBlJKgH7otq6u8kODdcjz7OkxrZRElpqgicrvlF7p2MXbKAoEoNQpUuKPYJY?= =?us-ascii?Q?o0zrRM/5aWxzbKY5pjcQabSkESG4/k4gkiV/H+/3beKjhMqzI3RgAHVMJBGn?= =?us-ascii?Q?jF2QmmfVx8HYdLbOyMxEyZMMCLiq4GI0TdASy7h//hauw/ZcuzQBxgqw6UD4?= =?us-ascii?Q?Yznl16dNIihi67HRvfSQVM2ajoUj+IdVvSfWzrpuij3nyVfE0VQnxcsgi6EJ?= =?us-ascii?Q?+wNIFf4QyXFwNsdnnL4Ddl3kD7StDebiKKeb6CKMj62r5sock6S+M0VBPzQF?= =?us-ascii?Q?3i5xN3Y2tvvjIsz5FyW1YWTAQxuwQ8MMnXTU/bzCfWh+pn2W/jisSFc8poBN?= =?us-ascii?Q?2Iz8mno9M52Vd3TRvJ+nmskcBfGQ+CmtllmEPSGoq6HMVxOrfhpB+C/tmvCe?= =?us-ascii?Q?51Z+AQeojwyIodP4PLCf/TYihMNd7KW3BXgUQAjdY7oCr5UM88gMrjYzQtiF?= =?us-ascii?Q?2gwOqsClArBMrs5G0/bIvObCFVf/fqnjR8eD8C2JINAsOBvw+s60916pK3Mk?= =?us-ascii?Q?UyOrrIYXQJjhXAjS5CqG3wA4mcBLJ1hz7bj6OQZgbzyyXxiqBdnDP4iamEJ8?= =?us-ascii?Q?u6EzRHwzuCXV9eKRaf4ZvX+n4RxI1J/S0hoPrO9ZxNApet075fJeAdsD0wZz?= =?us-ascii?Q?EhDlRnTN0uQHaeIq0zliwwGkots36N475ajyB7szkfv/EvOhzCE0fbSYAHMT?= =?us-ascii?Q?fzrpuB7IcdqN2t8DWUnuNhF3vDjlmAQThBMN32Cink7Rgc4WMNYXGjayRlel?= =?us-ascii?Q?3YXCqtUy7rW3gQ10cgM6c/grZ14xLaroJkdjfpYzKUg17gRqCkeuNrBCcJA/?= =?us-ascii?Q?mlnC4EjWgdrYTwFXcbxRxD8v07HVaPweQiLvITrYoFqX1+yzz2QURnkKr26X?= =?us-ascii?Q?kZHD0afoiFmWsKZ3ICdboGhupeY3B9a95FhmADN2l9WMrevPPTmG2LRO4ohC?= =?us-ascii?Q?/2oJCZWukKq8gNvdt3M=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(7416014)(376014)(1800799024)(82310400026)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Nov 2025 21:43:13.6548 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 89487329-6350-48b1-da9a-08de26224f87 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF0000013D.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV3PR12MB9119 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Per Documentation/dev-tools/checkpatch.rst, ENOTSUPP is not a standard error code and should be avoided. EOPNOTSUPP should be used instead. Signed-off-by: Tariq Toukan Reviewed-by: Gal Pressman --- drivers/net/ethernet/mellanox/mlx5/core/diag/fw_tracer.c | 2 +- drivers/net/ethernet/mellanox/mlx5/core/en_fs_ethtool.c | 2 +- drivers/net/ethernet/mellanox/mlx5/core/fpga/core.c | 2 +- drivers/net/ethernet/mellanox/mlx5/core/lib/vxlan.c | 2 +- .../ethernet/mellanox/mlx5/core/steering/sws/dr_domain.c | 8 ++++---- 5 files changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/diag/fw_tracer.c b/dri= vers/net/ethernet/mellanox/mlx5/core/diag/fw_tracer.c index 080e7eab52c7..7bcf822a89f9 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/diag/fw_tracer.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/diag/fw_tracer.c @@ -54,7 +54,7 @@ static int mlx5_query_mtrc_caps(struct mlx5_fw_tracer *tr= acer) =20 if (!MLX5_GET(mtrc_cap, out, trace_to_memory)) { mlx5_core_dbg(dev, "FWTracer: Device does not support logging traces to = memory\n"); - return -ENOTSUPP; + return -EOPNOTSUPP; } =20 tracer->trc_ver =3D MLX5_GET(mtrc_cap, out, trc_ver); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_fs_ethtool.c b/driv= ers/net/ethernet/mellanox/mlx5/core/en_fs_ethtool.c index 79916f1abd14..63bdef5b4ba5 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_fs_ethtool.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_fs_ethtool.c @@ -704,7 +704,7 @@ static int validate_flow(struct mlx5e_priv *priv, num_tuples +=3D ret; break; default: - return -ENOTSUPP; + return -EOPNOTSUPP; } if ((fs->flow_type & FLOW_EXT)) { ret =3D validate_vlan(fs); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/fpga/core.c b/drivers/= net/ethernet/mellanox/mlx5/core/fpga/core.c index e5c1012921d2..1ec61164e6b5 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/fpga/core.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/fpga/core.c @@ -211,7 +211,7 @@ int mlx5_fpga_device_start(struct mlx5_core_dev *mdev) max_num_qps =3D MLX5_CAP_FPGA(mdev, shell_caps.max_num_qps); if (!max_num_qps) { mlx5_fpga_err(fdev, "FPGA reports 0 QPs in SHELL_CAPS\n"); - err =3D -ENOTSUPP; + err =3D -EOPNOTSUPP; goto out; } =20 diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/vxlan.c b/drivers/= net/ethernet/mellanox/mlx5/core/lib/vxlan.c index d55e15c1f380..304912637c35 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lib/vxlan.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lib/vxlan.c @@ -149,7 +149,7 @@ struct mlx5_vxlan *mlx5_vxlan_create(struct mlx5_core_d= ev *mdev) struct mlx5_vxlan *vxlan; =20 if (!MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan) || !mlx5_core_is_pf(mdev)) - return ERR_PTR(-ENOTSUPP); + return ERR_PTR(-EOPNOTSUPP); =20 vxlan =3D kzalloc(sizeof(*vxlan), GFP_KERNEL); if (!vxlan) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/sws/dr_domain= .c b/drivers/net/ethernet/mellanox/mlx5/core/steering/sws/dr_domain.c index 65740bb68b09..e8c67ed9f748 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/sws/dr_domain.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/sws/dr_domain.c @@ -410,7 +410,7 @@ static int dr_domain_caps_init(struct mlx5_core_dev *md= ev, switch (dmn->type) { case MLX5DR_DOMAIN_TYPE_NIC_RX: if (!DR_DOMAIN_SW_STEERING_SUPPORTED(dmn, rx)) - return -ENOTSUPP; + return -EOPNOTSUPP; =20 dmn->info.supp_sw_steering =3D true; dmn->info.rx.type =3D DR_DOMAIN_NIC_TYPE_RX; @@ -419,7 +419,7 @@ static int dr_domain_caps_init(struct mlx5_core_dev *md= ev, break; case MLX5DR_DOMAIN_TYPE_NIC_TX: if (!DR_DOMAIN_SW_STEERING_SUPPORTED(dmn, tx)) - return -ENOTSUPP; + return -EOPNOTSUPP; =20 dmn->info.supp_sw_steering =3D true; dmn->info.tx.type =3D DR_DOMAIN_NIC_TYPE_TX; @@ -428,10 +428,10 @@ static int dr_domain_caps_init(struct mlx5_core_dev *= mdev, break; case MLX5DR_DOMAIN_TYPE_FDB: if (!dmn->info.caps.eswitch_manager) - return -ENOTSUPP; + return -EOPNOTSUPP; =20 if (!DR_DOMAIN_SW_STEERING_SUPPORTED(dmn, fdb)) - return -ENOTSUPP; + return -EOPNOTSUPP; =20 dmn->info.rx.type =3D DR_DOMAIN_NIC_TYPE_RX; dmn->info.tx.type =3D DR_DOMAIN_NIC_TYPE_TX; --=20 2.31.1