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Wed, 12 Nov 2025 01:31:20 -0800 From: Tariq Toukan To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , "Alexei Starovoitov" , Daniel Borkmann , "Jesper Dangaard Brouer" , John Fastabend , , , , , Gal Pressman , Leon Romanovsky , Moshe Shemesh , William Tu , Dragos Tatulea , Nimrod Oren , Alex Lazar Subject: [PATCH net-next 4/6] net/mlx5e: Conditionally create async ICOSQ Date: Wed, 12 Nov 2025 11:29:07 +0200 Message-ID: <1762939749-1165658-5-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1762939749-1165658-1-git-send-email-tariqt@nvidia.com> References: <1762939749-1165658-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWH0EPF000971E9:EE_|PH7PR12MB6884:EE_ X-MS-Office365-Filtering-Correlation-Id: b80174d8-35f1-456b-fec7-08de21ce4dd9 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|7416014|376014|36860700013|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?2EdaqXqxp8F3fqaNkXiO6C1S+plP8r1nSZDvr2OS5oSHMm/HMBJIwNHeAOC2?= =?us-ascii?Q?jfBHkZ6qydpA5Ta9lvBskgButYvKhQ/UYenmm7XPZ5rL/63U76402IpKu9LP?= =?us-ascii?Q?BkiZnSfhk4wbci73VFJDrjiZJTmSRyAmpfhG5S9bwuIJEQQ5pHCJaviUvXN2?= =?us-ascii?Q?wAYjhoPLl8jC+qNmU+YsU2dUW7afuKgRCzL0nCDgJ7djdfiHRihB6P7KehNN?= =?us-ascii?Q?1pAswdl5lz2ncLGQHa19h2AmFIBuA4VmlRecHz2V0wzKs3q8zEAqs3LCHSW2?= =?us-ascii?Q?tBOm0WUGmXQNCGwoz/C/LYAIPUi0hvtwV9+Ya3YGkN/gFW19lQeK2JyOBbLt?= =?us-ascii?Q?YK0NOOHYMl1WhJJjqCf6lQZ3SoRIXHzDe4N/3c2cUjWDk4IeaC9wLN+o4NLr?= =?us-ascii?Q?V/1WHPWfBUqolnrsBRAZHd6IAq2umkI/+qNLRiVRFyc5V0nhzCmT6Nxs/Unb?= =?us-ascii?Q?8sIXLE1pxkl26s/ymu4sw128C4ZxqWodWoOAw9IGWXr8bD6MUIDfsMQ7yh7d?= =?us-ascii?Q?1byqLthGQFVfYva1On7BevWAjEDPsC17Rs2gSNN1BnaXBCOG3AsFvFaQ1wcK?= =?us-ascii?Q?cAq+a08Atcg4a+66d0RxmiFlZVAfhr8rmxpjt97NqsCLVi6oOxeZdrJ96kIL?= =?us-ascii?Q?glpp78czCGxJ70r3UIbQD0rWhlDU4ogGi4jxltc+2ADdczflRnTKtCeiB8Ph?= =?us-ascii?Q?YtGc1W628vI987l3rV/yK9r3G3KaM0LYvzWjFjF6y83BFY5G8kDJr9ux5nWQ?= =?us-ascii?Q?l95A1KokE5hBqRzd2bv9+EId+RniZHGMTmE2Cj8OsWVuj0i1Dg9E5SF6nBjG?= =?us-ascii?Q?5+1D52tsjEUygd2zosQsGRMHHp6FxCrGyUbLK4uWK68GiiZKAUPjyKZxMtHs?= =?us-ascii?Q?wHQEXutF9XW5eBNxWtiPI9evjnmsmYLtR+6YF2MVf3RV8QvJ17T5qvJpi8e3?= =?us-ascii?Q?tQoqB45WKXa2lkb1VX2GsNm0z4Bbs8f8B2NKMDtetHsZwlx4X1QHbffwC+J3?= =?us-ascii?Q?9RDYP2TkSnYNDWSgmZO8C46Th5Pxh0uiQvPEXd3alSF1maFSaqBST3pOsR9a?= =?us-ascii?Q?jF6YuzPsJYLZB67N2F8jQX0CaWYHIuC9RwodxSumOuI5bZsn3cDJNzGueMKJ?= =?us-ascii?Q?s6B6pX1iAzJQS8LBsijp0xOm6h0oefLA0ljlfaitph2685esgltcw4v4TTls?= =?us-ascii?Q?iJg/rnknRWP+VUjkBEshInGE/sV3u3m97JVVxTZ1Rq42JEwmnMYswyCmvaXD?= =?us-ascii?Q?qDfoB9CB1m2lLnB5VPMUWee7MyTvZfd8vd/sL588mzaldWk4/KMC/Qgf3CI3?= =?us-ascii?Q?ua9umLdUpBrNukKMin3onlZ8Hh2ZDH5SHsGm87KJK3ngj9uuvb7X2WWLT6qp?= =?us-ascii?Q?UBnP4yV6/KpcAFBOm+umf5pdQnzN08jNfpU6eGiLCdOTGJlCUCd2qVoYTc4C?= =?us-ascii?Q?xK7lLKd/Fly8RS3NBEoHcBD6DeY7NlEeKgj4pEWzYIeq+Ksg0pkGrFj4dwRJ?= =?us-ascii?Q?hdaB4Q74ta9td+c8OgjhNxP1gSsEnEMQOi+WK5cZGhaSbPAEv2CkcCtJMcgW?= =?us-ascii?Q?wgQMyUQloisIsz3N7Bk=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(7416014)(376014)(36860700013)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Nov 2025 09:31:48.4849 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b80174d8-35f1-456b-fec7-08de21ce4dd9 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000971E9.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6884 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: William Tu The async ICOSQ is only required by TLS RX (for re-sync flow) and XSK TX. Create it only when these features are enabled instead of always allocating it. This reduces per-channel memory usage, saves hardware resources, improves latency, and decreases the default number of SQs (from 4 to 3) and CQs (from 5 to 4). It also speeds up channel open/close operations for a netdev when async ICOSQ is not needed. Currently when TLS RX is enabled, there is no channel reset triggered. As a result, async ICOSQ allocation is not triggered, causing a NULL pointer crash. One solution is to do channel reset every time when toggling TLS RX. However, it's not straightforward as the offload state matters only on connection creation, and can go on beyond the channels reset. In stead, introduce a new field 'ktls_rx_was_enabled': if TLS RX is enabled for the first time: reset channels, create async ICOSQ, set the field. From that point on, no need to reset channels for any TLS RX enable/disable. Async ICOSQ will always be needed. For XSK TX, async ICOSQ is used in wakeup control and is guaranteed to have async ICOSQ allocated. This improves the latency of interface up/down operations when it applies. Perf numbers: NIC: Connect-X7. Setup: 248 channels. Interface up + down: Before: 2.605 secs After: 2.246 secs (1.16x faster) Signed-off-by: William Tu Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/en.h | 1 + .../mellanox/mlx5/core/en_accel/ktls.c | 10 +++++-- .../net/ethernet/mellanox/mlx5/core/en_main.c | 30 ++++++++++++------- .../net/ethernet/mellanox/mlx5/core/en_txrx.c | 5 ++-- 4 files changed, 32 insertions(+), 14 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en.h b/drivers/net/eth= ernet/mellanox/mlx5/core/en.h index 3a68fe651760..fea26a3a1c87 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en.h @@ -958,6 +958,7 @@ struct mlx5e_priv { u8 max_opened_tc; bool tx_ptp_opened; bool rx_ptp_opened; + bool ktls_rx_was_enabled; struct kernel_hwtstamp_config hwtstamp_config; u16 q_counter[MLX5_SD_MAX_GROUP_SZ]; u16 drop_rq_q_counter; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ktls.c b/driv= ers/net/ethernet/mellanox/mlx5/core/en_accel/ktls.c index e3e57c849436..1c2cc2aad2b0 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ktls.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ktls.c @@ -135,10 +135,15 @@ int mlx5e_ktls_set_feature_rx(struct net_device *netd= ev, bool enable) int err =3D 0; =20 mutex_lock(&priv->state_lock); - if (enable) + if (enable) { err =3D mlx5e_accel_fs_tcp_create(priv->fs); - else + if (!err && !priv->ktls_rx_was_enabled) { + priv->ktls_rx_was_enabled =3D true; + mlx5e_safe_reopen_channels(priv); + } + } else { mlx5e_accel_fs_tcp_destroy(priv->fs); + } mutex_unlock(&priv->state_lock); =20 return err; @@ -161,6 +166,7 @@ int mlx5e_ktls_init_rx(struct mlx5e_priv *priv) destroy_workqueue(priv->tls->rx_wq); return err; } + priv->ktls_rx_was_enabled =3D true; } =20 return 0; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/en_main.c index 2b2504bd2c67..d1dbba1a7a2f 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c @@ -2633,7 +2633,8 @@ static void mlx5e_close_async_icosq(struct mlx5e_icos= q *async_icosq) =20 static int mlx5e_open_queues(struct mlx5e_channel *c, struct mlx5e_params *params, - struct mlx5e_channel_param *cparam) + struct mlx5e_channel_param *cparam, + bool async_icosq_needed) { const struct net_device_ops *netdev_ops =3D c->netdev->netdev_ops; struct dim_cq_moder icocq_moder =3D {0, 0}; @@ -2669,10 +2670,13 @@ static int mlx5e_open_queues(struct mlx5e_channel *= c, if (err) goto err_close_rx_cq; =20 - c->async_icosq =3D mlx5e_open_async_icosq(c, params, cparam, &ccp); - if (IS_ERR(c->async_icosq)) { - err =3D PTR_ERR(c->async_icosq); - goto err_close_rq_xdpsq_cq; + if (async_icosq_needed) { + c->async_icosq =3D mlx5e_open_async_icosq(c, params, cparam, + &ccp); + if (IS_ERR(c->async_icosq)) { + err =3D PTR_ERR(c->async_icosq); + goto err_close_rq_xdpsq_cq; + } } =20 mutex_init(&c->icosq_recovery_lock); @@ -2709,7 +2713,8 @@ static int mlx5e_open_queues(struct mlx5e_channel *c, mlx5e_close_icosq(&c->icosq); =20 err_close_async_icosq: - mlx5e_close_async_icosq(c->async_icosq); + if (c->async_icosq) + mlx5e_close_async_icosq(c->async_icosq); =20 err_close_rq_xdpsq_cq: if (c->xdp) @@ -2741,7 +2746,8 @@ static void mlx5e_close_queues(struct mlx5e_channel *= c) mlx5e_close_sqs(c); mlx5e_close_icosq(&c->icosq); mutex_destroy(&c->icosq_recovery_lock); - mlx5e_close_async_icosq(c->async_icosq); + if (c->async_icosq) + mlx5e_close_async_icosq(c->async_icosq); if (c->xdp) mlx5e_close_cq(&c->rq_xdpsq.cq); mlx5e_close_cq(&c->rq.cq); @@ -2827,6 +2833,7 @@ static int mlx5e_open_channel(struct mlx5e_priv *priv= , int ix, struct mlx5e_channel_param *cparam; struct mlx5_core_dev *mdev; struct mlx5e_xsk_param xsk; + bool async_icosq_needed; struct mlx5e_channel *c; unsigned int irq; int vec_ix; @@ -2876,7 +2883,8 @@ static int mlx5e_open_channel(struct mlx5e_priv *priv= , int ix, netif_napi_add_config_locked(netdev, &c->napi, mlx5e_napi_poll, ix); netif_napi_set_irq_locked(&c->napi, irq); =20 - err =3D mlx5e_open_queues(c, params, cparam); + async_icosq_needed =3D !!xsk_pool || priv->ktls_rx_was_enabled; + err =3D mlx5e_open_queues(c, params, cparam, async_icosq_needed); if (unlikely(err)) goto err_napi_del; =20 @@ -2914,7 +2922,8 @@ static void mlx5e_activate_channel(struct mlx5e_chann= el *c) for (tc =3D 0; tc < c->num_tc; tc++) mlx5e_activate_txqsq(&c->sq[tc]); mlx5e_activate_icosq(&c->icosq); - mlx5e_activate_icosq(c->async_icosq); + if (c->async_icosq) + mlx5e_activate_icosq(c->async_icosq); =20 if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state)) mlx5e_activate_xsk(c); @@ -2935,7 +2944,8 @@ static void mlx5e_deactivate_channel(struct mlx5e_cha= nnel *c) else mlx5e_deactivate_rq(&c->rq); =20 - mlx5e_deactivate_icosq(c->async_icosq); + if (c->async_icosq) + mlx5e_deactivate_icosq(c->async_icosq); mlx5e_deactivate_icosq(&c->icosq); for (tc =3D 0; tc < c->num_tc; tc++) mlx5e_deactivate_txqsq(&c->sq[tc]); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_txrx.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/en_txrx.c index 57c54265dbda..ec7391f38642 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_txrx.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_txrx.c @@ -180,7 +180,7 @@ int mlx5e_napi_poll(struct napi_struct *napi, int budge= t) busy |=3D work_done =3D=3D budget; =20 mlx5e_poll_ico_cq(&c->icosq.cq); - if (mlx5e_poll_ico_cq(&c->async_icosq->cq)) + if (c->async_icosq && mlx5e_poll_ico_cq(&c->async_icosq->cq)) /* Don't clear the flag if nothing was polled to prevent * queueing more WQEs and overflowing the async ICOSQ. */ @@ -237,7 +237,8 @@ int mlx5e_napi_poll(struct napi_struct *napi, int budge= t) =20 mlx5e_cq_arm(&rq->cq); mlx5e_cq_arm(&c->icosq.cq); - mlx5e_cq_arm(&c->async_icosq->cq); + if (c->async_icosq) + mlx5e_cq_arm(&c->async_icosq->cq); if (c->xdpsq) mlx5e_cq_arm(&c->xdpsq->cq); =20 --=20 2.31.1