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Sun, 9 Nov 2025 01:49:35 -0800 From: Tariq Toukan To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Leon Romanovsky , Jason Gunthorpe , "Saeed Mahameed" , Tariq Toukan , Mark Bloch , Dragos Tatulea , "Michael S. Tsirkin" , Jason Wang , , , , , Gal Pressman , Leon Romanovsky , Edward Srouji , Moshe Shemesh , Akiva Goldberger Subject: [PATCH net] mlx5: Fix default values in create CQ Date: Sun, 9 Nov 2025 11:49:03 +0200 Message-ID: <1762681743-1084694-1-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF0000343D:EE_|SA5PPFE494AA682:EE_ X-MS-Office365-Filtering-Correlation-Id: dce17594-8af9-43ea-c39c-08de1f754f6b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|82310400026|36860700013|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?m1cEZQaKMaulNaDvwCzPRw7suL4ueafSUVqffwISX+rWwZ7xlRUOhXqcRCEo?= =?us-ascii?Q?izEJyFuj6lRtOcdNqVY27ApZIKbl/mB9R4U/pGRyNrKgGaH0E0BrTcK/UU1C?= =?us-ascii?Q?FVKg18LE0ZpMUHiSn6Q+8Q1g3oc5Su3FMivZnYhK3taPRqFRuv/sqNU9/Pj4?= =?us-ascii?Q?rV6oFlqxXzvlb0LJpx24dMU6ZTuEopMo7VstGNjViyiK/FxxzzqKRkQMHnk/?= =?us-ascii?Q?w3SoAa6cC0FDUlbrH3tEwol6QGl8pACbct1XL/McCRRviHn69sf4LZDDCU+o?= =?us-ascii?Q?d4Xy3ttwH+sEH8iEFXuAVT2wFj9HMO2JsDbPmo8iDQD0icjycK7hWVdBfjNt?= =?us-ascii?Q?5rAyLvLThZ9IYbWzRdHE+5EBGClpLJQikFP36JFyjZc3cP7H03D+hwCsX1am?= =?us-ascii?Q?sdmB67PmbxnzPnDfwUKUTmV9caAnd0SApjy6ymvVRQ6LvI3HTy9hSd62P4fa?= =?us-ascii?Q?7vqXTaHujZNi9yUaR95qwUeLBlpmgRyokYf7gohkGw5B1wMxQ6CmqtCxMS9l?= =?us-ascii?Q?A0i37cE36KxITmfm3WMbBzNm+pBIB4IgjBkF2Z+vPZQdJxflIgUYiA/fXko4?= =?us-ascii?Q?QCLCtzx+HxabZ5lHzdbp09HpdgSXh+757QqcsJK6rEs/7D2wAIO0zuNGW4uL?= =?us-ascii?Q?s3YjoN28B7ZLh4llGqD+93ZqV0tQkcjiI/B2Lc63RJOGji801QbuRqIEzWnQ?= =?us-ascii?Q?JWo/4oIvMXEa5kQtCKnf0DPmOt8RP8G9aOu6Ya0/SMZQcZPu1N+Ved8DmB4N?= =?us-ascii?Q?JQPs041ZQNIXzuuUxFSCcdDLrqyOGSBeYx/+P883n8Fk+ls5PIsPVe4spOwx?= =?us-ascii?Q?Sz7gw8As4TE8Hcy7VN1Nae4fUk/ws4n+nybIa4VEPvRRpsBGYcOqD/BS+Vib?= =?us-ascii?Q?R1geE7/pSIa0+C6qS46jUwQrEUlRvLT0lSxfa3vCEGQQ9amgTvlkIcD223oU?= =?us-ascii?Q?yT/zBC/G9EQOYcPXk75X0b+kwaHd8AhHUvLYeYtb5fWbF6XhAdbybC/5DgJ2?= =?us-ascii?Q?ep2lEw7rxSPc/yi1M+w9d07dOzXUBscaqU1q0fc1FzBtj5oYibcq3Hq/HYIY?= =?us-ascii?Q?yXJIhHWJk9KoF5fcB4BGSeZQyMb/EA5oGH7aBeDm9+zDrbLUbZzf+5DK1ydv?= =?us-ascii?Q?PBCOP6WXOr6jwsA3GE7uX63401uuBHnnTF3ZJ1zZkn25d8H7UIvkHgABEHf9?= =?us-ascii?Q?TfbFdgfVv4/1ObBPwidm1GfCfftbdncR8F1eXtR0loAHWPm/fRLGNMh57Xpb?= =?us-ascii?Q?PE0IUT39dyeOgih6dHj+rHvK6P4nSfvdhtNf6Pw+JSRoAy6l0ONmi2pwKEv7?= =?us-ascii?Q?M5I9+3EVxPuw8PVebPeZa9pxFQWgwcJ/xpWP+ZHdvRuZVAu7wB6YJ2VMRdv5?= =?us-ascii?Q?MYfetNfYLTkEvoAga4NQx/1CL+ZnkDVqdVYE81+AAhG05AErR6CwvtSEjG54?= =?us-ascii?Q?ATL8pnnlNPkd60nDjzUAI7BzftEL3eu9j11O7rRPG3oz3RHqXgisiGhBfOUm?= =?us-ascii?Q?GajMOO/w/FjqFXF0G+JcjawzeSA8nlUQorWgOfiWd84R1j501ebFWqZANqtZ?= =?us-ascii?Q?uvw/8lFx770Z3efBtrQ=3D?= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(7416014)(82310400026)(36860700013)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Nov 2025 09:49:43.6022 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: dce17594-8af9-43ea-c39c-08de1f754f6b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF0000343D.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA5PPFE494AA682 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Akiva Goldberger Currently, CQs without a completion function are assigned the mlx5_add_cq_to_tasklet function by default. This is problematic since only user CQs created through the mlx5_ib driver are intended to use this function. Additionally, all CQs that will use doorbells instead of polling for completions must call mlx5_cq_arm. However, the default CQ creation flow leaves a valid value in the CQ's arm_db field, allowing FW to send interrupts to polling-only CQs in certain corner cases. These two factors would allow a polling-only kernel CQ to be triggered by an EQ interrupt and call a completion function intended only for user CQs, causing a null pointer exception. Some areas in the driver have prevented this issue with one-off fixes but did not address the root cause. This patch fixes the described issue by adding defaults to the create CQ flow. It adds a default dummy completion function to protect against null pointer exceptions, and it sets an invalid command sequence number by default in kernel CQs to prevent the FW from sending an interrupt to the CQ until it is armed. User CQs are responsible for their own initialization values. Callers of mlx5_core_create_cq are responsible for changing the completion function and arming the CQ per their needs. Fixes: cdd04f4d4d71 ("net/mlx5: Add support to create SQ and CQ for ASO") Signed-off-by: Akiva Goldberger Reviewed-by: Moshe Shemesh Signed-off-by: Tariq Toukan Acked-by: Leon Romanovsky --- drivers/infiniband/hw/mlx5/cq.c | 11 +++++--- drivers/net/ethernet/mellanox/mlx5/core/cq.c | 23 +++++++++++++-- .../net/ethernet/mellanox/mlx5/core/en_main.c | 1 - .../ethernet/mellanox/mlx5/core/fpga/conn.c | 15 +++++----- .../mellanox/mlx5/core/steering/hws/send.c | 7 ----- .../mellanox/mlx5/core/steering/sws/dr_send.c | 28 +++++-------------- drivers/vdpa/mlx5/net/mlx5_vnet.c | 6 ++-- include/linux/mlx5/cq.h | 1 + 8 files changed, 44 insertions(+), 48 deletions(-) diff --git a/drivers/infiniband/hw/mlx5/cq.c b/drivers/infiniband/hw/mlx5/c= q.c index a23b364e24ff..651d76bca114 100644 --- a/drivers/infiniband/hw/mlx5/cq.c +++ b/drivers/infiniband/hw/mlx5/cq.c @@ -1020,15 +1020,18 @@ int mlx5_ib_create_cq(struct ib_cq *ibcq, const str= uct ib_cq_init_attr *attr, if (cq->create_flags & IB_UVERBS_CQ_FLAGS_IGNORE_OVERRUN) MLX5_SET(cqc, cqc, oi, 1); =20 + if (udata) { + cq->mcq.comp =3D mlx5_add_cq_to_tasklet; + cq->mcq.tasklet_ctx.comp =3D mlx5_ib_cq_comp; + } else { + cq->mcq.comp =3D mlx5_ib_cq_comp; + } + err =3D mlx5_core_create_cq(dev->mdev, &cq->mcq, cqb, inlen, out, sizeof(= out)); if (err) goto err_cqb; =20 mlx5_ib_dbg(dev, "cqn 0x%x\n", cq->mcq.cqn); - if (udata) - cq->mcq.tasklet_ctx.comp =3D mlx5_ib_cq_comp; - else - cq->mcq.comp =3D mlx5_ib_cq_comp; cq->mcq.event =3D mlx5_ib_cq_event; =20 INIT_LIST_HEAD(&cq->wc_list); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/cq.c b/drivers/net/eth= ernet/mellanox/mlx5/core/cq.c index e9f319a9bdd6..60f7ab1d72e7 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/cq.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/cq.c @@ -66,8 +66,8 @@ void mlx5_cq_tasklet_cb(struct tasklet_struct *t) tasklet_schedule(&ctx->task); } =20 -static void mlx5_add_cq_to_tasklet(struct mlx5_core_cq *cq, - struct mlx5_eqe *eqe) +void mlx5_add_cq_to_tasklet(struct mlx5_core_cq *cq, + struct mlx5_eqe *eqe) { unsigned long flags; struct mlx5_eq_tasklet *tasklet_ctx =3D cq->tasklet_ctx.priv; @@ -95,7 +95,15 @@ static void mlx5_add_cq_to_tasklet(struct mlx5_core_cq *= cq, if (schedule_tasklet) tasklet_schedule(&tasklet_ctx->task); } +EXPORT_SYMBOL(mlx5_add_cq_to_tasklet); =20 +static void mlx5_core_cq_dummy_cb(struct mlx5_core_cq *cq, struct mlx5_eqe= *eqe) +{ + mlx5_core_err(cq->eq->core.dev, + "CQ default completion callback, CQ #%u\n", cq->cqn); +} + +#define MLX5_CQ_INIT_CMD_SN cpu_to_be32(2 << 28) /* Callers must verify outbox status in case of err */ int mlx5_create_cq(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq, u32 *in, int inlen, u32 *out, int outlen) @@ -121,10 +129,19 @@ int mlx5_create_cq(struct mlx5_core_dev *dev, struct = mlx5_core_cq *cq, cq->arm_sn =3D 0; cq->eq =3D eq; cq->uid =3D MLX5_GET(create_cq_in, in, uid); + + /* Kernel CQs must set the arm_db address prior to calling + * this function, allowing for the proper value to be + * initialized. User CQs are responsible for their own + * initialization since they do not use the arm_db field. + */ + if (cq->arm_db) + *cq->arm_db =3D MLX5_CQ_INIT_CMD_SN; + refcount_set(&cq->refcount, 1); init_completion(&cq->free); if (!cq->comp) - cq->comp =3D mlx5_add_cq_to_tasklet; + cq->comp =3D mlx5_core_cq_dummy_cb; /* assuming CQ will be deleted before the EQ */ cq->tasklet_ctx.priv =3D &eq->tasklet_ctx; INIT_LIST_HEAD(&cq->tasklet_ctx.list); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/en_main.c index 6023bbbf3f39..5e17eae81f4b 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c @@ -2219,7 +2219,6 @@ static int mlx5e_alloc_cq_common(struct mlx5_core_dev= *mdev, mcq->set_ci_db =3D cq->wq_ctrl.db.db; mcq->arm_db =3D cq->wq_ctrl.db.db + 1; *mcq->set_ci_db =3D 0; - *mcq->arm_db =3D 0; mcq->vector =3D param->eq_ix; mcq->comp =3D mlx5e_completion_event; mcq->event =3D mlx5e_cq_error_event; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/fpga/conn.c b/drivers/= net/ethernet/mellanox/mlx5/core/fpga/conn.c index cb1319974f83..ccef64fb40b6 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/fpga/conn.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/fpga/conn.c @@ -421,6 +421,13 @@ static int mlx5_fpga_conn_create_cq(struct mlx5_fpga_c= onn *conn, int cq_size) __be64 *pas; u32 i; =20 + conn->cq.mcq.cqe_sz =3D 64; + conn->cq.mcq.set_ci_db =3D conn->cq.wq_ctrl.db.db; + conn->cq.mcq.arm_db =3D conn->cq.wq_ctrl.db.db + 1; + *conn->cq.mcq.set_ci_db =3D 0; + conn->cq.mcq.vector =3D 0; + conn->cq.mcq.comp =3D mlx5_fpga_conn_cq_complete; + cq_size =3D roundup_pow_of_two(cq_size); MLX5_SET(cqc, temp_cqc, log_cq_size, ilog2(cq_size)); =20 @@ -468,15 +475,7 @@ static int mlx5_fpga_conn_create_cq(struct mlx5_fpga_c= onn *conn, int cq_size) if (err) goto err_cqwq; =20 - conn->cq.mcq.cqe_sz =3D 64; - conn->cq.mcq.set_ci_db =3D conn->cq.wq_ctrl.db.db; - conn->cq.mcq.arm_db =3D conn->cq.wq_ctrl.db.db + 1; - *conn->cq.mcq.set_ci_db =3D 0; - *conn->cq.mcq.arm_db =3D 0; - conn->cq.mcq.vector =3D 0; - conn->cq.mcq.comp =3D mlx5_fpga_conn_cq_complete; tasklet_setup(&conn->cq.tasklet, mlx5_fpga_conn_cq_tasklet); - mlx5_fpga_dbg(fdev, "Created CQ #0x%x\n", conn->cq.mcq.cqn); =20 goto out; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/send.c b/= drivers/net/ethernet/mellanox/mlx5/core/steering/hws/send.c index 24ef7d66fa8a..7510c46e58a5 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/send.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/send.c @@ -873,12 +873,6 @@ static int hws_send_ring_open_sq(struct mlx5hws_contex= t *ctx, return err; } =20 -static void hws_cq_complete(struct mlx5_core_cq *mcq, - struct mlx5_eqe *eqe) -{ - pr_err("CQ completion CQ: #%u\n", mcq->cqn); -} - static int hws_send_ring_alloc_cq(struct mlx5_core_dev *mdev, int numa_node, struct mlx5hws_send_engine *queue, @@ -901,7 +895,6 @@ static int hws_send_ring_alloc_cq(struct mlx5_core_dev = *mdev, mcq->cqe_sz =3D 64; mcq->set_ci_db =3D cq->wq_ctrl.db.db; mcq->arm_db =3D cq->wq_ctrl.db.db + 1; - mcq->comp =3D hws_cq_complete; =20 for (i =3D 0; i < mlx5_cqwq_get_size(&cq->wq); i++) { cqe =3D mlx5_cqwq_get_wqe(&cq->wq, i); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/sws/dr_send.c= b/drivers/net/ethernet/mellanox/mlx5/core/steering/sws/dr_send.c index 077a77fde670..d034372fa047 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/sws/dr_send.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/sws/dr_send.c @@ -1049,12 +1049,6 @@ static int dr_prepare_qp_to_rts(struct mlx5dr_domain= *dmn) return 0; } =20 -static void dr_cq_complete(struct mlx5_core_cq *mcq, - struct mlx5_eqe *eqe) -{ - pr_err("CQ completion CQ: #%u\n", mcq->cqn); -} - static struct mlx5dr_cq *dr_create_cq(struct mlx5_core_dev *mdev, struct mlx5_uars_page *uar, size_t ncqe) @@ -1089,6 +1083,13 @@ static struct mlx5dr_cq *dr_create_cq(struct mlx5_co= re_dev *mdev, cqe->op_own =3D MLX5_CQE_INVALID << 4 | MLX5_CQE_OWNER_MASK; } =20 + cq->mcq.cqe_sz =3D 64; + cq->mcq.set_ci_db =3D cq->wq_ctrl.db.db; + cq->mcq.arm_db =3D cq->wq_ctrl.db.db + 1; + *cq->mcq.set_ci_db =3D 0; + cq->mcq.vector =3D 0; + cq->mdev =3D mdev; + inlen =3D MLX5_ST_SZ_BYTES(create_cq_in) + sizeof(u64) * cq->wq_ctrl.buf.npages; in =3D kvzalloc(inlen, GFP_KERNEL); @@ -1112,27 +1113,12 @@ static struct mlx5dr_cq *dr_create_cq(struct mlx5_c= ore_dev *mdev, pas =3D (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas); mlx5_fill_page_frag_array(&cq->wq_ctrl.buf, pas); =20 - cq->mcq.comp =3D dr_cq_complete; - err =3D mlx5_core_create_cq(mdev, &cq->mcq, in, inlen, out, sizeof(out)); kvfree(in); =20 if (err) goto err_cqwq; =20 - cq->mcq.cqe_sz =3D 64; - cq->mcq.set_ci_db =3D cq->wq_ctrl.db.db; - cq->mcq.arm_db =3D cq->wq_ctrl.db.db + 1; - *cq->mcq.set_ci_db =3D 0; - - /* set no-zero value, in order to avoid the HW to run db-recovery on - * CQ that used in polling mode. - */ - *cq->mcq.arm_db =3D cpu_to_be32(2 << 28); - - cq->mcq.vector =3D 0; - cq->mdev =3D mdev; - return cq; =20 err_cqwq: diff --git a/drivers/vdpa/mlx5/net/mlx5_vnet.c b/drivers/vdpa/mlx5/net/mlx5= _vnet.c index 82034efb74fc..a7936bd1aabe 100644 --- a/drivers/vdpa/mlx5/net/mlx5_vnet.c +++ b/drivers/vdpa/mlx5/net/mlx5_vnet.c @@ -573,6 +573,8 @@ static int cq_create(struct mlx5_vdpa_net *ndev, u16 id= x, u32 num_ent) vcq->mcq.set_ci_db =3D vcq->db.db; vcq->mcq.arm_db =3D vcq->db.db + 1; vcq->mcq.cqe_sz =3D 64; + vcq->mcq.comp =3D mlx5_vdpa_cq_comp; + vcq->cqe =3D num_ent; =20 err =3D cq_frag_buf_alloc(ndev, &vcq->buf, num_ent); if (err) @@ -612,10 +614,6 @@ static int cq_create(struct mlx5_vdpa_net *ndev, u16 i= dx, u32 num_ent) if (err) goto err_vec; =20 - vcq->mcq.comp =3D mlx5_vdpa_cq_comp; - vcq->cqe =3D num_ent; - vcq->mcq.set_ci_db =3D vcq->db.db; - vcq->mcq.arm_db =3D vcq->db.db + 1; mlx5_cq_arm(&mvq->cq.mcq, MLX5_CQ_DB_REQ_NOT, uar_page, mvq->cq.mcq.cons_= index); kfree(in); return 0; diff --git a/include/linux/mlx5/cq.h b/include/linux/mlx5/cq.h index 7ef2c7c7d803..9d47cdc727ad 100644 --- a/include/linux/mlx5/cq.h +++ b/include/linux/mlx5/cq.h @@ -183,6 +183,7 @@ static inline void mlx5_cq_put(struct mlx5_core_cq *cq) complete(&cq->free); } =20 +void mlx5_add_cq_to_tasklet(struct mlx5_core_cq *cq, struct mlx5_eqe *eqe); int mlx5_create_cq(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq, u32 *in, int inlen, u32 *out, int outlen); int mlx5_core_create_cq(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq, base-commit: 96a9178a29a6b84bb632ebeb4e84cf61191c73d5 --=20 2.31.1