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Sun, 28 Jul 2024 15:45:01 -0700 From: Nicolin Chen To: CC: , , , , , , , , , Subject: [PATCH v10 2/9] iommu/arm-smmu-v3: Enforce arm_smmu_cmdq_build_sync_cmd Date: Sun, 28 Jul 2024 15:44:47 -0700 Message-ID: <176261860828f690958d93edf53569ca2505680c.1722206275.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWH0EPF000A672F:EE_|IA0PR12MB8349:EE_ X-MS-Office365-Filtering-Correlation-Id: 836de568-628c-49fa-6583-08dcaf56eee7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|376014|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?iEP1nUw6G8yXzQMT0pdPbuojGIMPmhZVs5K48QNxPr6iXNrjONLMReeRUnrE?= =?us-ascii?Q?XXlO7MrFZvSMb3LA/ve/kc/QLHX+jVKOe2A4xDHxDJQodNnLyB6RvaxPXJHt?= =?us-ascii?Q?Eul1Aj20X30CgdthG0kXyHaOW9gFr4Dnep6OtjPJDO14idwrUlPDlEL0GnqP?= =?us-ascii?Q?XPNIA26Pdg/T33xKaSsRgeQ3WYNnxPTejq5QVMwByIxFUSkGFAf3aNHr3FPS?= =?us-ascii?Q?cebuLk5s9LDlUC+CkQtYMA2gc4Csv9VBzul2rwND6tvnPGOWgdnlaO3d7Zzb?= =?us-ascii?Q?zfG6YkdDf16h+6404aLuOMZLNWWAzSSClobjF3JGd+f9w/iNbAHEFMYre3oo?= =?us-ascii?Q?uoT9i0N3mIx2H2zWTI66R5pwQDLqBVth4xV2D4ABKh+4QJzgG44AK6H2s1/8?= =?us-ascii?Q?DajzjU9Dli9QoGFLnltyH0HErkPDNXFT8DIOP3/QcsFtXzu3HCzPVZnKVE5W?= =?us-ascii?Q?OgdV8RP2fNXKt2p6PEFJxAvRkjLrg0hs33SpiVfFEJnjw9YuQdGthitxp9oM?= =?us-ascii?Q?u85gaLF7ALN8tAK8Z7PV2u4ZB6KlK3lSYgKHfc7mBLmkzQ6GsvkKofK3LYqd?= =?us-ascii?Q?Sl+DOqt/ZsmW81RJBEKBDDzyDcc1myogrtdanbhegZc59DlyFMjuyjSgD7E3?= =?us-ascii?Q?Vsq66vRFpCe541HOATIb770QJR63HOe7l2kkrerr+3Uv5fLGdMszJOOtPNCV?= =?us-ascii?Q?m3HE1naBeQDB8LkXyaVFE6IseAWOHkzDJbhgSYEj37IoB1kktCxJWO7FEIUW?= =?us-ascii?Q?JFCX/b3k7uIB+GBYy7rBa2OhrID4zO6eYHjQFrW1ujTeyXMWOroOTgu+RFMm?= =?us-ascii?Q?76S9XKbNjlx8eteaV6hg8yzKQHnT991Q+bSr1NPyEEVwJlP9oM9E3uw3WxRe?= =?us-ascii?Q?S+DMHCyF4n0Xo/IeR+RZzgpRohJPW/RHCKOgOlpL7MCj27aMvLEN+4l3M9ry?= =?us-ascii?Q?rtJzCey/jgsGO0IV0m4YLJ1eaBcZ7B+MfMdRU4CbtOFqTpCkqsJCj9nN7HOb?= =?us-ascii?Q?lZPAq/q2zIit+zfmWV1O7RVm5MiccU5hSn+DNGlNx6Xw44rFc8OP3z6pclH9?= =?us-ascii?Q?kk2yC13qY0dQxQqayrJ1gK39Gck+gyadZPEDAsS/G3fcpY22RKNFAu3fFrJj?= =?us-ascii?Q?wqURKSju2fpN2UR2K+r+EZQr9IqOjIxT02RpiW8b1A9gkixNmH6PqWDbx6xK?= =?us-ascii?Q?YVojMrnbs16FhuVy55jKO9d+5p4/RYKaGgqZpMnfzU2EG2B22qNxRAt9p0wW?= =?us-ascii?Q?OYHBdGM6jqSM/QoyyS/auI5w405TLAlZRtSBw9gLwDWan0qmGe0+4bc2xuUo?= =?us-ascii?Q?LqLH8Z29A6bJm3SDibXg97wT5BshxOAhsmcVmwCh/8DIxo7hzpbZkU0kbZz9?= =?us-ascii?Q?4msJ+4FfQWMy4uAWNJc35Nv4TAd5bWDbHwVJPPszDFYpjRYEv87akYu1Id+x?= =?us-ascii?Q?3g85a0WyLcdLvjKiv/IcpfmK0cHggwYP?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(1800799024)(376014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Jul 2024 22:45:08.9176 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 836de568-628c-49fa-6583-08dcaf56eee7 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000A672F.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB8349 Content-Type: text/plain; charset="utf-8" There is an existing arm_smmu_cmdq_build_sync_cmd() so the driver should call it at all places other than going through arm_smmu_cmdq_build_cmd() separately. This helps the following patch that adds a CS_NONE option. Note that this changes the type of CMD_SYNC in __arm_smmu_cmdq_skip_err, in ARM_SMMU_OPT_MSIPOLL=3Dtrue case, from previously a non-MSI one to now an MSI one that is proven to still work using a hacking test: nvme: Adding to iommu group 10 nvme: --------hacking----------- arm-smmu-v3: unexpected global error reported (0x00000001), this could be serious arm-smmu-v3: CMDQ error (cons 0x01000022): Illegal command arm-smmu-v3: skipping command in error state: arm-smmu-v3: 0x0000000000000000 arm-smmu-v3: 0x0000000000000000 nvme: -------recovered---------- nvme nvme0: 72/0/0 default/read/poll queues nvme0n1: p1 p2 Suggested-by: Jason Gunthorpe Reviewed-by: Jason Gunthorpe Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 36 ++++++++------------- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 3 -- 2 files changed, 13 insertions(+), 26 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index f409ead589ffc..f481d7be3d4ec 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -329,16 +329,6 @@ static int arm_smmu_cmdq_build_cmd(u64 *cmd, struct ar= m_smmu_cmdq_ent *ent) cmd[0] |=3D FIELD_PREP(CMDQ_RESUME_0_RESP, ent->resume.resp); cmd[1] |=3D FIELD_PREP(CMDQ_RESUME_1_STAG, ent->resume.stag); break; - case CMDQ_OP_CMD_SYNC: - if (ent->sync.msiaddr) { - cmd[0] |=3D FIELD_PREP(CMDQ_SYNC_0_CS, CMDQ_SYNC_0_CS_IRQ); - cmd[1] |=3D ent->sync.msiaddr & CMDQ_SYNC_1_MSIADDR_MASK; - } else { - cmd[0] |=3D FIELD_PREP(CMDQ_SYNC_0_CS, CMDQ_SYNC_0_CS_SEV); - } - cmd[0] |=3D FIELD_PREP(CMDQ_SYNC_0_MSH, ARM_SMMU_SH_ISH); - cmd[0] |=3D FIELD_PREP(CMDQ_SYNC_0_MSIATTR, ARM_SMMU_MEMATTR_OIWB); - break; default: return -ENOENT; } @@ -354,20 +344,23 @@ static struct arm_smmu_cmdq *arm_smmu_get_cmdq(struct= arm_smmu_device *smmu) static void arm_smmu_cmdq_build_sync_cmd(u64 *cmd, struct arm_smmu_device = *smmu, struct arm_smmu_queue *q, u32 prod) { - struct arm_smmu_cmdq_ent ent =3D { - .opcode =3D CMDQ_OP_CMD_SYNC, - }; + cmd[1] =3D 0; + cmd[0] =3D FIELD_PREP(CMDQ_0_OP, CMDQ_OP_CMD_SYNC) | + FIELD_PREP(CMDQ_SYNC_0_MSH, ARM_SMMU_SH_ISH) | + FIELD_PREP(CMDQ_SYNC_0_MSIATTR, ARM_SMMU_MEMATTR_OIWB); + + if (!(smmu->options & ARM_SMMU_OPT_MSIPOLL)) { + cmd[0] |=3D FIELD_PREP(CMDQ_SYNC_0_CS, CMDQ_SYNC_0_CS_SEV); + return; + } =20 /* * Beware that Hi16xx adds an extra 32 bits of goodness to its MSI * payload, so the write will zero the entire command on that platform. */ - if (smmu->options & ARM_SMMU_OPT_MSIPOLL) { - ent.sync.msiaddr =3D q->base_dma + Q_IDX(&q->llq, prod) * - q->ent_dwords * 8; - } - - arm_smmu_cmdq_build_cmd(cmd, &ent); + cmd[0] |=3D FIELD_PREP(CMDQ_SYNC_0_CS, CMDQ_SYNC_0_CS_IRQ); + cmd[1] |=3D (q->base_dma + Q_IDX(&q->llq, prod) * q->ent_dwords * 8) & + CMDQ_SYNC_1_MSIADDR_MASK; } =20 static void __arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu, @@ -384,9 +377,6 @@ static void __arm_smmu_cmdq_skip_err(struct arm_smmu_de= vice *smmu, u64 cmd[CMDQ_ENT_DWORDS]; u32 cons =3D readl_relaxed(q->cons_reg); u32 idx =3D FIELD_GET(CMDQ_CONS_ERR, cons); - struct arm_smmu_cmdq_ent cmd_sync =3D { - .opcode =3D CMDQ_OP_CMD_SYNC, - }; =20 dev_err(smmu->dev, "CMDQ error (cons 0x%08x): %s\n", cons, idx < ARRAY_SIZE(cerror_str) ? cerror_str[idx] : "Unknown"); @@ -420,7 +410,7 @@ static void __arm_smmu_cmdq_skip_err(struct arm_smmu_de= vice *smmu, dev_err(smmu->dev, "\t0x%016llx\n", (unsigned long long)cmd[i]); =20 /* Convert the erroneous command into a CMD_SYNC */ - arm_smmu_cmdq_build_cmd(cmd, &cmd_sync); + arm_smmu_cmdq_build_sync_cmd(cmd, smmu, q, cons); =20 queue_write(Q_ENT(q, cons), cmd, q->ent_dwords); } diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index c1454e9758c48..6c5739f6b90f5 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -518,9 +518,6 @@ struct arm_smmu_cmdq_ent { } resume; =20 #define CMDQ_OP_CMD_SYNC 0x46 - struct { - u64 msiaddr; - } sync; }; }; =20 --=20 2.43.0