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Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , , , , Gal Pressman , Dragos Tatulea Subject: [PATCH net 1/3] net/mlx5e: SHAMPO, Fix header mapping for 64K pages Date: Tue, 28 Oct 2025 08:47:17 +0200 Message-ID: <1761634039-999515-2-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1761634039-999515-1-git-send-email-tariqt@nvidia.com> References: <1761634039-999515-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00002316:EE_|IA1PR12MB9529:EE_ X-MS-Office365-Filtering-Correlation-Id: 05ad7b44-c53a-4724-0d3f-08de15ededef X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|376014|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?m6cAcM2RcCJQRfLXbcJ+Nici08pm60CEKImOpKYEA1kydSsUtjCCm4TTXAWu?= =?us-ascii?Q?/9F8bCkyCUzFeppL5JlpEr9Zduz/b7RxWJX4ppBbt1QqemDDv4iVJRmqRBo8?= =?us-ascii?Q?u7hwZKH6SiWWNogGBIRk2B0f9zrX4dpZIJRTA5i+DbMIbvNSSDzb+9ieO4Av?= =?us-ascii?Q?wjwVzVWrHBBooQjlSglP8KIMryCzbp7DPtQB74fiRR0NvukY/wZ4PnB9+n8d?= =?us-ascii?Q?2iJvG03a7LEYd/QZFqQ01LVape8UAozaRkcznKnQbtNCul7C4A9Bu9w5Tr23?= =?us-ascii?Q?okvTKJkB44V8DsjMlV6eeNCazkga25wCESRXUUUUMdn0G4zQ2KoYWvrLUOnL?= =?us-ascii?Q?NMZRocRpx4q8GY5bPeSo7C6zY6zXtOsbsOBiEvodbvh2aJN8KrRnyTx2+j81?= =?us-ascii?Q?JMo54O8OphMailB3p/S4kXjq3CGEhd4wMWEq3kUxS7tmQLF2H206rebfV8IO?= =?us-ascii?Q?Qp3T7oALGZh+E/gmW+dg5H9cy2eJcWj2Rpjss1NQCQukAV0724oKaVNsf1Cs?= =?us-ascii?Q?27MdQSNATMgp5Cg68HxCqMOOgZXBbCOa0MW2ASAOt1/5eb6VujdhOF25IjxQ?= =?us-ascii?Q?SDUTHBWkooXapxRaQ0MF4yP/tUFG0Y20uEmDQLjFjYydZxn6uGDPVgud14cy?= =?us-ascii?Q?Zs19odwRB4xssgxN0tQbEu8sJUXNWIWzOAsg1kBMkVhs2RUY5trg6UnQPgPz?= =?us-ascii?Q?1Ztvve1wYiKFZnQjqvfQnEFj69sbBmahJetS3evOMwQZsRaHtqLW3IWJDPwG?= =?us-ascii?Q?tlUX4zy/wT7BfVtkOyVDWXYIER3lcbO7UVCus5T/Eq/Wws1pUers2ZGxu2Sx?= =?us-ascii?Q?lePPA+PzGiHjOx5yBNugFLgRHS/4PDIqD1ZiyZE7nGFNWH9Bd/e4/Keb/5Sx?= =?us-ascii?Q?A1e8+YxJ5fFbY6H92D0mBwq0G7u9J4v5Zf4kyq1xfLNL2OQw335vCKMA99qu?= =?us-ascii?Q?/LcTrI33x+Y6f3ez6ByUOlOB4Jr5etF2Sj2qjroguuaet+PKPIyeMwfC4J7f?= =?us-ascii?Q?zN63QAPShxwgkvsvCoYtE04LZ3+RqBMkIoBmzGk6kzSjuRiOhloWDhLKeZKE?= =?us-ascii?Q?60unCwN/TGdlaEw0eqDgmN2+x/xIxk7RvisU8JgzayR0BN1PlRaBQi28iylX?= =?us-ascii?Q?UKSF1ai+vzbeVABAVZjcBMhAPM6BvHcbpqkTLAOIlHUtooW+w9TF3YNAYQcc?= =?us-ascii?Q?JCqFslOJGiva1y11xGvy++Uun21NxPT1RS/zbqUQSf5Sk57nk7rFVN9i0cLz?= =?us-ascii?Q?TAisge45AL9H3OKtqBDtloYfoab3e5lL7eg+LtwFL0dEqbNCtzRLke3amUdE?= =?us-ascii?Q?hTuDcKAxFELAQEPy+4fglqQYlpjT8HjwZTDS+z5RWWryB8tngZ9+THZQWjJt?= =?us-ascii?Q?yHnQJcjhQvBJ6nh0d2DdXJ2OshHCAL0vF9iO0QqOQCOtgzXSKrGNp4avvgJI?= =?us-ascii?Q?JhNZ22aQAc1ONgvMPye8oRy7LrEQxfs3kN7stSxBuE53Ly6+9bDrBRUoouxU?= =?us-ascii?Q?S4SC4bKd3yi/a5oHe2Zp31Pairz2WSWi96U6TY/B+n1+wC+aWEuL1YW2gAjB?= =?us-ascii?Q?rVEZJ+vA03/LjtVZTRI=3D?= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(1800799024)(376014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Oct 2025 06:47:57.6318 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 05ad7b44-c53a-4724-0d3f-08de15ededef X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00002316.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB9529 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Dragos Tatulea HW-GRO is broken on mlx5 for 64K page sizes. The patch in the fixes tag didn't take into account larger page sizes when doing an align down of max_ksm_entries. For 64K page size, max_ksm_entries is 0 which will skip mapping header pages via WQE UMR. This breaks header-data split and will result in the following syndrome: mlx5_core 0000:00:08.0 eth2: Error cqe on cqn 0x4c9, ci 0x0, qn 0x1133, opc= ode 0xe, syndrome 0x4, vendor syndrome 0x32 00000000: 00 00 00 00 04 4a 00 00 00 00 00 00 20 00 93 32 00000010: 55 00 00 00 fb cc 00 00 00 00 00 00 07 18 00 00 00000020: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 4a 00000030: 00 00 3b c7 93 01 32 04 00 00 00 00 00 00 bf e0 mlx5_core 0000:00:08.0 eth2: ERR CQE on RQ: 0x1133 Furthermore, the function that fills in WQE UMRs for the headers (mlx5e_build_shampo_hd_umr()) only supports mapping page sizes that fit in a single UMR WQE. This patch goes back to the old non-aligned max_ksm_entries value and it changes mlx5e_build_shampo_hd_umr() to support mapping a large page over multiple UMR WQEs. This means that mlx5e_build_shampo_hd_umr() can now leave a page only partially mapped. The caller, mlx5e_build_shampo_hd_umr(), ensures that there are enough UMR WQEs to cover complete pages by working on ksm_entries that are multiples of MLX5E_SHAMPO_WQ_HEADER_PER_PAGE. Fixes: 8a0ee54027b1 ("net/mlx5e: SHAMPO, Simplify UMR allocation for header= s") Signed-off-by: Dragos Tatulea Signed-off-by: Tariq Toukan --- .../net/ethernet/mellanox/mlx5/core/en_rx.c | 34 +++++++++---------- 1 file changed, 16 insertions(+), 18 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c b/drivers/net/= ethernet/mellanox/mlx5/core/en_rx.c index 1c79adc51a04..77f7a1ca091d 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c @@ -679,25 +679,24 @@ static int mlx5e_build_shampo_hd_umr(struct mlx5e_rq = *rq, umr_wqe =3D mlx5_wq_cyc_get_wqe(&sq->wq, pi); build_ksm_umr(sq, umr_wqe, shampo->mkey_be, index, ksm_entries); =20 - WARN_ON_ONCE(ksm_entries & (MLX5E_SHAMPO_WQ_HEADER_PER_PAGE - 1)); - while (i < ksm_entries) { - struct mlx5e_frag_page *frag_page =3D mlx5e_shampo_hd_to_frag_page(rq, i= ndex); + for ( ; i < ksm_entries; i++, index++) { + struct mlx5e_frag_page *frag_page; u64 addr; =20 - err =3D mlx5e_page_alloc_fragmented(rq->hd_page_pool, frag_page); - if (unlikely(err)) - goto err_unmap; + frag_page =3D mlx5e_shampo_hd_to_frag_page(rq, index); + header_offset =3D mlx5e_shampo_hd_offset(index); + if (!header_offset) { + err =3D mlx5e_page_alloc_fragmented(rq->hd_page_pool, + frag_page); + if (err) + goto err_unmap; + } =20 addr =3D page_pool_get_dma_addr_netmem(frag_page->netmem); - - for (int j =3D 0; j < MLX5E_SHAMPO_WQ_HEADER_PER_PAGE; j++) { - header_offset =3D mlx5e_shampo_hd_offset(index++); - - umr_wqe->inline_ksms[i++] =3D (struct mlx5_ksm) { - .key =3D cpu_to_be32(lkey), - .va =3D cpu_to_be64(addr + header_offset + headroom), - }; - } + umr_wqe->inline_ksms[i] =3D (struct mlx5_ksm) { + .key =3D cpu_to_be32(lkey), + .va =3D cpu_to_be64(addr + header_offset + headroom), + }; } =20 sq->db.wqe_info[pi] =3D (struct mlx5e_icosq_wqe_info) { @@ -713,7 +712,7 @@ static int mlx5e_build_shampo_hd_umr(struct mlx5e_rq *r= q, return 0; =20 err_unmap: - while (--i) { + while (--i >=3D 0) { --index; header_offset =3D mlx5e_shampo_hd_offset(index); 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This formula is incorrect for 64K page sizes and it triggers early GRO session termination because the first fragment will blow up beyond GRO_LEGACY_MAX_SIZE. This patch adds a special case for page sizes >=3D GRO_LEGACY_MAX_SIZE (64K) which will uses the skb->data_len instead. Within this context, this check will be safe from fragment overflow. It is expected that the if statement will be optimized out as the check is done with constants. Fixes: 92552d3abd32 ("net/mlx5e: HW_GRO cqe handler implementation") Signed-off-by: Dragos Tatulea Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/en_rx.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c b/drivers/net/= ethernet/mellanox/mlx5/core/en_rx.c index 77f7a1ca091d..ea4e7f486c8b 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c @@ -2350,7 +2350,10 @@ mlx5e_hw_gro_skb_has_enough_space(struct sk_buff *sk= b, u16 data_bcnt) { int nr_frags =3D skb_shinfo(skb)->nr_frags; =20 - return PAGE_SIZE * nr_frags + data_bcnt <=3D GRO_LEGACY_MAX_SIZE; + if (PAGE_SIZE >=3D GRO_LEGACY_MAX_SIZE) + return skb->len + data_bcnt <=3D GRO_LEGACY_MAX_SIZE; + else + return PAGE_SIZE * nr_frags + data_bcnt <=3D GRO_LEGACY_MAX_SIZE; } =20 static void mlx5e_handle_rx_cqe_mpwrq_shampo(struct mlx5e_rq *rq, struct m= lx5_cqe64 *cqe) --=20 2.31.1 From nobody Sun Feb 8 01:31:04 2026 Received: from DM5PR21CU001.outbound.protection.outlook.com (mail-centralusazon11011021.outbound.protection.outlook.com [52.101.62.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AB3B72C3244; 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Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , , , , Gal Pressman , Dragos Tatulea Subject: [PATCH net 3/3] net/mlx5e: SHAMPO, Fix header formulas for higher MTUs and 64K pages Date: Tue, 28 Oct 2025 08:47:19 +0200 Message-ID: <1761634039-999515-4-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1761634039-999515-1-git-send-email-tariqt@nvidia.com> References: <1761634039-999515-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MN1PEPF0000ECD8:EE_|DS0PR12MB7945:EE_ X-MS-Office365-Filtering-Correlation-Id: 84e43b87-ccaf-45e9-40c4-08de15edf31e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|376014|1800799024|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?MGsg6123hMoju6ggCx5MM93sYBKZlejJUW3hZWLMjv6tnRboYfGX6ngdsSO7?= =?us-ascii?Q?dXuK9Gle3GDFNeYM9OttlOe0pzqTUZOG5qy8A6MitngvieG+LYcMff2F8/7b?= =?us-ascii?Q?bsnpt0U/LDcJKre7WEXAyELPAqxCTAxy+TQaBj1200ZS8ED5CFYGa2Mo9ZhG?= =?us-ascii?Q?q/iPsLAHQwNnV8BYd8Kd/1bkfM7KTL2nWETt4GfLWcW6syzIzE/lFkOHA/cy?= =?us-ascii?Q?5eto5StLwW4wH9buJl1uZYoc44NZFNbhsP8Oug7BNa7RqVRaT60hIzV9nW2l?= =?us-ascii?Q?/K7g3Rx6gC1EjAKD9lEdlP1NnxR64x/9Qj8jPIp+e9lsGrIcGwI6dFHxSPK3?= =?us-ascii?Q?0+6rj99xH9cdGkCiHfPIK+KBOJxRlQxDMwGYVhfQHmxB7bqzznJh+NTNAGSF?= =?us-ascii?Q?Fdjolo4wkP8y8+FsK6m5m6S0g/T4Kpwi+mUEjjIYCeYY1QnhdWoCzBCOPMWo?= =?us-ascii?Q?MkjQlxPJQwd2/hvJrur6yKTPn5/IDVWiR0QF7Xu4h+vJHArt0XM+yMfJm3EQ?= =?us-ascii?Q?e1DvxfklPVSuLDoIbd2IYMsP2ehBE8uw/JifHH6lGzN2XD+GBYRPlaraJad3?= =?us-ascii?Q?MTxeJTOIHH2RCKkFf4KWUntV3RamYSIEsjN3tmk6SZnaMihactM+p/r1hDqq?= =?us-ascii?Q?+lSJsDStkzoN30Ka6sHfnQazrvi7fzJh6CxafeB5lwvYYUYmybBLB/wQ+GBP?= =?us-ascii?Q?AkxP/I6TTRNHjUQZK1L/lRt2Ctf+3ZTlfxDETeZDJCijQWZt0ZcbXmqejLrE?= =?us-ascii?Q?HUTNHotIoJC2qunAyaPvGXliBIu5yfEHGRPiOoyVPwtnm4QxxTtZSuHD1sbJ?= =?us-ascii?Q?1/xMeBoYZOVMD5Q57hfSgo52zB5lJ7aheA2Xw6o4aW98L2hax45gUadqEJj0?= =?us-ascii?Q?z9INSH7kO8gLa1AhPrFHrk2maICZDyT1odhkPWImKLDP9qJ7SixhxbXkRZpq?= =?us-ascii?Q?l80OEL36CVaIxQ55lgxiUP9pgzboXKlQjaTnTtZzz2EIm3pYHIj0FtUeRKz8?= =?us-ascii?Q?A1PW3Nxdac58egpvu8rbhsNURisnlR7A56Si2x+E9+qB5NqgAzRbPAhL32yz?= =?us-ascii?Q?ZCLxx2LCtJx8v+JqzXNTeQxyywsJTtiRXvKf2OvsQu/FFcrNW7UaoBgE+4ev?= =?us-ascii?Q?HC2RQG+skINv/LIG1bkMgLBJ6MB+SEQRJXVOuxJliZKaaGF4r4wTPKlt2ih7?= =?us-ascii?Q?BtARy2cL1Oetz253XOKk/G++Azgvrll1rddAF4Ar3GLaW9qAghVMqrBY0rZE?= =?us-ascii?Q?mSj0TIXrkitO21zbyyMLxedyfy1c2QAeXIcSYlCrtg6X2+yZVou1JFbhF4wG?= =?us-ascii?Q?Y4QC876Cvmd2gdBtEoWApCONeJNsTiYssRXoFjl7rQYqdVhTTRbA9WJP81br?= =?us-ascii?Q?8dpCWGWCCT5RUPIG5dWurghrDXD0kiU78PylKtWSkCbgLFub4WvpAXvFwMJ+?= =?us-ascii?Q?VhN9Xz8XwDfg1hR5G0i+7v3C+zCAoF56VM+Skoe5TGsqA91/E9wHAeAADUwm?= =?us-ascii?Q?fbC41SkKIIYimpExEPiF1YDJh0hsecu0x+EM3KGjazTD886bZkHY5wtXGoWs?= =?us-ascii?Q?WbJaLsc4F95svvMHgI4=3D?= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(376014)(1800799024)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Oct 2025 06:48:06.1657 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 84e43b87-ccaf-45e9-40c4-08de15edf31e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MN1PEPF0000ECD8.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7945 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Dragos Tatulea The MLX5E_SHAMPO_WQ_HEADER_PER_PAGE and MLX5E_SHAMPO_LOG_MAX_HEADER_ENTRY_SIZE macros are used directly in several places under the assumption that there will always be more headers per WQE than headers per page. However, this assumption doesn't hold for 64K page sizes and higher MTUs (> 4K). This can be first observed during header page allocation: ksm_entries will become 0 during alignment to MLX5E_SHAMPO_WQ_HEADER_PER_PAGE. This patch introduces 2 additional members to the mlx5e_shampo_hd struct which are meant to be used instead of the macrose mentioned above. When the number of headers per WQE goes below MLX5E_SHAMPO_WQ_HEADER_PER_PAGE, clamp the number of headers per page and expand the header size accordingly so that the headers for one WQE cover a full page. All the formulas are adapted to use these two new members. Fixes: 945ca432bfd0 ("net/mlx5e: SHAMPO, Drop info array") Signed-off-by: Dragos Tatulea Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/en.h | 3 ++ .../net/ethernet/mellanox/mlx5/core/en_main.c | 24 +++++++++++--- .../net/ethernet/mellanox/mlx5/core/en_rx.c | 33 +++++++++++-------- 3 files changed, 41 insertions(+), 19 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en.h b/drivers/net/eth= ernet/mellanox/mlx5/core/en.h index 14e3207b14e7..a163f81f07c1 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en.h @@ -634,7 +634,10 @@ struct mlx5e_dma_info { struct mlx5e_shampo_hd { struct mlx5e_frag_page *pages; u32 hd_per_wq; + u32 hd_per_page; u16 hd_per_wqe; + u8 log_hd_per_page; + u8 log_hd_entry_size; unsigned long *bitmap; u16 pi; u16 ci; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/en_main.c index 9c46511e7b43..6023bbbf3f39 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c @@ -791,8 +791,9 @@ static int mlx5_rq_shampo_alloc(struct mlx5_core_dev *m= dev, int node) { void *wqc =3D MLX5_ADDR_OF(rqc, rqp->rqc, wq); + u8 log_hd_per_page, log_hd_entry_size; + u16 hd_per_wq, hd_per_wqe; u32 hd_pool_size; - u16 hd_per_wq; int wq_size; int err; =20 @@ -815,11 +816,24 @@ static int mlx5_rq_shampo_alloc(struct mlx5_core_dev = *mdev, if (err) goto err_umr_mkey; =20 - rq->mpwqe.shampo->hd_per_wqe =3D - mlx5e_shampo_hd_per_wqe(mdev, params, rqp); + hd_per_wqe =3D mlx5e_shampo_hd_per_wqe(mdev, params, rqp); wq_size =3D BIT(MLX5_GET(wq, wqc, log_wq_sz)); - hd_pool_size =3D (rq->mpwqe.shampo->hd_per_wqe * wq_size) / - MLX5E_SHAMPO_WQ_HEADER_PER_PAGE; + + BUILD_BUG_ON(MLX5E_SHAMPO_LOG_MAX_HEADER_ENTRY_SIZE > PAGE_SHIFT); + if (hd_per_wqe >=3D MLX5E_SHAMPO_WQ_HEADER_PER_PAGE) { + log_hd_per_page =3D MLX5E_SHAMPO_LOG_WQ_HEADER_PER_PAGE; + log_hd_entry_size =3D MLX5E_SHAMPO_LOG_MAX_HEADER_ENTRY_SIZE; + } else { + log_hd_per_page =3D order_base_2(hd_per_wqe); + log_hd_entry_size =3D order_base_2(PAGE_SIZE / hd_per_wqe); + } + + rq->mpwqe.shampo->hd_per_wqe =3D hd_per_wqe; + rq->mpwqe.shampo->hd_per_page =3D BIT(log_hd_per_page); + rq->mpwqe.shampo->log_hd_per_page =3D log_hd_per_page; + rq->mpwqe.shampo->log_hd_entry_size =3D log_hd_entry_size; + + hd_pool_size =3D (hd_per_wqe * wq_size) >> log_hd_per_page; =20 if (netif_rxq_has_unreadable_mp(rq->netdev, rq->ix)) { /* Separate page pool for shampo headers */ diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c b/drivers/net/= ethernet/mellanox/mlx5/core/en_rx.c index ea4e7f486c8b..e84899a47119 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c @@ -648,17 +648,20 @@ static void build_ksm_umr(struct mlx5e_icosq *sq, str= uct mlx5e_umr_wqe *umr_wqe, umr_wqe->hdr.uctrl.mkey_mask =3D cpu_to_be64(MLX5_MKEY_MASK_FREE); } =20 -static struct mlx5e_frag_page *mlx5e_shampo_hd_to_frag_page(struct mlx5e_r= q *rq, int header_index) +static struct mlx5e_frag_page *mlx5e_shampo_hd_to_frag_page(struct mlx5e_r= q *rq, + int header_index) { - BUILD_BUG_ON(MLX5E_SHAMPO_LOG_MAX_HEADER_ENTRY_SIZE > PAGE_SHIFT); + struct mlx5e_shampo_hd *shampo =3D rq->mpwqe.shampo; =20 - return &rq->mpwqe.shampo->pages[header_index >> MLX5E_SHAMPO_LOG_WQ_HEADE= R_PER_PAGE]; + return &shampo->pages[header_index >> shampo->log_hd_per_page]; } =20 -static u64 mlx5e_shampo_hd_offset(int header_index) +static u64 mlx5e_shampo_hd_offset(struct mlx5e_rq *rq, int header_index) { - return (header_index & (MLX5E_SHAMPO_WQ_HEADER_PER_PAGE - 1)) << - MLX5E_SHAMPO_LOG_MAX_HEADER_ENTRY_SIZE; + struct mlx5e_shampo_hd *shampo =3D rq->mpwqe.shampo; + u32 hd_per_page =3D shampo->hd_per_page; + + return (header_index & (hd_per_page - 1)) << shampo->log_hd_entry_size; } =20 static void mlx5e_free_rx_shampo_hd_entry(struct mlx5e_rq *rq, u16 header_= index); @@ -684,7 +687,7 @@ static int mlx5e_build_shampo_hd_umr(struct mlx5e_rq *r= q, u64 addr; =20 frag_page =3D mlx5e_shampo_hd_to_frag_page(rq, index); - header_offset =3D mlx5e_shampo_hd_offset(index); + header_offset =3D mlx5e_shampo_hd_offset(rq, index); if (!header_offset) { err =3D mlx5e_page_alloc_fragmented(rq->hd_page_pool, frag_page); @@ -714,7 +717,7 @@ static int mlx5e_build_shampo_hd_umr(struct mlx5e_rq *r= q, err_unmap: while (--i >=3D 0) { --index; - header_offset =3D mlx5e_shampo_hd_offset(index); + header_offset =3D mlx5e_shampo_hd_offset(rq, index); if (!header_offset) { struct mlx5e_frag_page *frag_page =3D mlx5e_shampo_hd_to_frag_page(rq, = index); =20 @@ -738,7 +741,7 @@ static int mlx5e_alloc_rx_hd_mpwqe(struct mlx5e_rq *rq) ksm_entries =3D bitmap_find_window(shampo->bitmap, shampo->hd_per_wqe, shampo->hd_per_wq, shampo->pi); - ksm_entries =3D ALIGN_DOWN(ksm_entries, MLX5E_SHAMPO_WQ_HEADER_PER_PAGE); + ksm_entries =3D ALIGN_DOWN(ksm_entries, shampo->hd_per_page); if (!ksm_entries) return 0; =20 @@ -856,7 +859,7 @@ mlx5e_free_rx_shampo_hd_entry(struct mlx5e_rq *rq, u16 = header_index) { struct mlx5e_shampo_hd *shampo =3D rq->mpwqe.shampo; =20 - if (((header_index + 1) & (MLX5E_SHAMPO_WQ_HEADER_PER_PAGE - 1)) =3D=3D 0= ) { + if (((header_index + 1) & (shampo->hd_per_page - 1)) =3D=3D 0) { struct mlx5e_frag_page *frag_page =3D mlx5e_shampo_hd_to_frag_page(rq, h= eader_index); =20 mlx5e_page_release_fragmented(rq->hd_page_pool, frag_page); @@ -1219,9 +1222,10 @@ static unsigned int mlx5e_lro_update_hdr(struct sk_b= uff *skb, static void *mlx5e_shampo_get_packet_hd(struct mlx5e_rq *rq, u16 header_in= dex) { struct mlx5e_frag_page *frag_page =3D mlx5e_shampo_hd_to_frag_page(rq, he= ader_index); - u16 head_offset =3D mlx5e_shampo_hd_offset(header_index) + rq->buff.headr= oom; + u16 head_offset =3D mlx5e_shampo_hd_offset(rq, header_index); + void *addr =3D netmem_address(frag_page->netmem); =20 - return netmem_address(frag_page->netmem) + head_offset; + return addr + head_offset + rq->buff.headroom; } =20 static void mlx5e_shampo_update_ipv4_udp_hdr(struct mlx5e_rq *rq, struct i= phdr *ipv4) @@ -2261,7 +2265,8 @@ mlx5e_skb_from_cqe_shampo(struct mlx5e_rq *rq, struct= mlx5e_mpw_info *wi, struct mlx5_cqe64 *cqe, u16 header_index) { struct mlx5e_frag_page *frag_page =3D mlx5e_shampo_hd_to_frag_page(rq, he= ader_index); - u16 head_offset =3D mlx5e_shampo_hd_offset(header_index); + u16 head_offset =3D mlx5e_shampo_hd_offset(rq, header_index); + struct mlx5e_shampo_hd *shampo =3D rq->mpwqe.shampo; u16 head_size =3D cqe->shampo.header_size; u16 rx_headroom =3D rq->buff.headroom; struct sk_buff *skb =3D NULL; @@ -2277,7 +2282,7 @@ mlx5e_skb_from_cqe_shampo(struct mlx5e_rq *rq, struct= mlx5e_mpw_info *wi, data =3D hdr + rx_headroom; frag_size =3D MLX5_SKB_FRAG_SZ(rx_headroom + head_size); =20 - if (likely(frag_size <=3D BIT(MLX5E_SHAMPO_LOG_MAX_HEADER_ENTRY_SIZE))) { + if (likely(frag_size <=3D BIT(shampo->log_hd_entry_size))) { /* build SKB around header */ dma_sync_single_range_for_cpu(rq->pdev, dma_addr, 0, frag_size, rq->buff= .map_dir); net_prefetchw(hdr); --=20 2.31.1