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Thu, 23 Oct 2025 02:17:49 -0700 From: Tariq Toukan To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , , , , Gal Pressman , Moshe Shemesh , Shay Drori Subject: [PATCH net-next 5/5] net/mlx5: Add balance ID support for LAG multiplane groups Date: Thu, 23 Oct 2025 12:17:00 +0300 Message-ID: <1761211020-925651-6-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1761211020-925651-1-git-send-email-tariqt@nvidia.com> References: <1761211020-925651-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF00004FC0:EE_|BL3PR12MB6569:EE_ X-MS-Office365-Filtering-Correlation-Id: 418bdeb1-c3d0-462c-e0bb-08de12151587 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|376014|36860700013|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?hIr9h2FtRdFmz5tj1rO2tkQnhzyKiRoVo8rr5zmd9khriycDkxvWx9gI503B?= =?us-ascii?Q?EA5/z2lvQV0//kgbG19u11i13DRxZHPJ0/j86wWsKqv2jg445ypKAypMm3S9?= =?us-ascii?Q?zyAZdtuBZhsV2eRLhbVnnV4JPRtejqgciBMXqPVMh+t4wEarNsMX5cdVFNj2?= =?us-ascii?Q?oRjnCar5aGFhjvRZZpVAYy5JdWZfYZXXfDrFwGfAs4iL+QqgLLaNwAP20gdS?= =?us-ascii?Q?uerxm46venB60G5LNcHKvlYTK1yCEymCfLriE2+S+HMA5+nhj/UtDUFUV3LE?= =?us-ascii?Q?1d1Qz2/3vDIxrLidS7Cy1ELKWyagNVh4S+ZI1EvwVsSWIQwSUKbhX37LfbOQ?= =?us-ascii?Q?uKuRNTjXhZmokINg6jKnxq0T5VhzED6rtzQkABAb9Byku4TBiLNbNzAsgzRH?= =?us-ascii?Q?IQ8srZIYJFgyIMUIAdOrQ6PmsE8Nqhq4mN/ypj2+C8gHC7ogAN2BLgjaVH95?= =?us-ascii?Q?SgBK20Yqzqy6+Oj9iykpbd/dl1TIEB7nhrLlF6gYnzTeYgNfF9mSlMdbtMWh?= =?us-ascii?Q?uRNbnAeTX4QIPosnW5akD0FyLEO2lBcvx0DIw/O8KcH1p8njgRfWfX9uIugA?= =?us-ascii?Q?BuXPON9RXbVT1zaPKDn/jgwqKu/wWWPERID9+srwlGMUYkLMOe6GK7bv2ReO?= =?us-ascii?Q?2vyaZtSClE8sWCTRyhFJrdL4V0mfigSmSBOZYrZDjM+YZMXc3ApfUsHCMp88?= =?us-ascii?Q?qoftmIoKWG6CDIyTO5gL+dCWVcykMBU++N5qaQ8ff8AhXcStlFCJrgu9/Mm6?= =?us-ascii?Q?h5+ws2UX6WlGiw6xg3vNNTjhLEV75a5L1N8w9lPmrz1/Q1rMHpRIrLbDdje1?= =?us-ascii?Q?Cq/A4NPEbNr90NVIFo9GSFUoNQzlY4oWX6lGWHEZ4wIqHD5iWtaWMLVR0rke?= =?us-ascii?Q?ZpO/Ke+vghm+2YnWePWYDoER4CLmDwQJ+xjbknTHgS/vXgNh0xijrzuQcc3c?= =?us-ascii?Q?7LSI1FKWoHnT1Jh3YPKdLdXBSiqJN02vy7/PJThXT6HkYYsMT/rfDPsjLAPT?= =?us-ascii?Q?Na1DFleOk0KEvuGytxNcvV73j9MDc/Lf7rp/qgqUT6eTlOocUPUeWo+Tp+4g?= =?us-ascii?Q?ozNj2SMRi+A1hgCCVcJ08V4DdwmE3S3HJb7PyyYjKVNV3SVihlyXwdv+Rs8C?= =?us-ascii?Q?rwUNbdcZk7E6x+Sz3tPpN9yd87tG1jZYw6xZfQPSeFD5V4xiVhk0AN8x+CWP?= =?us-ascii?Q?ztG6xqO14d4AIAaQcIJASWna9VwVDp4ZXD27rTaS+0iurifTy8Cxp+5dJt5i?= =?us-ascii?Q?FqGbLC0iwjRSq2bEEQ01U7zv+sh92RtUn9bTmDe3Gx7ThvX/g9O6TCLgMFH0?= =?us-ascii?Q?H3xLqliDQY0QrQe4JZh+ntBodjkDZFfl7H8ylOsQSIVpXGn3RFF8PUaSjV0C?= =?us-ascii?Q?83/Ck8SRiy2UQ+t8J6Vsk1yxd+xCEf+XDAJL+UktyBg6Gfie2eOKdGG4GSej?= =?us-ascii?Q?/9Yblka2V4iuRNfRd38ersMkzct5CDu/p1JVLJ286cElzLZ8CoMFG/l9Mxxc?= =?us-ascii?Q?Q5aEohhixMRA3a4QJtrOSzTcFOa80ADL4AqiTla2RAoAYFAfL2adPdfdqt0j?= =?us-ascii?Q?pM5Ght6W+eZmUJmtdcA=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(376014)(36860700013)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Oct 2025 09:18:09.6226 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 418bdeb1-c3d0-462c-e0bb-08de12151587 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF00004FC0.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL3PR12MB6569 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Mark Bloch Implement balance ID support for multiplane LAG configurations. This feature enables per-multiplane group load balancing by extending the software system image GUID with a balance ID component. Key implementations: - Enable lag_per_mp_group capability when supported by hardware. - Append load_balance_id to software system image GUID when conditions are met. - Increase MLX5_SW_IMAGE_GUID_MAX_BYTES from 8 to 9 to accommodate the extra byte. The balance ID is appended to the system image GUID only when both load_balance_id and lag_per_mp_group capabilities are available, ensuring backward compatibility while enabling enhanced LAG functionality. This enhancement allows for more granular load balancing control in complex multi-plane LAG deployments, improving network performance and flexibility. Signed-off-by: Mark Bloch Reviewed-by: Moshe Shemesh Reviewed-by: Shay Drori Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/main.c | 5 +++++ drivers/net/ethernet/mellanox/mlx5/core/vport.c | 4 ++++ include/linux/mlx5/driver.h | 2 +- 3 files changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/main.c b/drivers/net/e= thernet/mellanox/mlx5/core/main.c index 1126e4db0318..cc6374b4e0b8 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/main.c @@ -575,6 +575,11 @@ static int handle_hca_cap_2(struct mlx5_core_dev *dev,= void *set_ctx) do_set =3D true; } =20 + if (MLX5_CAP_GEN_2_MAX(dev, lag_per_mp_group)) { + MLX5_SET(cmd_hca_cap_2, set_hca_cap, lag_per_mp_group, 1); + do_set =3D true; + } + /* some FW versions that support querying MLX5_CAP_GENERAL_2 * capabilities but don't support setting them. * Skip unnecessary update to hca_cap_2 when no changes were introduced diff --git a/drivers/net/ethernet/mellanox/mlx5/core/vport.c b/drivers/net/= ethernet/mellanox/mlx5/core/vport.c index 4224e2750865..992873536c1b 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/vport.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/vport.c @@ -1203,6 +1203,10 @@ void mlx5_query_nic_sw_system_image_guid(struct mlx5= _core_dev *mdev, u8 *buf, =20 memcpy(buf, &fw_system_image_guid, sizeof(fw_system_image_guid)); *len +=3D sizeof(fw_system_image_guid); + + if (MLX5_CAP_GEN_2(mdev, load_balance_id) && + MLX5_CAP_GEN_2(mdev, lag_per_mp_group)) + buf[(*len)++] =3D MLX5_CAP_GEN_2(mdev, load_balance_id); } =20 static bool mlx5_vport_use_vhca_id_as_func_id(struct mlx5_core_dev *dev, diff --git a/include/linux/mlx5/driver.h b/include/linux/mlx5/driver.h index dcf262aa9ea6..046396269ccf 100644 --- a/include/linux/mlx5/driver.h +++ b/include/linux/mlx5/driver.h @@ -1380,6 +1380,6 @@ static inline struct net *mlx5_core_net(struct mlx5_c= ore_dev *dev) return devlink_net(priv_to_devlink(dev)); } =20 -#define MLX5_SW_IMAGE_GUID_MAX_BYTES 8 +#define MLX5_SW_IMAGE_GUID_MAX_BYTES 9 =20 #endif /* MLX5_DRIVER_H */ --=20 2.31.1