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Wed, 22 Oct 2025 23:44:49 -0700 From: Tariq Toukan To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , , , , Gal Pressman , "Carolina Jubran" , Dragos Tatulea Subject: [PATCH net-next 1/7] net/mlx5e: Enhance function structures for self loopback prevention application Date: Thu, 23 Oct 2025 09:43:34 +0300 Message-ID: <1761201820-923638-2-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1761201820-923638-1-git-send-email-tariqt@nvidia.com> References: <1761201820-923638-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000A348:EE_|DS7PR12MB6165:EE_ X-MS-Office365-Filtering-Correlation-Id: d3f5f294-102c-431d-6bce-08de11ffb330 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|376014|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?U0U3BcuS391ek3lxn4bkL/5/EK87s19ecTx5w+/CzJdOYoWozrtPhy0LW8n4?= =?us-ascii?Q?0Av7UNfr2kfB3iJp3MjAbT+jn6F1/C27i+sbPO9ECS6CxNWwmnwHag918Vri?= =?us-ascii?Q?KUjw/IccRRYY3Jx0yRF9aUUCKXjACK8QwZwVCxIkP4Ryr3RpcXDmm6R3O6UE?= =?us-ascii?Q?f9FAZRzpP0WieDgR7yC2m1UElxF6ppf/Fmm5vW9SG0IxaYm3KZK6ooQpiZEx?= =?us-ascii?Q?u30+nL95Wkp1VvE5J9bOIYrhplsGYtroYqE+VnvGfq/WWSEK7oRHa/9KFE6s?= =?us-ascii?Q?Y6eMQvRHSjzRu0sFZu2FYzfQeiYRGIOK7FT4t2Kh92gjnmBOrwsGn3z83yvW?= =?us-ascii?Q?LEkrNNCpxPr3P09e+M92dpjn9hl1Mq/5EZDq0R22KFakb8cr1OxF3YKv+JBK?= =?us-ascii?Q?V4VE6+/phqrZI8XsHR70Kh2fjw1PaZFaV8kgJhhuJqTX50SV3JjsnDT0Mvhm?= =?us-ascii?Q?f1FRwL/WkzhqF6VShfC3zILNQakSoumAdQdt4BIsoIwV2tZcQR2IAETzVjFp?= =?us-ascii?Q?JSFnvjbhv69juF/OSccGwFbGfVL5qPLZnGvapeq5VC8q+EwpLP1lcQDrHA8u?= =?us-ascii?Q?JjDkuPC7+BYKQVMvSeO4w8fsAxYeKlFTb3tOh/h/ibC+NAA8Ce9kcAAGtifA?= =?us-ascii?Q?QQp4oHchNGlK2S240gZ5kE1nzSHF1vNoQSCGfYfhW+rK5+lB1YD7tq4doDsB?= =?us-ascii?Q?8A8ajUYv0QFznry4h9clCGUOJUuwrEX0M1r2jrcqeGAWe2wxWUXeWp0UC5Ax?= =?us-ascii?Q?DurwQBkuKvRkRdjJqQO8qnJ+uRMQsWpk65X6mNu0efL/RjDPKhOCoEX9g1U9?= =?us-ascii?Q?789oKkPUOuoWmOZms0XEWmZxrq3kulP/Wghv4V2led3A2HGysXxolFl/QUyS?= =?us-ascii?Q?xH6lbD91Xa/5/Mpv05380S/bBRlMgY2ZCsA/1kpwVmXbjHfUUM0TgDXxnwb0?= =?us-ascii?Q?U1EJ3vgkiq1q4up6VAq9Y1FkVa2JBwQE4jRveotzqtSxp5CeEb+N1nPIvLnf?= =?us-ascii?Q?XShxKUZcWlAnL0UbIwvZ4EQcXT2bXcS3Hu/TyUAW55q8AUELKrxiM3/7fJSC?= =?us-ascii?Q?/4Ryc22FjhKvN8TzJ+XsXImeeYUSeuAuThA4xqsOPRf0ckbhuj2JXdlvkjye?= =?us-ascii?Q?DffVrVlZ261pLYHqQo4fGWHgKMc7is4kPjtwvk/XOSuPpr0QWHprOyigFCS0?= =?us-ascii?Q?ollG23Q+Qnc505jXJexTJA1trIHb1Vf7cUHEmePwVHTwZJetHwpbkrS5smzO?= =?us-ascii?Q?DBTosbmQuvPr5VjKRTKEd1Vgu+pSDlPqnmC8Bbp1Xqk+KipA7ek/n55MdiXl?= =?us-ascii?Q?oVIaqRHisOXdu2ivd+L4ELA3njcUcO6GbafenlZMYgIAZahtWHo9kmb9z6oD?= =?us-ascii?Q?0SPW66gNmw2hZN9Jc7waHQdynQeDV82hBnW4zuZzQPSeAvXC2sn088wexymE?= =?us-ascii?Q?GRZEb/T8vGMwZdU4NVKDTJzmD/d9X27euUL7q64yRJfAiFtp48hL5Uvg8tQ7?= =?us-ascii?Q?U9hlTOSSfWlywrvb27TRqdhMYOXcs8czEpid3w0pX6XODU0WpNt2SC3DxrXT?= =?us-ascii?Q?MaZlg3yPWEdMw1/7Uj4=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(1800799024)(376014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Oct 2025 06:45:05.2314 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d3f5f294-102c-431d-6bce-08de11ffb330 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000A348.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB6165 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The re-application of self loopback prevention attributes in TIRs is necessary in old firmwares (where tis_tir_td_order cap is cleared) after recreation of SQs. However, this is not needed in new firmware with tis_tir_td_order=3D1. As a preparation patch, enhance the function structures to differentiate between an explicit loopback prevention configuration apply, and the re-apply operation required by old firmware. Loopback selftests should now call mlx5e_modify_tirs_lb() directly, as their use case is not related to the firmware limitation. Signed-off-by: Tariq Toukan Reviewed-by: Carolina Jubran --- drivers/net/ethernet/mellanox/mlx5/core/en.h | 4 +++- .../net/ethernet/mellanox/mlx5/core/en_common.c | 16 ++++++++++++---- .../net/ethernet/mellanox/mlx5/core/en_main.c | 2 +- .../ethernet/mellanox/mlx5/core/en_selftest.c | 4 ++-- .../ethernet/mellanox/mlx5/core/ipoib/ipoib.c | 2 +- 5 files changed, 19 insertions(+), 9 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en.h b/drivers/net/eth= ernet/mellanox/mlx5/core/en.h index 14e3207b14e7..a25588fe2773 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en.h @@ -1154,7 +1154,9 @@ extern const struct ethtool_ops mlx5e_ethtool_ops; int mlx5e_create_mkey(struct mlx5_core_dev *mdev, u32 pdn, u32 *mkey); int mlx5e_create_mdev_resources(struct mlx5_core_dev *mdev, bool create_ti= ses); void mlx5e_destroy_mdev_resources(struct mlx5_core_dev *mdev); -int mlx5e_refresh_tirs(struct mlx5e_priv *priv, bool enable_uc_lb, +int mlx5e_modify_tirs_lb(struct mlx5_core_dev *mdev, bool enable_uc_lb, + bool enable_mc_lb); +int mlx5e_refresh_tirs(struct mlx5_core_dev *mdev, bool enable_uc_lb, bool enable_mc_lb); void mlx5e_mkey_set_relaxed_ordering(struct mlx5_core_dev *mdev, void *mkc= ); =20 diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_common.c b/drivers/= net/ethernet/mellanox/mlx5/core/en_common.c index 30424ccad584..376a018b2db1 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_common.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_common.c @@ -247,10 +247,9 @@ void mlx5e_destroy_mdev_resources(struct mlx5_core_dev= *mdev) memset(res, 0, sizeof(*res)); } =20 -int mlx5e_refresh_tirs(struct mlx5e_priv *priv, bool enable_uc_lb, - bool enable_mc_lb) +int mlx5e_modify_tirs_lb(struct mlx5_core_dev *mdev, bool enable_uc_lb, + bool enable_mc_lb) { - struct mlx5_core_dev *mdev =3D priv->mdev; struct mlx5e_tir *tir; u8 lb_flags =3D 0; int err =3D 0; @@ -285,7 +284,16 @@ int mlx5e_refresh_tirs(struct mlx5e_priv *priv, bool e= nable_uc_lb, =20 kvfree(in); if (err) - netdev_err(priv->netdev, "refresh tir(0x%x) failed, %d\n", tirn, err); + mlx5_core_err(mdev, + "modify tir(0x%x) enable_lb uc(%d) mc(%d) failed, %d\n", + tirn, + enable_uc_lb, enable_mc_lb, err); =20 return err; } + +int mlx5e_refresh_tirs(struct mlx5_core_dev *mdev, bool enable_uc_lb, + bool enable_mc_lb) +{ + return mlx5e_modify_tirs_lb(mdev, enable_uc_lb, enable_mc_lb); +} diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/en_main.c index a56825921c23..8e13f2542d8d 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c @@ -6130,7 +6130,7 @@ static void mlx5e_nic_disable(struct mlx5e_priv *priv) =20 static int mlx5e_update_nic_rx(struct mlx5e_priv *priv) { - return mlx5e_refresh_tirs(priv, false, false); + return mlx5e_refresh_tirs(priv->mdev, false, false); } =20 static const struct mlx5e_profile mlx5e_nic_profile =3D { diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_selftest.c b/driver= s/net/ethernet/mellanox/mlx5/core/en_selftest.c index 2f7a543feca6..fcad464bc4d5 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_selftest.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_selftest.c @@ -214,7 +214,7 @@ static int mlx5e_test_loopback_setup(struct mlx5e_priv = *priv, return err; } =20 - err =3D mlx5e_refresh_tirs(priv, true, false); + err =3D mlx5e_modify_tirs_lb(priv->mdev, true, false); if (err) goto out; =20 @@ -243,7 +243,7 @@ static void mlx5e_test_loopback_cleanup(struct mlx5e_pr= iv *priv, mlx5_nic_vport_update_local_lb(priv->mdev, false); =20 dev_remove_pack(&lbtp->pt); - mlx5e_refresh_tirs(priv, false, false); + mlx5e_modify_tirs_lb(priv->mdev, false, false); } =20 static int mlx5e_cond_loopback(struct mlx5e_priv *priv) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/ipoib/ipoib.c b/driver= s/net/ethernet/mellanox/mlx5/core/ipoib/ipoib.c index 79ae3a51a4b3..49ab0de762c9 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/ipoib/ipoib.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/ipoib/ipoib.c @@ -316,7 +316,7 @@ void mlx5i_destroy_underlay_qp(struct mlx5_core_dev *md= ev, u32 qpn) =20 int mlx5i_update_nic_rx(struct mlx5e_priv *priv) { - return mlx5e_refresh_tirs(priv, true, true); + return mlx5e_refresh_tirs(priv->mdev, true, true); } =20 int mlx5i_create_tis(struct mlx5_core_dev *mdev, u32 underlay_qpn, u32 *ti= sn) --=20 2.31.1 From nobody Sat Feb 7 12:19:23 2026 Received: from CH1PR05CU001.outbound.protection.outlook.com (mail-northcentralusazon11010047.outbound.protection.outlook.com [52.101.193.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A2E7A2566F2; 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Signed-off-by: Tariq Toukan Reviewed-by: Carolina Jubran Reviewed-by: Dragos Tatulea --- .../net/ethernet/mellanox/mlx5/core/en/tir.c | 29 +++++++++++++++++-- .../net/ethernet/mellanox/mlx5/core/en/tir.h | 3 ++ .../ethernet/mellanox/mlx5/core/en_common.c | 29 +++++-------------- 3 files changed, 37 insertions(+), 24 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/tir.c b/drivers/net= /ethernet/mellanox/mlx5/core/en/tir.c index 19499072f67f..0b55e77f19c8 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/tir.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/tir.c @@ -146,6 +146,31 @@ void mlx5e_tir_builder_build_direct(struct mlx5e_tir_b= uilder *builder) MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8); } =20 +static void mlx5e_tir_context_self_lb_block(void *tirc, bool enable_uc_lb, + bool enable_mc_lb) +{ + u8 lb_flags =3D 0; + + if (enable_uc_lb) + lb_flags =3D MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST; + if (enable_mc_lb) + lb_flags |=3D MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST; + + MLX5_SET(tirc, tirc, self_lb_block, lb_flags); +} + +void mlx5e_tir_builder_build_self_lb_block(struct mlx5e_tir_builder *build= er, + bool enable_uc_lb, + bool enable_mc_lb) +{ + void *tirc =3D mlx5e_tir_builder_get_tirc(builder); + + if (builder->modify) + MLX5_SET(modify_tir_in, builder->in, bitmask.self_lb_en, 1); + + mlx5e_tir_context_self_lb_block(tirc, enable_uc_lb, enable_mc_lb); +} + void mlx5e_tir_builder_build_tls(struct mlx5e_tir_builder *builder) { void *tirc =3D mlx5e_tir_builder_get_tirc(builder); @@ -153,9 +178,7 @@ void mlx5e_tir_builder_build_tls(struct mlx5e_tir_build= er *builder) WARN_ON(builder->modify); =20 MLX5_SET(tirc, tirc, tls_en, 1); - MLX5_SET(tirc, tirc, self_lb_block, - MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST | - MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST); + mlx5e_tir_context_self_lb_block(tirc, true, true); } =20 int mlx5e_tir_init(struct mlx5e_tir *tir, struct mlx5e_tir_builder *builde= r, diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/tir.h b/drivers/net= /ethernet/mellanox/mlx5/core/en/tir.h index e8df3aaf6562..958eeb959a19 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/tir.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/tir.h @@ -35,6 +35,9 @@ void mlx5e_tir_builder_build_rss(struct mlx5e_tir_builder= *builder, const struct mlx5e_rss_params_traffic_type *rss_tt, bool inner); void mlx5e_tir_builder_build_direct(struct mlx5e_tir_builder *builder); +void mlx5e_tir_builder_build_self_lb_block(struct mlx5e_tir_builder *build= er, + bool enable_uc_lb, + bool enable_mc_lb); void mlx5e_tir_builder_build_tls(struct mlx5e_tir_builder *builder); =20 struct mlx5_core_dev; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_common.c b/drivers/= net/ethernet/mellanox/mlx5/core/en_common.c index 376a018b2db1..fad6b761f622 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_common.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_common.c @@ -250,43 +250,30 @@ void mlx5e_destroy_mdev_resources(struct mlx5_core_de= v *mdev) int mlx5e_modify_tirs_lb(struct mlx5_core_dev *mdev, bool enable_uc_lb, bool enable_mc_lb) { + struct mlx5e_tir_builder *builder; struct mlx5e_tir *tir; - u8 lb_flags =3D 0; int err =3D 0; - u32 tirn =3D 0; - int inlen; - void *in; =20 - inlen =3D MLX5_ST_SZ_BYTES(modify_tir_in); - in =3D kvzalloc(inlen, GFP_KERNEL); - if (!in) + builder =3D mlx5e_tir_builder_alloc(true); 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Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , , , , Gal Pressman , "Carolina Jubran" , Dragos Tatulea Subject: [PATCH net-next 3/7] net/mlx5e: Allow setting self loopback prevention bits on TIR init Date: Thu, 23 Oct 2025 09:43:36 +0300 Message-ID: <1761201820-923638-4-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1761201820-923638-1-git-send-email-tariqt@nvidia.com> References: <1761201820-923638-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE31:EE_|DS0PR12MB8813:EE_ X-MS-Office365-Filtering-Correlation-Id: 4e89a69d-fd86-4284-363f-08de11ffbbae X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|82310400026|36860700013|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?aFKYVB4Lgycag6Kkh2zqJ4FknZvySVrBszbENKnwHU3Mr4fPN3LWnk4QqnXQ?= =?us-ascii?Q?KU6j55GTjLg/6kTvfJCcMFDno9WLq9fenGGXdrnxMsA+J5Iv5xgZk4rZvQF1?= =?us-ascii?Q?Xfgeuyb9MlzGoHsD0s89ldqkoK8KJTpmBPZTDxl1tlleD5thAoMAzzM3iPt2?= =?us-ascii?Q?GEx3KBtl8wh1+ZBCUFguO4Oj+lAK4dNNHzAM31tYleOOqX+04oO56FKN282j?= =?us-ascii?Q?CeCdsVzjpL6kMF4BTlRGA6ShvS3kcuI/g/6Z6/7eRznfRCEqoyY8688uraZV?= =?us-ascii?Q?9ibZKL0y8umLjc9Iz08Eb/h6zFJPfjjFNNBwKVwKMgt5bgm3uERyTd7EiNtS?= =?us-ascii?Q?/TPBJb3OS6X+7O9LqdY27RA1SRmAvP7NhpO+HF+BsvRDm1WNibelOZe8vZoT?= =?us-ascii?Q?HuQelWgpwhDlCN1GZgD0qF1iuVM+OFALg2RgxY6xHBjIvf88tZf1bE+Jn/Q5?= =?us-ascii?Q?pwdstNQJGtGGR5MN+7wZHqQhgJxIBiQx/wNsW/jlJ61SsPCojZt2QmYGx8Em?= =?us-ascii?Q?aXGF+iYg5eUGfgHfchcevWrwKgmO2GaEugqpQr5VhjwZOJ1iIcxYagYoJU96?= =?us-ascii?Q?lCBOq2SpfUuQKBAXMSXbmYvL9MEmOAWsc6zBNmUh8P31y2bE0kfneqjbXAAL?= =?us-ascii?Q?AF/NcgZG73TApzKHSR/EkU8y3JxASgQy+catuEKFZH3Pe+d+WU3JSaqlaj87?= =?us-ascii?Q?zqVRlwd3+VcJy4JnJ0jgdNEMKmoB0fzhiW+tnNaTvz+dohuARYnqpnkZBL8U?= =?us-ascii?Q?1NkaE0Hi39xDbWLkiLxnDHVDzCWvEXYeXt2uNyeZntmMfVkVPbLq0Q1S8f69?= =?us-ascii?Q?RyLSl8pNsFZCF6JisWCF6Ph0kjVB4n3GRbFvfw7mzuMvSUcPnHkEw+mqq8MJ?= =?us-ascii?Q?6lRYIjagSDO3eB5AlxKR1fBWPpZJnJ/sPE0mamTgzIeF9BlSRi+bLu9kFezq?= =?us-ascii?Q?q2PuUI9vuX9952CeWNShwQd7X7NG4Me8TN4Z/eJ/gbTFpkUkGWElP8IsjD92?= =?us-ascii?Q?XoRfbPHSMYDv/eH+6hiEV+fxgMyS+4O/P+1eN1a+FMaliJj9+8/RlLGSAMf2?= =?us-ascii?Q?WBZJVGqlHnZl0JdhHvw+/v7WUeVIkm4hILaDDJ+O3F1iTU1+g18mHzcIJtm3?= =?us-ascii?Q?6dw2vCijajmoHVOx4XLtbaJppXVI3wXXShoBqn/VMNDhgcf4xhAcmW9CNKn4?= =?us-ascii?Q?A/G9PmELwnyvH/7kZwgb86jNcDna9IvY3xDJclgwaXAgLEz3GIEXKDj+RKuI?= =?us-ascii?Q?BvReVvLwXLeOJE16vaEUsA/1nmCibdhNTOLwfCN/2AaSr6ZhKJOOKdoqqALq?= =?us-ascii?Q?wnkd80U+vd+Rb5DIufr2mXJKWskRzX4h7dDrUeiDC+Cyk6l20xqHs/xDxIxQ?= =?us-ascii?Q?jx87LY3z/fb0QtLKL7vBcK567SuKLbTIbWEhWO/K2CwNt6g+Ry1E4R7O3lds?= =?us-ascii?Q?uu721fK7fkz66RRchaMlR5OVlkVc9Zjf5DGQlqsPunNfTi8/pFs5hShh71Sk?= =?us-ascii?Q?sMKhrnAqKGrrSx6QPOJv6sY5P/VHOAo4Na2odXFpcoaVOi26pV0bSieC10t7?= =?us-ascii?Q?M1iaH4+VHklHBB5St/w=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(82310400026)(36860700013)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Oct 2025 06:45:19.5086 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4e89a69d-fd86-4284-363f-08de11ffbbae X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE31.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB8813 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Until now, IPoIB was creating TIRs without setting self loopback prevention, then modifying them in activation stage. This is a preparation patch, that will be used by IPoIB to init TIRs properly without the need for following calls of modify_tir. Signed-off-by: Tariq Toukan Reviewed-by: Carolina Jubran --- drivers/net/ethernet/mellanox/mlx5/core/en/rss.c | 2 ++ drivers/net/ethernet/mellanox/mlx5/core/en/rss.h | 1 + drivers/net/ethernet/mellanox/mlx5/core/en/rx_res.c | 7 +++++++ drivers/net/ethernet/mellanox/mlx5/core/en/rx_res.h | 1 + 4 files changed, 11 insertions(+) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/rss.c b/drivers/net= /ethernet/mellanox/mlx5/core/en/rss.c index c96cbc4b0dbf..88b0e1050d1a 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/rss.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/rss.c @@ -231,6 +231,8 @@ mlx5e_rss_create_tir(struct mlx5e_rss *rss, enum mlx5_t= raffic_types tt, rqtn, rss_inner); mlx5e_tir_builder_build_packet_merge(builder, pkt_merge_param); rss_tt =3D mlx5e_rss_get_tt_config(rss, tt); + mlx5e_tir_builder_build_self_lb_block(builder, rss->params.self_lb_blk, + rss->params.self_lb_blk); mlx5e_tir_builder_build_rss(builder, &rss->hash, &rss_tt, inner); =20 err =3D mlx5e_tir_init(tir, builder, rss->mdev, true); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/rss.h b/drivers/net= /ethernet/mellanox/mlx5/core/en/rss.h index 5fb03cd0a411..17664757a561 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/rss.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/rss.h @@ -23,6 +23,7 @@ struct mlx5e_rss_init_params { struct mlx5e_rss_params { bool inner_ft_support; u32 drop_rqn; + bool self_lb_blk; }; =20 struct mlx5e_rss_params_traffic_type diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/rx_res.c b/drivers/= net/ethernet/mellanox/mlx5/core/en/rx_res.c index ac26a32845d0..55c117b7d8c4 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/rx_res.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/rx_res.c @@ -71,6 +71,8 @@ static int mlx5e_rx_res_rss_init_def(struct mlx5e_rx_res = *res, rss_params =3D (struct mlx5e_rss_params) { .inner_ft_support =3D inner_ft_support, .drop_rqn =3D res->drop_rqn, + .self_lb_blk =3D + res->features & MLX5E_RX_RES_FEATURE_SELF_LB_BLOCK, }; =20 rss =3D mlx5e_rss_init(res->mdev, &rss_params, &init_params); @@ -104,6 +106,8 @@ int mlx5e_rx_res_rss_init(struct mlx5e_rx_res *res, u32= rss_idx, unsigned int in rss_params =3D (struct mlx5e_rss_params) { .inner_ft_support =3D inner_ft_support, .drop_rqn =3D res->drop_rqn, + .self_lb_blk =3D + res->features & MLX5E_RX_RES_FEATURE_SELF_LB_BLOCK, }; =20 rss =3D mlx5e_rss_init(res->mdev, &rss_params, &init_params); @@ -346,6 +350,7 @@ static struct mlx5e_rx_res *mlx5e_rx_res_alloc(struct m= lx5_core_dev *mdev, unsig static int mlx5e_rx_res_channels_init(struct mlx5e_rx_res *res) { bool inner_ft_support =3D res->features & MLX5E_RX_RES_FEATURE_INNER_FT; + bool self_lb_blk =3D res->features & MLX5E_RX_RES_FEATURE_SELF_LB_BLOCK; struct mlx5e_tir_builder *builder; int err =3D 0; int ix; @@ -376,6 +381,8 @@ static int mlx5e_rx_res_channels_init(struct mlx5e_rx_r= es *res) mlx5e_rqt_get_rqtn(&res->channels[ix].direct_rqt), inner_ft_support); mlx5e_tir_builder_build_packet_merge(builder, &res->pkt_merge_param); + mlx5e_tir_builder_build_self_lb_block(builder, self_lb_blk, + self_lb_blk); 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Here we set the proper configuration in init, to allow skipping the modify_tirs commands on new firmware in a downstream patch. Signed-off-by: Tariq Toukan Reviewed-by: Carolina Jubran --- drivers/net/ethernet/mellanox/mlx5/core/ipoib/ipoib.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/ipoib/ipoib.c b/driver= s/net/ethernet/mellanox/mlx5/core/ipoib/ipoib.c index 49ab0de762c9..7f3f6d7edb38 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/ipoib/ipoib.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/ipoib/ipoib.c @@ -409,6 +409,7 @@ static void mlx5i_destroy_flow_steering(struct mlx5e_pr= iv *priv) static int mlx5i_init_rx(struct mlx5e_priv *priv) { struct mlx5_core_dev *mdev =3D priv->mdev; + enum mlx5e_rx_res_features features; int err; =20 priv->fs =3D mlx5e_fs_init(priv->profile, mdev, @@ -427,7 +428,9 @@ static int mlx5i_init_rx(struct mlx5e_priv *priv) goto err_destroy_q_counters; } =20 - priv->rx_res =3D mlx5e_rx_res_create(priv->mdev, 0, priv->max_nch, priv->= drop_rq.rqn, + features =3D MLX5E_RX_RES_FEATURE_SELF_LB_BLOCK; + priv->rx_res =3D mlx5e_rx_res_create(priv->mdev, features, priv->max_nch, + priv->drop_rq.rqn, &priv->channels.params.packet_merge, priv->channels.params.num_channels); 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Wed, 22 Oct 2025 23:45:07 -0700 From: Tariq Toukan To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , , , , Gal Pressman , "Carolina Jubran" , Dragos Tatulea Subject: [PATCH net-next 5/7] net/mlx5e: Do not re-apply TIR loopback configuration if not necessary Date: Thu, 23 Oct 2025 09:43:38 +0300 Message-ID: <1761201820-923638-6-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1761201820-923638-1-git-send-email-tariqt@nvidia.com> References: <1761201820-923638-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000A34C:EE_|SN7PR12MB7346:EE_ X-MS-Office365-Filtering-Correlation-Id: da27cbd6-98ac-4a8f-b34f-08de11ffbedc X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|376014|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?0E8j1yaLG7YMBKwtognUqqHyDWf0Y1wNhIQWu37zFW+px+06u8JrSxQNHi4j?= =?us-ascii?Q?FfVML6EiB/BYXHHujdC21SgywV1TywUhEa75SE3fwELqa/oq1tA13oAq0ZA2?= =?us-ascii?Q?1r4p80pwZx6YYkkSo5OzIeLKcacADHH9iMapDVORofV0LImQX6UJZxZ5KiTG?= =?us-ascii?Q?agCpniU/u+h/ik+KzdaYEKitD5C7/JB9/NZVDcDsUqInt5BR+Zdmf8eKjWQw?= =?us-ascii?Q?+HUDvZiEHr4iGzUFRRrrxSyiqs1SM2ekk79Ywjc36cLyMbcl8DQboRGSchkh?= =?us-ascii?Q?ZyeRyXHCXMbNFb5fp6W8iBH4G4UzP/knvY7HILZnrVbx9JArE7J1YTUjlHwp?= =?us-ascii?Q?rEfsErWCdC8G/J781ZBlOyjZ/ifrHeAPBi50xKLLmphF5HRklhVS50n/Ivbs?= =?us-ascii?Q?iC98CbjM+7+UDTVXyeIj96bilPw9JkFlDCqKpt9BN7DZK3GEHytMvcnIdY6g?= =?us-ascii?Q?64weYhGy5eubgyo8t7tN4vRWiR2qBt1KzDRIVFIM3ONoSsyl9jVCFocinvEO?= =?us-ascii?Q?M9WBYaQbeE5LWjemvp4YHXRJIn1IHL+zmkbqVHJTiPQPfVCHXusEKDsLstkE?= =?us-ascii?Q?lkbLa/oHarNRiC/YtFs674SrbodLXowEmEBngo40BFDNP1skRmpuCpMUxTgx?= =?us-ascii?Q?AFd4UwmmZxXA2I8qspPN0smxkVwFGgR1eT9Fx5Baj9YlAaol9cd/GLfe9w65?= =?us-ascii?Q?KgRame2Ni6koGQEOuTv+8T+rsPkpDQVKl6zmAAqrxfQy/hz+03YxQ4za1PLT?= =?us-ascii?Q?RbbRU0SMkoBQ6lQvPFnbj4gZYuH7LoVyH6WZi8QUcX7VWRtFDa1ej29Tek/I?= =?us-ascii?Q?O3uCbBAH8qYYykmB3RNLiC+MoQLdmZRjwGXd269OqueGC+IUaAnsM15i+vAY?= =?us-ascii?Q?Cqf0Rv6UhOCsed/EL0vG31deVVZgpdFRkdFBTZkHdQU8W1Y3RDIb8i41R6KU?= =?us-ascii?Q?5tN9+jspd7xB/Q4oz57IZXkyzXIRcMBTuNDIa+T+UmNb0pqaDseh1/S/oJuu?= =?us-ascii?Q?0vAQ+ep4pZNRviIE7zz1pS1Drb6aqpC8IhUSDQNlV6vbyGzIsx8sB17sqZTT?= =?us-ascii?Q?R5h8plvyDgJgDtS6M+EutB8WsPH7tq/i86dUtyxi9tiajNVbMbc6RqIIBzjP?= =?us-ascii?Q?qzXUbtqumZ0coiQIyJGp5rSXttp7nKjHk+nR9V9GAvIxvIOY6SITxYkqdxi4?= =?us-ascii?Q?oFUVMiMNv5jQT59wG4BTMLo6eknBSFRrazkr7h4a6iEitR30uT6TL+ghOxAy?= =?us-ascii?Q?LOqqRF08UKNW2E4Iy7yhJXTWwacwrl/RzvPLCjnBJg1iOayO3bTFJd9JQNlE?= =?us-ascii?Q?FnWl5EsTW8SKihuGfMf9m5zk84c5xJqL4Vp65H6vfvCMIEJs+zKRc9MYWY9D?= =?us-ascii?Q?AByrwayQS2kKVANt2ksA8EWYp/T1fDXHFZNHQf3jvhu+Jm87UcgcwiBjH+WM?= =?us-ascii?Q?dhFHSoTS7PzRhbpjgCZiqtmxwY7j2R77gu8whSq66NLyIq1FClvBbFpG+McB?= =?us-ascii?Q?EifXfXbTbNCx6FMuY6g9ItF+UuLWw4Kp8UiGRHqic9SmTNsIgeG2ePLrzwtu?= =?us-ascii?Q?LU9t3e5J69LnBOolWac=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(1800799024)(376014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Oct 2025 06:45:24.8107 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: da27cbd6-98ac-4a8f-b34f-08de11ffbedc X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000A34C.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB7346 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" On old firmware, (tis_tir_td_order=3D0), TIR of a transport domain should either be created after all SQs of the same domain, or TIR.self_lb_en should be reapplied using MODIFY_TIR, for self loopback filtering to function correctly. This is not necessary anymnore on new FW (tis_tir_td_order=3D1), thus there's no need for calling modify_tir operations after creating a new set of SQs to maintain the self loopback prevention functional. Skip these operations. This saves O(max_num_channels) MODIFY_TIR firmware commands in operations like interface up or channels configuration change. Signed-off-by: Tariq Toukan Reviewed-by: Carolina Jubran --- drivers/net/ethernet/mellanox/mlx5/core/en_common.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_common.c b/drivers/= net/ethernet/mellanox/mlx5/core/en_common.c index fad6b761f622..1d663c9597a3 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_common.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_common.c @@ -282,5 +282,8 @@ int mlx5e_modify_tirs_lb(struct mlx5_core_dev *mdev, bo= ol enable_uc_lb, int mlx5e_refresh_tirs(struct mlx5_core_dev *mdev, bool enable_uc_lb, bool enable_mc_lb) { + if (MLX5_CAP_GEN(mdev, tis_tir_td_order)) + return 0; /* refresh not needed */ + return mlx5e_modify_tirs_lb(mdev, enable_uc_lb, enable_mc_lb); } --=20 2.31.1 From nobody Sat Feb 7 12:19:23 2026 Received: from SN4PR2101CU001.outbound.protection.outlook.com (mail-southcentralusazon11012066.outbound.protection.outlook.com [40.93.195.66]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B24AC279DC9; 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This is in preparation for the next patch. Signed-off-by: Tariq Toukan Reviewed-by: Carolina Jubran --- .../net/ethernet/mellanox/mlx5/core/en_main.c | 25 +++++++++++++------ 1 file changed, 17 insertions(+), 8 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/en_main.c index 8e13f2542d8d..cd2842dcffcd 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c @@ -3356,12 +3356,12 @@ static int mlx5e_switch_priv_params(struct mlx5e_pr= iv *priv, } =20 static int mlx5e_switch_priv_channels(struct mlx5e_priv *priv, + struct mlx5e_channels *old_chs, struct mlx5e_channels *new_chs, mlx5e_fp_preactivate preactivate, void *context) { struct net_device *netdev =3D priv->netdev; - struct mlx5e_channels old_chs; int carrier_ok; int err =3D 0; =20 @@ -3370,7 +3370,6 @@ static int mlx5e_switch_priv_channels(struct mlx5e_pr= iv *priv, =20 mlx5e_deactivate_priv_channels(priv); =20 - old_chs =3D priv->channels; priv->channels =3D *new_chs; =20 /* New channels are ready to roll, call the preactivate hook if needed @@ -3379,12 +3378,12 @@ static int mlx5e_switch_priv_channels(struct mlx5e_= priv *priv, if (preactivate) { err =3D preactivate(priv, context); if (err) { - priv->channels =3D old_chs; + priv->channels =3D *old_chs; goto out; } } =20 - mlx5e_close_channels(&old_chs); + mlx5e_close_channels(old_chs); priv->profile->update_rx(priv); =20 mlx5e_selq_apply(&priv->selq); @@ -3403,16 +3402,20 @@ int mlx5e_safe_switch_params(struct mlx5e_priv *pri= v, mlx5e_fp_preactivate preactivate, void *context, bool reset) { - struct mlx5e_channels *new_chs; + struct mlx5e_channels *old_chs, *new_chs; int err; =20 reset &=3D test_bit(MLX5E_STATE_OPENED, &priv->state); if (!reset) return mlx5e_switch_priv_params(priv, params, preactivate, context); =20 + old_chs =3D kzalloc(sizeof(*old_chs), GFP_KERNEL); new_chs =3D kzalloc(sizeof(*new_chs), GFP_KERNEL); - if (!new_chs) - return -ENOMEM; + if (!old_chs || !new_chs) { + err =3D -ENOMEM; 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Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , , , , Gal Pressman , "Carolina Jubran" , Dragos Tatulea Subject: [PATCH net-next 7/7] net/mlx5e: Defer channels closure to reduce interface down time Date: Thu, 23 Oct 2025 09:43:40 +0300 Message-ID: <1761201820-923638-8-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1761201820-923638-1-git-send-email-tariqt@nvidia.com> References: <1761201820-923638-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000A34C:EE_|CH3PR12MB8879:EE_ X-MS-Office365-Filtering-Correlation-Id: 44e7d301-7073-4ff3-b79c-08de11ffc4f6 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|82310400026|36860700013|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?PLBTUHS48P/u+JOUj92YNki0NEnE9SXOu5/vZYtndvqoWrsIUh6aomqNxXUC?= =?us-ascii?Q?0Gb5gd8+I4UWYcDPnRZvJhg6IUos5vGt7llGaVWaEjBkT+/IA6EirmuhMHpm?= =?us-ascii?Q?ERpmWI3Fl4HMkSIIq+sRIRKWWoYHrlULbMX3NJ9w+/CeIwQsdwc+ByX18yTY?= =?us-ascii?Q?6YXg5SX5DwAaU12ZXOYk0y7oj7yzfnB0ADsBo8G5DTDKukXu24WwShwkWyQX?= =?us-ascii?Q?17T0f6Bptm55LMQXCmVe2wBKghh0cH23BZTfYNiFi1uUBEHxw1Ra3TAt2iG/?= =?us-ascii?Q?OmWVReUU2yC/OliavWzc0dKBGXmK1u3vLX1BL0SRcQ2hGCTjopD23Simr7/0?= =?us-ascii?Q?7iwlVq+IMWYG70PqZ1EP9HaRRqBErgDG03IGA4TI4CVTBVGxe3G448pvda/I?= =?us-ascii?Q?+noZPqmV/lsSUiAp4J1RSam8Tc7JFXPzRmHNv2ZP4e+rpr6maBjNB5NRZJtS?= =?us-ascii?Q?Ehe/zOed9672eSI4VQF/buXUDkyAFojamAdkQ8/REjvqOt7RiIyWi+iODgG1?= =?us-ascii?Q?bCWTFbmAJoV4tPGMAemfpKTwSWjQF4FhG45H2saJ6Iq5OO56pR8bb8ecP9zX?= =?us-ascii?Q?GnWTquBa4FSsxrDqPEaYkDDSDPe8TIF99sGLPfQfU1UBf2C4ORA+2OGejhGQ?= =?us-ascii?Q?S6oeRr3FWwckuTaVSfpQiCxHcJTW8nBbcDrLSvTsKwsJytLmax4S+tgkNzw6?= =?us-ascii?Q?+jtQhFF2MY6c+l25/La7aW1x4EOP2tblbDvrRWAbFPZ5oOEHVxrKTCbt6mnt?= =?us-ascii?Q?AeR8p0NxiVOO6L5ezBN8VtPouKzL0b+mEpkoB8Yo/ECqOCL3vxkWVC5ZR+Jr?= =?us-ascii?Q?hwsYZRE5Ji+P5Mu7Y4UtuLCLGWm7Sjw3OKEDsKrIkUyLxHu0ZohX6RpnnMbM?= =?us-ascii?Q?RNl/Wm82GrBeRv8wMAGEvSsxrB9dEUo6ExXrFxXurUKlyJpFrfPM2t3lLphV?= =?us-ascii?Q?EErpeCT1ejqIzollUodG5HAbiF4ySKwZ3/ashD1Cb8FmvtnII57Flnw7OOwC?= =?us-ascii?Q?QskSXsnbrcRLuCdorud1xw97Im2fepmw2qmaH8h+n0M37NjVcgMNPq++HTl0?= =?us-ascii?Q?SeemugsNBC41kF2+7eUJYaKvpyejHIJ05oWxDdcL47M81TUsEBk8Pk3rZQeg?= =?us-ascii?Q?q+uJUTv7sXDGeqNmwgAsav5sWk9q0YOH05+Mt0taGgHZMum8krN6khji7MA+?= =?us-ascii?Q?DvIu0BJhc1kjNjbRrVhb362Pv0aukCcpHF4OlUw4gLxAO78UD3C8C0XNc7jq?= =?us-ascii?Q?bmYcga7evifPZ2AHy3qeEnB2YglrX+ahZOrm4Re4ksCCbBkTR2Cphdq1RAcQ?= =?us-ascii?Q?2azKtPLXyB0X/j8tcRoQGI91Ng8sX4cG2S16rYMmqIWEoJfvrgShv9gm/NBH?= =?us-ascii?Q?dtutpWhQ7PE6D+rGP2RId+IvjdU6sJE0zYohwuxhH4Rp4S+VNSxCqGdXcEYe?= =?us-ascii?Q?nNLTJynZxHVlbDI+NHq9cr+Vru7Ts6if+k8lGFxXs88+YHuql3ae6ZKbn0f5?= =?us-ascii?Q?aFh20miCcA5ePDUlBpcsiL7nyGdBIIHfWrpI+0zASDQ8e0W6WlBBUUF0+jhl?= =?us-ascii?Q?yIAw0CfWgMX+0qHlrfE=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(82310400026)(36860700013)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Oct 2025 06:45:35.0562 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 44e7d301-7073-4ff3-b79c-08de11ffc4f6 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000A34C.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB8879 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Cap bit tis_tir_td_order=3D1 indicates that an old firmware requirement / limitation no longer exists. When unset, the latency of several firmware commands significantly increases with the presence of high number of co-existing channels (both old and new sets). Hence, we used to close unneeded old channels before invoking those firmware commands. Today, on capable devices, this is no longer the case. Minimize the interface down time by deferring the old channels closure, after the activation of the new ones. Perf numbers: Measured the number of dropped packets in a simple ping flood test, during a configuration change operation, that switches the number of channels from 247 to 248. Before: 71 packets lost After: 15 packets lost, ~80% saving. Signed-off-by: Tariq Toukan Reviewed-by: Carolina Jubran --- drivers/net/ethernet/mellanox/mlx5/core/en_main.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/en_main.c index cd2842dcffcd..a4c2c78660b0 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c @@ -3383,7 +3383,8 @@ static int mlx5e_switch_priv_channels(struct mlx5e_pr= iv *priv, } } =20 - mlx5e_close_channels(old_chs); + if (!MLX5_CAP_GEN(priv->mdev, tis_tir_td_order)) + mlx5e_close_channels(old_chs); priv->profile->update_rx(priv); =20 mlx5e_selq_apply(&priv->selq); @@ -3431,6 +3432,9 @@ int mlx5e_safe_switch_params(struct mlx5e_priv *priv, if (err) goto err_close; =20 + if (MLX5_CAP_GEN(priv->mdev, tis_tir_td_order)) + mlx5e_close_channels(old_chs); + kfree(new_chs); kfree(old_chs); return 0; --=20 2.31.1