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Sun, 5 Oct 2025 01:30:17 -0700 From: Tariq Toukan To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , , , , Gal Pressman , "Carolina Jubran" Subject: [PATCH net 1/3] net/mlx5: Prevent tunnel mode conflicts between FDB and NIC IPsec tables Date: Sun, 5 Oct 2025 11:29:57 +0300 Message-ID: <1759652999-858513-2-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1759652999-858513-1-git-send-email-tariqt@nvidia.com> References: <1759652999-858513-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF00004681:EE_|IA1PR12MB7590:EE_ X-MS-Office365-Filtering-Correlation-Id: 7186c8cc-49de-48af-bc46-08de03e97a9e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|376014|82310400026; X-Microsoft-Antispam-Message-Info: =?utf-8?B?MEU1SU9qK3hjanltQnM5V1V5YUM2WXhzTFZ1RlNSMWo5cFl1VVNoV0N0M1hE?= =?utf-8?B?blpNalQrQXlWYTFjZ2xBbkpRcUpHS0VFK21mTWpVU3hZL3RQTjRuMVgwbk1y?= =?utf-8?B?RG5HUU5GWWp3S01UQlhuUi85b3dGU0txd2g1Tk1YL2dOajd5b2NzZlFJc3c3?= =?utf-8?B?NHhoL3RHQXE4ajF0UVZhaC9rYkVwTG04U09ON3VDamZ6VjJ2dlhTTHpBNjVV?= =?utf-8?B?VGVSek9UNzMwWWJwZnVCSjZkMkhpQmt6VzZWV21qUDY1SlVVUHp0bTVDT2Zs?= =?utf-8?B?Vi9FMW9VbWRlcnAyZ3VSRVorSnM2TG8rMUxidUdlMC8yVjRQdTFseENudU5R?= =?utf-8?B?Uk9lTzVYNG4vdkxsZktVM2NRbjZmSGVBODM0V24vZzlvS1JFdGNzSDU1SEox?= =?utf-8?B?RE1OUThpNEhTT2ZXaDd3ZXhhRlNpSVhZeHJtYTAyeU1tYlFBZEZ0TGxaTzc4?= =?utf-8?B?V0luRnhVd0VCUWh2UmY5NU1ZalpCc3M4QjhITXlsTERKazI1VGc4SnhidHcw?= =?utf-8?B?Q2hPcWh6Nk9xV0Zzb1hYZHU3ZmF4dDQyMENhMGtjdmFXd3NWdG8yNGFyU2pj?= =?utf-8?B?ZDRKc2tDQ3IvNGE4NHNXRVJESmpvWGF0TC9FUmpITCtNNzdxajh3cC9BeWVB?= =?utf-8?B?NmVjdnpxODJOMDhyZjI0MEcyVkF0aWhOS3dLR3J0Z1lVN1ZYSWtqS2lRS0tv?= =?utf-8?B?SkFxNndJZ0IvdEp0MWF3MlNuOWE5TEltbWNoRGhRQXVuWFRsd00wTDJRcEFv?= =?utf-8?B?NVlxK2p0OHpQVkpNK0tUV0FtMGFRam9sYTJDdmNuMHkyK0xyeVVING9EaW1z?= =?utf-8?B?bE9FUlZaTXFYYlFJbEQwa2RvUE42MHVnanZRT2MzNklsQkdReWFtZmRmbnJ4?= =?utf-8?B?YndURGRrV2RXU0hBZ0ZlRUFKK2ZsTTIxT3BYQzh1M0xkYW9kMGxNVDhkbHFK?= =?utf-8?B?cGx2azUxS1hHWW85bHVhTlhCT0lNSlU0K29URWZaRWtHYTBnMEJKUEM5cnV4?= =?utf-8?B?UXBLbGh2clAyRlQrMXFIcEpLbWpwQ21rTFBiS3R2YlBSQzJsRGlvZk1qcDNB?= =?utf-8?B?M0E5OU9KcDM2bHIzTEpMNWw0U2QzVWIzR1ByZ09WRHFmbFZjM0ZaOXBIbnZB?= =?utf-8?B?bDRicEdtVjk4dk5NREN0MFlsV0Z0bFAvMm9mVFpUekNuZHMyTFA5MzExK0JN?= =?utf-8?B?VStmTjlEZ2YycUU5d0hFYzV4RElkekU1Nm52em1FTFBBakFuQ05QN2RPMndY?= =?utf-8?B?Z1B2c3BMSUxreS96b0hxN1crOTlkVWVRa0JKOCt1bllVUGpkZXRuK3F3OXMr?= =?utf-8?B?OFNOaGxPWk5FWG9rMEJRMFNONHZsN1VIRTNITUdVZ04rSmRFV09QRVRCZmRh?= =?utf-8?B?T2UzZWFmc1cyV29RQUVBTHJFam9PWXpvK2x1UjB0V3loaGxkVUs1eWxLV3V0?= =?utf-8?B?WmR6SFpWRjZucnRXdjdGWjRVS0Z3NlJpbWVxUjFFYUIyQkJtYW84cEVKNkNo?= =?utf-8?B?ZjJTTDlrZWhONmhwblZyM0Fyd2Vab3B1SytPbTIvYnZCcTg5aHh1UUIrU0lo?= =?utf-8?B?eU1FR1pZZDg0ODRXTE9waFgxdHU1MXNJTFdHUXV3cVd6b05uZVE4cjB0Vml3?= =?utf-8?B?ZzYvbHBpYVlkZFg0ck5YV2wvRFE1L2JEMVVIdGo4UHZsTlBrTlFXbHI1MjVx?= =?utf-8?B?OWYyNUg1OW1NSm1sWFduVllwZHI1aWpvMWZwS1FOMVpDNUJraUhKbzVSNG5N?= =?utf-8?B?NHE1UUJyemxMV1VndGxxRlQxcnppNEgvTlJFVS9IQkZTZEY5NmZ5QzgzbVNx?= =?utf-8?B?VWRQSjJMK1pOZDFpRi9nQmVTYkJZLzNHR2tydTc2UzdHM1BzVE9QdGRndG1r?= =?utf-8?B?Q1BGUTFCek1EaUpDejFqd2d3cXlpaW8yMDZ3L3FLT3lrYTJWVUhiUjVYRjdZ?= =?utf-8?B?QXlyazZxR3lLUjQ5dUEweDFqVmoyMDFnK2RlREFyZCtJaUU3YWtyMUZqRFpm?= =?utf-8?B?RzhPa1FJTk5lNVBGVmYxWEV1aEZJcDRrTW1SOTlmbUlwUFhwVGxSZDFNWDhD?= =?utf-8?B?VEwzcVVnZDJUeG8vVGlmWlR2c3Y2NHVkZlV2UVpZL3ZHYWFzZjJEUUFEVDVW?= =?utf-8?Q?uCTo=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(36860700013)(376014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Oct 2025 08:30:45.0817 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7186c8cc-49de-48af-bc46-08de03e97a9e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF00004681.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB7590 From: Carolina Jubran When creating IPsec flow tables with tunnel mode enabled, the driver uses mlx5_eswitch_block_encap() to prevent tunnel encapsulation conflicts across different domains (NIC_RX/NIC_TX and FDB), since the firmware doesn=E2=80=99t allow both at the same time. Currently, the driver attempts to reserve tunnel mode unconditionally for both NIC and FDB IPsec tables. This can lead to conflicting tunnel mode setups, for example, if a flow table was created in the FDB domain with tunnel offload enabled, and we later try to create another one in the NIC, or vice versa. To resolve this, adjust the blocking logic so that tunnel mode is only reserved by NIC flows. This ensures that tunnel offload is exclusively used in either the NIC or the FDB, and avoids unintended offload conflicts. Fixes: 1762f132d542 ("net/mlx5e: Support IPsec packet offload for RX in swi= tchdev mode") Fixes: c6c2bf5db4ea ("net/mlx5e: Support IPsec packet offload for TX in swi= tchdev mode") Signed-off-by: Carolina Jubran Reviewed-by: Jianbo Liu Reviewed-by: Leon Romanovsky Signed-off-by: Tariq Toukan --- .../mellanox/mlx5/core/en_accel/ipsec_fs.c | 8 ++++++-- .../net/ethernet/mellanox/mlx5/core/eswitch.h | 5 +++-- .../mellanox/mlx5/core/eswitch_offloads.c | 18 ++++++++++-------- 3 files changed, 19 insertions(+), 12 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_fs.c b/= drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_fs.c index 6ccfc2af07b7..0bc080274584 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_fs.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_fs.c @@ -1069,7 +1069,9 @@ static int rx_create(struct mlx5_core_dev *mdev, stru= ct mlx5e_ipsec *ipsec, =20 /* Create FT */ if (mlx5_ipsec_device_caps(mdev) & MLX5_IPSEC_CAP_TUNNEL) - rx->allow_tunnel_mode =3D mlx5_eswitch_block_encap(mdev); + rx->allow_tunnel_mode =3D + mlx5_eswitch_block_encap(mdev, rx =3D=3D ipsec->rx_esw); + if (rx->allow_tunnel_mode) flags =3D MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT; ft =3D ipsec_ft_create(attr.ns, attr.sa_level, attr.prio, 1, 2, flags); @@ -1310,7 +1312,9 @@ static int tx_create(struct mlx5e_ipsec *ipsec, struc= t mlx5e_ipsec_tx *tx, goto err_status_rule; =20 if (mlx5_ipsec_device_caps(mdev) & MLX5_IPSEC_CAP_TUNNEL) - tx->allow_tunnel_mode =3D mlx5_eswitch_block_encap(mdev); + tx->allow_tunnel_mode =3D + mlx5_eswitch_block_encap(mdev, tx =3D=3D ipsec->tx_esw); + if (tx->allow_tunnel_mode) flags =3D MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT; ft =3D ipsec_ft_create(tx->ns, attr.sa_level, attr.prio, 1, 4, flags); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h b/drivers/ne= t/ethernet/mellanox/mlx5/core/eswitch.h index df3756d7e52e..16eb99aba2a7 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h @@ -879,7 +879,7 @@ void mlx5_eswitch_offloads_single_fdb_del_one(struct ml= x5_eswitch *master_esw, struct mlx5_eswitch *slave_esw); int mlx5_eswitch_reload_ib_reps(struct mlx5_eswitch *esw); =20 -bool mlx5_eswitch_block_encap(struct mlx5_core_dev *dev); +bool mlx5_eswitch_block_encap(struct mlx5_core_dev *dev, bool from_fdb); void mlx5_eswitch_unblock_encap(struct mlx5_core_dev *dev); =20 int mlx5_eswitch_block_mode(struct mlx5_core_dev *dev); @@ -974,7 +974,8 @@ mlx5_eswitch_reload_ib_reps(struct mlx5_eswitch *esw) return 0; } =20 -static inline bool mlx5_eswitch_block_encap(struct mlx5_core_dev *dev) +static inline bool +mlx5_eswitch_block_encap(struct mlx5_core_dev *dev, bool from_fdb) { return true; } diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c b/d= rivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c index 52c3de24bea3..4cf995be127d 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c @@ -4006,23 +4006,25 @@ int mlx5_devlink_eswitch_inline_mode_get(struct dev= link *devlink, u8 *mode) return esw_inline_mode_to_devlink(esw->offloads.inline_mode, mode); } =20 -bool mlx5_eswitch_block_encap(struct mlx5_core_dev *dev) +bool mlx5_eswitch_block_encap(struct mlx5_core_dev *dev, bool from_fdb) { struct mlx5_eswitch *esw =3D dev->priv.eswitch; + enum devlink_eswitch_encap_mode encap; + bool allow_tunnel =3D false; =20 if (!mlx5_esw_allowed(esw)) return true; =20 down_write(&esw->mode_lock); - if (esw->mode !=3D MLX5_ESWITCH_LEGACY && - esw->offloads.encap !=3D DEVLINK_ESWITCH_ENCAP_MODE_NONE) { - up_write(&esw->mode_lock); - return false; + encap =3D esw->offloads.encap; + if (esw->mode =3D=3D MLX5_ESWITCH_LEGACY || + (encap =3D=3D DEVLINK_ESWITCH_ENCAP_MODE_NONE && !from_fdb)) { + allow_tunnel =3D true; + esw->offloads.num_block_encap++; } - - esw->offloads.num_block_encap++; up_write(&esw->mode_lock); - return true; + + return allow_tunnel; } =20 void mlx5_eswitch_unblock_encap(struct mlx5_core_dev *dev) --=20 2.31.1 From nobody Wed Dec 17 19:19:08 2025 Received: from MW6PR02CU001.outbound.protection.outlook.com (mail-westus2azon11012039.outbound.protection.outlook.com [52.101.48.39]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D54AF1F12F4; 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This is incorrect, because tunnel mode is only permitted under specific encapsulation settings, and that decision is already made when the flow table is created. The offending commit attempted to block this case in the state add path, but the check there happens too late and does not prevent the reformat from being configured. Fix by taking short reservations for both the eswitch mode and the encap at the start of state setup. This preserves the block ordering (mode --> encap) used later: the mode is blocked during RX/TX get, and the encap is blocked during flow-table creation. This lets us fail early if either reservation cannot be obtained, it means a mode transition is underway or a conflicting configuration already owns encap. If both succeed, the flow-table path later takes the ownership and the reservations are released on exit. Fixes: 146c196b60e4 ("net/mlx5e: Create IPsec table with tunnel support onl= y when encap is disabled") Signed-off-by: Carolina Jubran Reviewed-by: Jianbo Liu Reviewed-by: Leon Romanovsky Signed-off-by: Tariq Toukan --- .../mellanox/mlx5/core/en_accel/ipsec.c | 38 +++++++++++++------ .../mellanox/mlx5/core/en_accel/ipsec.h | 2 +- .../mellanox/mlx5/core/en_accel/ipsec_fs.c | 24 +++++++----- 3 files changed, 43 insertions(+), 21 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.c b/dri= vers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.c index 00e77c71e201..0a4fb8c92268 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.c @@ -772,6 +772,7 @@ static int mlx5e_xfrm_add_state(struct net_device *dev, struct netlink_ext_ack *extack) { struct mlx5e_ipsec_sa_entry *sa_entry =3D NULL; + bool allow_tunnel_mode =3D false; struct mlx5e_ipsec *ipsec; struct mlx5e_priv *priv; gfp_t gfp; @@ -803,6 +804,20 @@ static int mlx5e_xfrm_add_state(struct net_device *dev, goto err_xfrm; } =20 + if (mlx5_eswitch_block_mode(priv->mdev)) + goto unblock_ipsec; + + if (x->props.mode =3D=3D XFRM_MODE_TUNNEL && + x->xso.type =3D=3D XFRM_DEV_OFFLOAD_PACKET) { + allow_tunnel_mode =3D mlx5e_ipsec_fs_tunnel_allowed(sa_entry); + if (!allow_tunnel_mode) { + NL_SET_ERR_MSG_MOD(extack, + "Packet offload tunnel mode is disabled due to encap settings"); + err =3D -EINVAL; + goto unblock_mode; + } + } + /* check esn */ if (x->props.flags & XFRM_STATE_ESN) mlx5e_ipsec_update_esn_state(sa_entry); @@ -817,7 +832,7 @@ static int mlx5e_xfrm_add_state(struct net_device *dev, =20 err =3D mlx5_ipsec_create_work(sa_entry); if (err) - goto unblock_ipsec; + goto unblock_encap; =20 err =3D mlx5e_ipsec_create_dwork(sa_entry); if (err) @@ -832,14 +847,6 @@ static int mlx5e_xfrm_add_state(struct net_device *dev, if (err) goto err_hw_ctx; =20 - if (x->props.mode =3D=3D XFRM_MODE_TUNNEL && - x->xso.type =3D=3D XFRM_DEV_OFFLOAD_PACKET && - !mlx5e_ipsec_fs_tunnel_enabled(sa_entry)) { - NL_SET_ERR_MSG_MOD(extack, "Packet offload tunnel mode is disabled due t= o encap settings"); - err =3D -EINVAL; - goto err_add_rule; - } - /* We use *_bh() variant because xfrm_timer_handler(), which runs * in softirq context, can reach our state delete logic and we need * xa_erase_bh() there. @@ -855,8 +862,7 @@ static int mlx5e_xfrm_add_state(struct net_device *dev, queue_delayed_work(ipsec->wq, &sa_entry->dwork->dwork, MLX5_IPSEC_RESCHED); =20 - if (x->xso.type =3D=3D XFRM_DEV_OFFLOAD_PACKET && - x->props.mode =3D=3D XFRM_MODE_TUNNEL) { + if (allow_tunnel_mode) { xa_lock_bh(&ipsec->sadb); __xa_set_mark(&ipsec->sadb, sa_entry->ipsec_obj_id, MLX5E_IPSEC_TUNNEL_SA); @@ -865,6 +871,11 @@ static int mlx5e_xfrm_add_state(struct net_device *dev, =20 out: x->xso.offload_handle =3D (unsigned long)sa_entry; + if (allow_tunnel_mode) + mlx5_eswitch_unblock_encap(priv->mdev); + + mlx5_eswitch_unblock_mode(priv->mdev); + return 0; =20 err_add_rule: @@ -877,6 +888,11 @@ static int mlx5e_xfrm_add_state(struct net_device *dev, if (sa_entry->work) kfree(sa_entry->work->data); kfree(sa_entry->work); +unblock_encap: + if (allow_tunnel_mode) + mlx5_eswitch_unblock_encap(priv->mdev); +unblock_mode: + mlx5_eswitch_unblock_mode(priv->mdev); unblock_ipsec: mlx5_eswitch_unblock_ipsec(priv->mdev); err_xfrm: diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.h b/dri= vers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.h index 23703f28386a..5d7c15abfcaf 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.h @@ -319,7 +319,7 @@ void mlx5e_accel_ipsec_fs_del_rule(struct mlx5e_ipsec_s= a_entry *sa_entry); int mlx5e_accel_ipsec_fs_add_pol(struct mlx5e_ipsec_pol_entry *pol_entry); void mlx5e_accel_ipsec_fs_del_pol(struct mlx5e_ipsec_pol_entry *pol_entry); void mlx5e_accel_ipsec_fs_modify(struct mlx5e_ipsec_sa_entry *sa_entry); -bool mlx5e_ipsec_fs_tunnel_enabled(struct mlx5e_ipsec_sa_entry *sa_entry); +bool mlx5e_ipsec_fs_tunnel_allowed(struct mlx5e_ipsec_sa_entry *sa_entry); =20 int mlx5_ipsec_create_sa_ctx(struct mlx5e_ipsec_sa_entry *sa_entry); void mlx5_ipsec_free_sa_ctx(struct mlx5e_ipsec_sa_entry *sa_entry); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_fs.c b/= drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_fs.c index 0bc080274584..bf1d2769d4f1 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_fs.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_fs.c @@ -2850,18 +2850,24 @@ void mlx5e_accel_ipsec_fs_modify(struct mlx5e_ipsec= _sa_entry *sa_entry) memcpy(sa_entry, &sa_entry_shadow, sizeof(*sa_entry)); } =20 -bool mlx5e_ipsec_fs_tunnel_enabled(struct mlx5e_ipsec_sa_entry *sa_entry) +bool mlx5e_ipsec_fs_tunnel_allowed(struct mlx5e_ipsec_sa_entry *sa_entry) { - struct mlx5_accel_esp_xfrm_attrs *attrs =3D &sa_entry->attrs; - struct mlx5e_ipsec_rx *rx; - struct mlx5e_ipsec_tx *tx; + struct mlx5e_ipsec *ipsec =3D sa_entry->ipsec; + struct xfrm_state *x =3D sa_entry->x; + bool from_fdb; =20 - rx =3D ipsec_rx(sa_entry->ipsec, attrs->addrs.family, attrs->type); - tx =3D ipsec_tx(sa_entry->ipsec, attrs->type); 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Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , , , , Gal Pressman , Cosmin Ratiu Subject: [PATCH net 3/3] net/mlx5e: Do not fail PSP init on missing caps Date: Sun, 5 Oct 2025 11:29:59 +0300 Message-ID: <1759652999-858513-4-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1759652999-858513-1-git-send-email-tariqt@nvidia.com> References: <1759652999-858513-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF00004683:EE_|PH7PR12MB6585:EE_ X-MS-Office365-Filtering-Correlation-Id: d61a6d9a-011e-4aea-6382-08de03e97f36 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|36860700013|376014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?3r7Na+YYKGQePhyktuWs1TLe4HJcQEKCZE1gw9dVYxxpqI7rzbt8UEiFS6Ho?= =?us-ascii?Q?w9qj7uVVFkdVaAf1+uGpy2K0mS9QUxk9mm9DW1ngdNTwCQJu7QMBauzsrRt0?= =?us-ascii?Q?G2ghhMp4tNYr4brxPZiNwtMdZY/fG76JPVeJ2oIgNJpHwbC+AbeF9nAhsXcZ?= =?us-ascii?Q?zvlA4DcW/rKbKLI8omjQIEfM8KAbGFhNeASONDUYgvvKqzBpFPZWTisSB+cq?= =?us-ascii?Q?3EyukYTEWPU9Ys0Qr5va2zUsspOFyUwwlaymS1lNwTICcFGFfiUAkk+GpCBh?= =?us-ascii?Q?yxRBru4kaJYoUVeU0OuOy29PivX8PFmNIy0i3dGKF0p6AWWWmhKSeJ3kpQ2W?= =?us-ascii?Q?7YUjIIFCCzIBrwfLr3PeH+T14agxVO5tRC1bNXgu4oDKXvXFtkaIYbL1UHeX?= =?us-ascii?Q?SfhHc87Js8alybUPc26Aq6zIqskCOW5e/ROvDUlBnedU1/ZzdKg3QGzbCDK3?= =?us-ascii?Q?ZJi9134c3gBbH/8JeNMraJAJhN1abFPfH4rC7RjhZ3gCKWZ4tykyaARVN5BX?= =?us-ascii?Q?Q/kHNuJv6uKMmLZPoDpVWmY9+YL+lUrrBKeASts+kzDILyeFPXvXndgelofQ?= =?us-ascii?Q?/MJY8P3G+ks9t65mn48FI04rn7qLaECcRX/8QraeOuRc6EPQ3RTCEKeGazmM?= =?us-ascii?Q?cWzULwP++ArvB/E3LiaPipC2udyrIJ/TdoCALXTCU2ParOHAiE2cjrieetrY?= =?us-ascii?Q?o5R6jCB0ICTWHg1HldrtwpQtFR0WVeGDoociCnervu91AtDunVq5Gfkey5iv?= =?us-ascii?Q?UkvfD3Oel5PLYuZTOvhBFowFU2YEZjJ1kC+aGBVJ/22X0wxnDqbtKohAp2Ix?= =?us-ascii?Q?O87/4fmhOC3ki2I6wLud1KXJkrXseX09ydcdvnQW9BG/WvISoOfcEzDzWDzI?= =?us-ascii?Q?iUNzy5WXH3k1sFSTdngAXI58Gyvks/wI8RGcbTKVkCxiKsYsrI67ZB433ibb?= =?us-ascii?Q?+fF/EmPQufc9K1A4Ce+UiETm6rsXuxsXagpQVmIiqyCVEPd+UtdI9i/BtZZo?= =?us-ascii?Q?yiRWXXzO/lI9KDNgRVI8PSK5ViXBYqSG+B5pLinY1arDfdq4PE1ezOow7NVC?= =?us-ascii?Q?xqb43nQhl47xRfCVYbnN34sMaPhVjmVky/7LUA02zGqzVDxaYoktuPH8wYCP?= =?us-ascii?Q?0fkPq0h+7gqzWSReuM37KSnBVqQiv5LQTTY5OlbNNuKVS5LYLyc70mZCXuz0?= =?us-ascii?Q?6h7wh9WPDysCZc1Bsbvoc7ybnNB/od8ktNDCq2VMzNYDJcbzeDVxuDJqDBq/?= =?us-ascii?Q?8qkYHqdlsA47YbZxpEaeEyH9zFTsRftwQdKRcH8An7KN4dMV+CLCzkYrco49?= =?us-ascii?Q?lODl5l7DPkIZyEM4o+sGuuHma5amgzIdKtWg+XrK2WOZysabC43lylRb8BZE?= =?us-ascii?Q?lFjrfqmSzzibwNyBSU0+HnLlIwHGla8aUpelMJadl8QFEIAww9Zj9/atEtzU?= =?us-ascii?Q?uQTLE1qCKPVQIw93HLnV8eJTwAw1P80M954298PkPzMwuurbqsmGdd7mzzRn?= =?us-ascii?Q?uP6QKlY0jiOciXQJk9376GTzR/KHlExA55SnWkvf1Scn1YFvD2/qtNe1Jsiu?= =?us-ascii?Q?UzENEWLYby1mOPh+RE8=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(36860700013)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Oct 2025 08:30:52.7888 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d61a6d9a-011e-4aea-6382-08de03e97f36 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF00004683.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6585 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Cosmin Ratiu PSP support requires a set of cap bits to be set, otherwise an init error is logged. But logging an error when PSP cannot be initialized is too much, and not in line with other features. If a feature cannot be initialized because it is not supported, that's not an error. An error should only be printed when the feature cannot be initialized because of an actual error. Fixes: 89ee2d92f66c ("net/mlx5e: Support PSP offload functionality") Signed-off-by: Cosmin Ratiu Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/en_accel/psp.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/psp.c b/drive= rs/net/ethernet/mellanox/mlx5/core/en_accel/psp.c index b4cb131c5f81..8565cfe8d7dc 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/psp.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/psp.c @@ -893,27 +893,27 @@ int mlx5e_psp_init(struct mlx5e_priv *priv) =20 if (!mlx5_is_psp_device(mdev)) { mlx5_core_dbg(mdev, "PSP offload not supported\n"); - return -EOPNOTSUPP; + return 0; } =20 if (!MLX5_CAP_ETH(mdev, swp)) { mlx5_core_dbg(mdev, "SWP not supported\n"); - return -EOPNOTSUPP; + return 0; } =20 if (!MLX5_CAP_ETH(mdev, swp_csum)) { mlx5_core_dbg(mdev, "SWP checksum not supported\n"); - return -EOPNOTSUPP; + return 0; } =20 if (!MLX5_CAP_ETH(mdev, swp_csum_l4_partial)) { mlx5_core_dbg(mdev, "SWP L4 partial checksum not supported\n"); - return -EOPNOTSUPP; + return 0; } =20 if (!MLX5_CAP_ETH(mdev, swp_lso)) { mlx5_core_dbg(mdev, "PSP LSO not supported\n"); - return -EOPNOTSUPP; + return 0; } =20 psp =3D kzalloc(sizeof(*psp), GFP_KERNEL); --=20 2.31.1