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Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , , , , Gal Pressman , Moshe Shemesh , Carolina Jubran Subject: [PATCH net-next 3/7] net/mlx5: Improve QoS error messages with actual depth values Date: Mon, 22 Sep 2025 12:01:07 +0300 Message-ID: <1758531671-819655-4-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1758531671-819655-1-git-send-email-tariqt@nvidia.com> References: <1758531671-819655-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF00000145:EE_|LV2PR12MB5917:EE_ X-MS-Office365-Filtering-Correlation-Id: e7691fb7-2b89-4d29-db86-08ddf9b6b3e8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|82310400026|376014|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?Zr0E50UtNCiwBNAKGup+td9aZ4IPshRYAmxEyGW+beMJvi/rRM7woL2j65V7?= =?us-ascii?Q?HD/PD6IBw9hVle+3g/XsMElqYl+9mYRQ6HBok2cfEvf/0H1JyR2atX4rnTLl?= =?us-ascii?Q?zS31IVtmkRX2A4a6rgsa7n9CehYPJF+SMx6Jm0vuYVzr6CA+JL7NpaZ7BWsJ?= =?us-ascii?Q?hWM7y6H8a/nOmpc5dgUFlZZEBph9ERok/6hdqFpJWCev7aAzLxHJ1hhfTKvT?= =?us-ascii?Q?+zcU6/2oxPIZUp9HrOql8+3uNF67flBehXt6M5r0GFWGHhyRFLFrXZg59/60?= =?us-ascii?Q?0mPp/iKl6pn6ebgHW/CA9MJko/jci8BsvaBszCz+y2NeshyRhROJjHyueI6L?= =?us-ascii?Q?/J7YewRpo2L8Aix0nUixLtL7uGDF/t9RrRkyJ6rAFV84/CDyx1QP1Srp5eI1?= =?us-ascii?Q?IZqjCP/df1Yv7GwMfe+JgItrBjL4wKXqGNW6Kfae744CxJeD+hFyhc/qLBnj?= =?us-ascii?Q?cCMzLdiwWOD7q9VGOcjQLLzDUm2LDb3DMv3RUA9P5DFISXKAdTtI3+1wWBIb?= =?us-ascii?Q?LdJcniidY5xFns0f1tnuj8iNF38kRcx66+yoZK7ICZ/NuPcPffezLEN6VL5B?= =?us-ascii?Q?TcR2Ovf3b0WbrWBQIR6qmdZpFPWvU4j+I/LtW4ILD5TWfDmMR1nrIovg7L4c?= =?us-ascii?Q?ltmLMvKpZX6bwXvAlbIancuNeaBnOkbk1HZ+vLhhLV9NK9C+EaBk9VXMvApc?= =?us-ascii?Q?/gbMfxonj1KhXqAXmZPyKj1rWfX3LQTPfX7TOM2ymhTQp9Yy9bWl5tu3gUlK?= =?us-ascii?Q?Ka5Xfh0C7IktnHbg+LWyTfW2jtV7K2z7tJUKewIor5YuUvKXHZ4AUdFv+6Zq?= =?us-ascii?Q?1RYd2ttiva1rnwm4ejJmSfJEgnMb6mzj1mpbu8yJK9gPvV+209gI50wjod27?= =?us-ascii?Q?nvk2L/ju9Frucc3zwbfASz4y9Q+xFtMFp62BAG0sgAU9XvHPsMPJHCy53l/w?= =?us-ascii?Q?gGfbfTgpzc6P2MqIvVaM2Vp+rBXC5b9bHMmmdtg9mnRO3UcUMqSrRaxOfvBM?= =?us-ascii?Q?vT1rJba/wrzLAjLcmnHYBhL2oplP0QP0hfoKU2s/S5asy9Q8iaCWKgNUiZ+2?= =?us-ascii?Q?3/BBHblCjj5tMgpnDz7/2YuukfX1yOBy/54E2kexgOIIlifE2u1jASgvpuTl?= =?us-ascii?Q?9OXVVSI3+E5jg+rw7N9/1QYehZqbmpU+0IjW8TU7XbtRgcXc7t1/nF6jSjwh?= =?us-ascii?Q?/Ff/SxKCGLXSqXbn3WlE0Xd98V5+JhWSNZjdL2DO+0AFJ+lxpS+NAQ5Y95si?= =?us-ascii?Q?WOp3+hrm0D9bzL3DLn43auWhD91t1f/IW9sFHii+a77cnHdBpFcNKrgQ8iDG?= =?us-ascii?Q?LBxGHDD8P5Dwg6ccK1T9FTOSV+YEc17h5NazCGWQ7V7ZsccYu0ef4CRQ01H5?= =?us-ascii?Q?HEpRdSCQdWaQg5hmq8FuRF46y6895sTJBp0rGE8rD6iyKJcKq6N1YLVjky3A?= =?us-ascii?Q?r0D9KKIKCg4LROx5PAqv/20eR8h3GGXVODCe1D6FPwoanIcJpXKQByuUOuxg?= =?us-ascii?Q?N+ZBlJ6Zaiyo7VFTQupNbjIz0k2TaPvj0m+A?= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(82310400026)(376014)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Sep 2025 09:02:05.2629 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e7691fb7-2b89-4d29-db86-08ddf9b6b3e8 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF00000145.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV2PR12MB5917 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Carolina Jubran Enhance error messages in MLX5 QoS scheduling depth validation by including the actual values that caused the validation to fail. Suggested-by: Paolo Abeni Signed-off-by: Carolina Jubran Reviewed-by: Cosmin Ratiu Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/esw/qos.c index 5f2d6c35f1ad..8574eb96f606 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c @@ -971,8 +971,9 @@ esw_qos_vport_tc_enable(struct mlx5_vport *vport, enum = sched_node_type type, max_level =3D 1 << MLX5_CAP_QOS(vport_node->esw->dev, log_esw_max_sched_depth); if (new_level > max_level) { - NL_SET_ERR_MSG_MOD(extack, - "TC arbitration on leafs is not supported beyond max scheduling de= pth"); + NL_SET_ERR_MSG_FMT_MOD(extack, + "TC arbitration on leafs is not supported beyond max schedulin= g depth %d", + max_level); return -EOPNOTSUPP; } } @@ -1444,8 +1445,9 @@ static int esw_qos_node_enable_tc_arbitration(struct = mlx5_esw_sched_node *node, new_level =3D node->level + 1; max_level =3D 1 << MLX5_CAP_QOS(node->esw->dev, log_esw_max_sched_depth); if (new_level > max_level) { - NL_SET_ERR_MSG_MOD(extack, - "TC arbitration on nodes is not supported beyond max scheduling dep= th"); + NL_SET_ERR_MSG_FMT_MOD(extack, + "TC arbitration on nodes is not supported beyond max scheduling= depth %d", + max_level); return -EOPNOTSUPP; } =20 @@ -1997,8 +1999,9 @@ mlx5_esw_qos_node_validate_set_parent(struct mlx5_esw= _sched_node *node, =20 max_level =3D 1 << MLX5_CAP_QOS(node->esw->dev, log_esw_max_sched_depth); if (new_level > max_level) { - NL_SET_ERR_MSG_MOD(extack, - "Node hierarchy depth exceeds the maximum supported level"); + NL_SET_ERR_MSG_FMT_MOD(extack, + "Node hierarchy depth %d exceeds the maximum supported level %d= ", + new_level, max_level); return -EOPNOTSUPP; } =20 --=20 2.31.1