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Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , , , , Gal Pressman , Moshe Shemesh , Vlad Dogaru , Yevgeny Kliteynik Subject: [PATCH net-next 1/7] net/mlx5: HWS, Generalize complex matchers Date: Mon, 22 Sep 2025 12:01:05 +0300 Message-ID: <1758531671-819655-2-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1758531671-819655-1-git-send-email-tariqt@nvidia.com> References: <1758531671-819655-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF00000145:EE_|DM4PR12MB7622:EE_ X-MS-Office365-Filtering-Correlation-Id: 3dfdc9de-d606-4ee6-0fd9-08ddf9b6b01e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|376014|36860700013|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?NpMZJnlhbiND3relKwG/4ia4dDez/l3WaFrHUXp6DN6EkUGdeqpAYKDbEaI2?= =?us-ascii?Q?ZiD+0xE59WWtAho50+2zyB1IZFljXyh+NinVbQli2ZiWPlTjt0IaKmEeypIG?= =?us-ascii?Q?+XXv1AaIg4Wv/BsZbONY2syCEPx4TudkzZqDDU2O3MtKRe3o0gYLBpgXDGho?= =?us-ascii?Q?cF6ZXEiPFvXXuai/TIng7Ai4t0IYAS+PPIP9xgmXcYlDmZSqBeCJMWdfEsFj?= =?us-ascii?Q?h0yn+Zt86RrHDHd9qp0afrS078tAQzUw1G/aYCLSDBNnDfRLZ+QVevBkniD/?= =?us-ascii?Q?ht5qXaKt/bk6zmsodyr2BEasqHQDEXkeDaHfw/z1S3yJ+O/mbrox5dRCLmy9?= =?us-ascii?Q?egthCa/cfkYk1ddm2A6Wd5KiCT+nPibZDR/NScWrbztX5TVP9uS4iZkNwvym?= =?us-ascii?Q?D8UDnZpbap3YFlkKxmCluuHG7uRNPjk2LclLsv4b+aY/6HbR3lx5uVpiAcpT?= =?us-ascii?Q?mOUnYzwwSiDJNYJeV/nn0ALwdYHhhN/WGdssI3tKpswqO08ZMoGrianiorik?= =?us-ascii?Q?2mMDWDlkBUv/sQApQGudBmoC3DDVTN9cC/AkVRPLo7xmONGLZIm5+RQWkYfK?= =?us-ascii?Q?9SWGh8YK6u/G84TGZ2WHoIs549nZ102/5LKmBln5LZRaS2QtY5J1YrAjryp+?= =?us-ascii?Q?CvWhxb8PefQV6tTu038Gma+QQ35Tn63WTQLp6BR0lcCC+nVdb7RLT2ty/R5m?= =?us-ascii?Q?430zxenRpEIt397DEig5sMrAnEsV8rn8mPqWeaUuKWNtlxQVkVhqVO3oscBs?= =?us-ascii?Q?pkgMRUJ0fz4raEVyTHqa9NQXdtkNXdfpexcDsxQwVmd0kLZuW1w3ALPbXTW0?= =?us-ascii?Q?2MkkPDV2glAvMcL5y98I6n/dl2T0U/b6PCyVHtrZnsNGyLAewSEfCn9iaGQ4?= =?us-ascii?Q?fiL3ri69bBhV2Y8dw5h6MO13Joa2IqAs5GgOW8F78cpF5GOjQCXlkjlng/i6?= =?us-ascii?Q?oPf1qpYu9KnNHencHRTvnQiuD6O+4B3oUfNfq/QwLSWHiiG7FT2Pk5tKmyTh?= =?us-ascii?Q?Pbfle32CIi5nNcvoXcb8UCqccf2mRnaO3TbcfkgflNzeozvZD4JOk89CG9tC?= =?us-ascii?Q?hhuuHEFtS1iaaY7aOIOzhm7OsdCsLAr7u7SdofMNSwiLpsGQJPDT5W75nJW5?= =?us-ascii?Q?JMYmRdWh5XotOOpo4uzQDdCAkJxG4XDuQ7lvzy0OKHRTgUXEbvIbUCIftPSb?= =?us-ascii?Q?cdgZxIwc5vrj/KaRQHCRFJmijj3tNHJbFzutHYr+Jm5Nf4ibHKcCWaxn726B?= =?us-ascii?Q?XaIc/NifXEOBerjb05DLTlqVh6iymI+pFtvD46gaE7Tq+APzH2NCwisn2mEe?= =?us-ascii?Q?YGDaewQBePEri1/0myqU5YPO7VnnN5D9cZle087B1iAsLVglHirgpZDkBa/d?= =?us-ascii?Q?DCwDB6+KL9FSy30ueGo+SPL5rbGmzx3BIcCIvc/R6sk82O2A2QVLF56C+tiZ?= =?us-ascii?Q?1lo5vb+T5X6UzpTSjwL1SXmyzNLIr2bAHVgOBuDYDygl8whBwjSlA3KKxYrO?= =?us-ascii?Q?wO2p3iJJQ2MViXmvNjgAtyPr0P+zoERUJpXt?= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(376014)(36860700013)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Sep 2025 09:01:58.9091 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3dfdc9de-d606-4ee6-0fd9-08ddf9b6b01e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF00000145.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB7622 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Vlad Dogaru The existing solution of complex matchers splits the match parameters across two, and exactly two, matchers. For some rather extreme cases (e.g. IPv6-in-IPv6 tunnels), even two matchers are not enough. Generalize complex matchers to up to 4 submatchers, and allow easy extension to more if needed. This resulted in rewriting a large part of the high-level complex matchers logic, but the original concepts were rock solid and still hold. Key characteristics of the new implementation: * Rework complex matchers to include multiple submatchers. All submatchers but the first are isolated, in keeping with the existing paradigm of handing off to specialized matchers that are not otherwise reachable by regular rules. * Similarly, rework complex rules to allow splitting them into more than two simple rules. Rules continue to be refcounted to allow for multiple complex rules matching on identical parts of the match params. * Rely on the match tag, as opposed to the entire match_param, to hash subrules. This results in lower memory usage. * Prefer to split the original user-supplied match parameters rather than the internal field descriptors. This avoids the awkward transition back and forth between the two formats. * Allow splitting multi-dword fields across matchers. The only restrictions that the new implementation impose are: a) any fragment of an IP address must be accompanied by a match on the IP version; and b) a single lower dword of an IPv6 address cannot be present in a submatcher as it would be interpreted as an IPv4 address. * Employ a greedy algorithm to split the match params, as opposed to complete search. The results are not optimal, but the algorithm is now linear compared to exponential. Consequently, we see complex matcher creation time drops two orders of magnitude in our tests. Signed-off-by: Vlad Dogaru Signed-off-by: Yevgeny Kliteynik Reviewed-by: Mark Bloch Signed-off-by: Tariq Toukan --- .../mellanox/mlx5/core/steering/hws/bwc.c | 37 +- .../mellanox/mlx5/core/steering/hws/bwc.h | 21 +- .../mlx5/core/steering/hws/bwc_complex.c | 1821 +++++++---------- .../mlx5/core/steering/hws/bwc_complex.h | 60 +- .../mellanox/mlx5/core/steering/hws/definer.c | 87 +- .../mellanox/mlx5/core/steering/hws/definer.h | 9 +- 6 files changed, 837 insertions(+), 1198 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.c b/d= rivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.c index adeccc588e5d..6ef0c4be27e1 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.c @@ -51,9 +51,6 @@ static void hws_bwc_matcher_init_attr(struct mlx5hws_bwc_= matcher *bwc_matcher, u8 size_log_rx, u8 size_log_tx, struct mlx5hws_matcher_attr *attr) { - struct mlx5hws_bwc_matcher *first_matcher =3D - bwc_matcher->complex_first_bwc_matcher; - memset(attr, 0, sizeof(*attr)); =20 attr->priority =3D priority; @@ -66,9 +63,6 @@ static void hws_bwc_matcher_init_attr(struct mlx5hws_bwc_= matcher *bwc_matcher, attr->size[MLX5HWS_MATCHER_SIZE_TYPE_TX].rule.num_log =3D size_log_tx; attr->resizable =3D true; attr->max_num_of_at_attach =3D MLX5HWS_BWC_MATCHER_ATTACH_AT_NUM; - - attr->isolated_matcher_end_ft_id =3D - first_matcher ? first_matcher->matcher->end_ft_id : 0; } =20 static int @@ -171,10 +165,16 @@ hws_bwc_matcher_move_all_simple(struct mlx5hws_bwc_ma= tcher *bwc_matcher) =20 static int hws_bwc_matcher_move_all(struct mlx5hws_bwc_matcher *bwc_matche= r) { - if (!bwc_matcher->complex) + switch (bwc_matcher->matcher_type) { + case MLX5HWS_BWC_MATCHER_SIMPLE: return hws_bwc_matcher_move_all_simple(bwc_matcher); - - return mlx5hws_bwc_matcher_move_all_complex(bwc_matcher); + case MLX5HWS_BWC_MATCHER_COMPLEX_FIRST: + return mlx5hws_bwc_matcher_complex_move_first(bwc_matcher); + case MLX5HWS_BWC_MATCHER_COMPLEX_SUBMATCHER: + return mlx5hws_bwc_matcher_complex_move(bwc_matcher); + default: + return -EINVAL; + } } =20 static int hws_bwc_matcher_move(struct mlx5hws_bwc_matcher *bwc_matcher) @@ -249,6 +249,7 @@ int mlx5hws_bwc_matcher_create_simple(struct mlx5hws_bw= c_matcher *bwc_matcher, bwc_matcher->tx_size.size_log, &attr); =20 + bwc_matcher->matcher_type =3D MLX5HWS_BWC_MATCHER_SIMPLE; bwc_matcher->priority =3D priority; =20 bwc_matcher->size_of_at_array =3D MLX5HWS_BWC_MATCHER_ATTACH_AT_NUM; @@ -393,7 +394,7 @@ int mlx5hws_bwc_matcher_destroy(struct mlx5hws_bwc_matc= her *bwc_matcher) "BWC matcher destroy: matcher still has %u RX and %u TX rules\n", rx_rules, tx_rules); =20 - if (bwc_matcher->complex) + if (bwc_matcher->matcher_type =3D=3D MLX5HWS_BWC_MATCHER_COMPLEX_FIRST) mlx5hws_bwc_matcher_destroy_complex(bwc_matcher); else mlx5hws_bwc_matcher_destroy_simple(bwc_matcher); @@ -651,7 +652,8 @@ int mlx5hws_bwc_rule_destroy_simple(struct mlx5hws_bwc_= rule *bwc_rule) =20 int mlx5hws_bwc_rule_destroy(struct mlx5hws_bwc_rule *bwc_rule) { - bool is_complex =3D !!bwc_rule->bwc_matcher->complex; + bool is_complex =3D bwc_rule->bwc_matcher->matcher_type =3D=3D + MLX5HWS_BWC_MATCHER_COMPLEX_FIRST; int ret =3D 0; =20 if (is_complex) @@ -1147,7 +1149,7 @@ mlx5hws_bwc_rule_create(struct mlx5hws_bwc_matcher *b= wc_matcher, =20 bwc_queue_idx =3D hws_bwc_gen_queue_idx(ctx); =20 - if (bwc_matcher->complex) + if (bwc_matcher->matcher_type =3D=3D MLX5HWS_BWC_MATCHER_COMPLEX_FIRST) ret =3D mlx5hws_bwc_rule_create_complex(bwc_rule, params, flow_source, @@ -1216,10 +1218,9 @@ int mlx5hws_bwc_rule_action_update(struct mlx5hws_bw= c_rule *bwc_rule, return -EINVAL; } =20 - /* For complex rule, the update should happen on the second matcher */ - if (bwc_rule->isolated_bwc_rule) - return hws_bwc_rule_action_update(bwc_rule->isolated_bwc_rule, - rule_actions); - else - return hws_bwc_rule_action_update(bwc_rule, rule_actions); + /* For complex rules, the update should happen on the last subrule. */ + while (bwc_rule->next_subrule) + bwc_rule =3D bwc_rule->next_subrule; + + return hws_bwc_rule_action_update(bwc_rule, rule_actions); } diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.h b/d= rivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.h index af391d70c14f..b905511f5c53 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.h @@ -18,6 +18,21 @@ =20 #define MLX5HWS_BWC_POLLING_TIMEOUT 60 =20 +enum mlx5hws_bwc_matcher_type { + /* Standalone bwc matcher. */ + MLX5HWS_BWC_MATCHER_SIMPLE, + /* The first matcher of a complex matcher. When rules are inserted into + * a matcher of this type, they are split into subrules and inserted + * into their corresponding submatchers. + */ + MLX5HWS_BWC_MATCHER_COMPLEX_FIRST, + /* A submatcher that is part of a complex matcher. For most purposes + * these are treated as simple matchers, except when it comes to moving + * rules during resize. + */ + MLX5HWS_BWC_MATCHER_COMPLEX_SUBMATCHER, +}; + struct mlx5hws_bwc_matcher_complex_data; =20 struct mlx5hws_bwc_matcher_size { @@ -31,9 +46,9 @@ struct mlx5hws_bwc_matcher { struct mlx5hws_match_template *mt; struct mlx5hws_action_template **at; struct mlx5hws_bwc_matcher_complex_data *complex; - struct mlx5hws_bwc_matcher *complex_first_bwc_matcher; u8 num_of_at; u8 size_of_at_array; + enum mlx5hws_bwc_matcher_type matcher_type; u32 priority; struct mlx5hws_bwc_matcher_size rx_size; struct mlx5hws_bwc_matcher_size tx_size; @@ -43,8 +58,8 @@ struct mlx5hws_bwc_matcher { struct mlx5hws_bwc_rule { struct mlx5hws_bwc_matcher *bwc_matcher; struct mlx5hws_rule *rule; - struct mlx5hws_bwc_rule *isolated_bwc_rule; - struct mlx5hws_bwc_complex_rule_hash_node *complex_hash_node; + struct mlx5hws_bwc_rule *next_subrule; + struct mlx5hws_bwc_complex_subrule_data *subrule_data; u32 flow_source; u16 bwc_queue_idx; bool skip_rx; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc_compl= ex.c b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc_complex.c index 14e79579c719..6115c0273fdb 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc_complex.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc_complex.c @@ -3,25 +3,27 @@ =20 #include "internal.h" =20 -#define HWS_CLEAR_MATCH_PARAM(mask, field) \ - MLX5_SET(fte_match_param, (mask)->match_buf, field, 0) - -#define HWS_SZ_MATCH_PARAM (MLX5_ST_SZ_DW_MATCH_PARAM * 4) - -static const struct rhashtable_params hws_refcount_hash =3D { - .key_len =3D sizeof_field(struct mlx5hws_bwc_complex_rule_hash_node, - match_buf), - .key_offset =3D offsetof(struct mlx5hws_bwc_complex_rule_hash_node, - match_buf), - .head_offset =3D offsetof(struct mlx5hws_bwc_complex_rule_hash_node, - hash_node), - .automatic_shrinking =3D true, - .min_size =3D 1, +/* We chain submatchers by applying three rules on a subrule: modify heade= r (to + * set register C6), jump to table (to the next submatcher) and the mandat= ory + * last rule. + */ +#define HWS_NUM_CHAIN_ACTIONS 3 + +static const struct rhashtable_params hws_rules_hash_params =3D { + .key_len =3D sizeof_field(struct mlx5hws_bwc_complex_subrule_data, + match_tag), + .key_offset =3D + offsetof(struct mlx5hws_bwc_complex_subrule_data, match_tag), + .head_offset =3D + offsetof(struct mlx5hws_bwc_complex_subrule_data, hash_node), + .automatic_shrinking =3D true, .min_size =3D 1, }; =20 -bool mlx5hws_bwc_match_params_is_complex(struct mlx5hws_context *ctx, - u8 match_criteria_enable, - struct mlx5hws_match_parameters *mask) +static bool +hws_match_params_exceeds_definer(struct mlx5hws_context *ctx, + u8 match_criteria_enable, + struct mlx5hws_match_parameters *mask, + bool allow_jumbo) { struct mlx5hws_definer match_layout =3D {0}; struct mlx5hws_match_template *mt; @@ -36,11 +38,11 @@ bool mlx5hws_bwc_match_params_is_complex(struct mlx5hws= _context *ctx, mask->match_sz, match_criteria_enable); if (!mt) { - mlx5hws_err(ctx, "BWC: failed creating match template\n"); + mlx5hws_err(ctx, "Complex matcher: failed creating match template\n"); return false; } =20 - ret =3D mlx5hws_definer_calc_layout(ctx, mt, &match_layout); + ret =3D mlx5hws_definer_calc_layout(ctx, mt, &match_layout, allow_jumbo); if (ret) { /* The only case that we're interested in is E2BIG, * which means that the match parameters need to be @@ -64,825 +66,481 @@ bool mlx5hws_bwc_match_params_is_complex(struct mlx5h= ws_context *ctx, return is_complex; } =20 -static void -hws_bwc_matcher_complex_params_clear_fld(struct mlx5hws_context *ctx, - enum mlx5hws_definer_fname fname, +bool mlx5hws_bwc_match_params_is_complex(struct mlx5hws_context *ctx, + u8 match_criteria_enable, struct mlx5hws_match_parameters *mask) { - struct mlx5hws_cmd_query_caps *caps =3D ctx->caps; - - switch (fname) { - case MLX5HWS_DEFINER_FNAME_ETH_TYPE_O: - case MLX5HWS_DEFINER_FNAME_ETH_TYPE_I: - case MLX5HWS_DEFINER_FNAME_ETH_L3_TYPE_O: - case MLX5HWS_DEFINER_FNAME_ETH_L3_TYPE_I: - case MLX5HWS_DEFINER_FNAME_IP_VERSION_O: - case MLX5HWS_DEFINER_FNAME_IP_VERSION_I: - /* Because of the strict requirements for IP address matching - * that require ethtype/ip_version matching as well, don't clear - * these fields - have them in both parts of the complex matcher - */ - break; - case MLX5HWS_DEFINER_FNAME_ETH_SMAC_47_16_O: - HWS_CLEAR_MATCH_PARAM(mask, outer_headers.smac_47_16); - break; - case MLX5HWS_DEFINER_FNAME_ETH_SMAC_47_16_I: - HWS_CLEAR_MATCH_PARAM(mask, inner_headers.smac_47_16); - break; - case MLX5HWS_DEFINER_FNAME_ETH_SMAC_15_0_O: - HWS_CLEAR_MATCH_PARAM(mask, outer_headers.smac_15_0); - break; - case MLX5HWS_DEFINER_FNAME_ETH_SMAC_15_0_I: - HWS_CLEAR_MATCH_PARAM(mask, inner_headers.smac_15_0); - break; - case MLX5HWS_DEFINER_FNAME_ETH_DMAC_47_16_O: - HWS_CLEAR_MATCH_PARAM(mask, outer_headers.dmac_47_16); - break; - case MLX5HWS_DEFINER_FNAME_ETH_DMAC_47_16_I: - HWS_CLEAR_MATCH_PARAM(mask, inner_headers.dmac_47_16); - break; - case MLX5HWS_DEFINER_FNAME_ETH_DMAC_15_0_O: - HWS_CLEAR_MATCH_PARAM(mask, outer_headers.dmac_15_0); - break; - case MLX5HWS_DEFINER_FNAME_ETH_DMAC_15_0_I: - HWS_CLEAR_MATCH_PARAM(mask, inner_headers.dmac_15_0); - break; - case MLX5HWS_DEFINER_FNAME_VLAN_TYPE_O: - HWS_CLEAR_MATCH_PARAM(mask, outer_headers.cvlan_tag); - HWS_CLEAR_MATCH_PARAM(mask, outer_headers.svlan_tag); - break; - case MLX5HWS_DEFINER_FNAME_VLAN_TYPE_I: - HWS_CLEAR_MATCH_PARAM(mask, inner_headers.cvlan_tag); - HWS_CLEAR_MATCH_PARAM(mask, inner_headers.svlan_tag); - break; - case MLX5HWS_DEFINER_FNAME_VLAN_FIRST_PRIO_O: - HWS_CLEAR_MATCH_PARAM(mask, outer_headers.first_prio); - break; - case MLX5HWS_DEFINER_FNAME_VLAN_FIRST_PRIO_I: - HWS_CLEAR_MATCH_PARAM(mask, inner_headers.first_prio); - break; - case MLX5HWS_DEFINER_FNAME_VLAN_CFI_O: - HWS_CLEAR_MATCH_PARAM(mask, outer_headers.first_cfi); - break; - case MLX5HWS_DEFINER_FNAME_VLAN_CFI_I: - HWS_CLEAR_MATCH_PARAM(mask, inner_headers.first_cfi); - break; - case MLX5HWS_DEFINER_FNAME_VLAN_ID_O: - HWS_CLEAR_MATCH_PARAM(mask, outer_headers.first_vid); - break; - case MLX5HWS_DEFINER_FNAME_VLAN_ID_I: - HWS_CLEAR_MATCH_PARAM(mask, inner_headers.first_vid); - break; - case MLX5HWS_DEFINER_FNAME_VLAN_SECOND_TYPE_O: - HWS_CLEAR_MATCH_PARAM(mask, - misc_parameters.outer_second_cvlan_tag); - HWS_CLEAR_MATCH_PARAM(mask, - misc_parameters.outer_second_svlan_tag); - break; - case MLX5HWS_DEFINER_FNAME_VLAN_SECOND_TYPE_I: - HWS_CLEAR_MATCH_PARAM(mask, - misc_parameters.inner_second_cvlan_tag); - HWS_CLEAR_MATCH_PARAM(mask, - misc_parameters.inner_second_svlan_tag); - break; - case MLX5HWS_DEFINER_FNAME_VLAN_SECOND_PRIO_O: - HWS_CLEAR_MATCH_PARAM(mask, misc_parameters.outer_second_prio); - break; - case MLX5HWS_DEFINER_FNAME_VLAN_SECOND_PRIO_I: - HWS_CLEAR_MATCH_PARAM(mask, misc_parameters.inner_second_prio); - break; - case MLX5HWS_DEFINER_FNAME_VLAN_SECOND_CFI_O: - HWS_CLEAR_MATCH_PARAM(mask, misc_parameters.outer_second_cfi); - break; - case MLX5HWS_DEFINER_FNAME_VLAN_SECOND_CFI_I: - HWS_CLEAR_MATCH_PARAM(mask, misc_parameters.inner_second_cfi); - break; - case MLX5HWS_DEFINER_FNAME_VLAN_SECOND_ID_O: - HWS_CLEAR_MATCH_PARAM(mask, misc_parameters.outer_second_vid); - break; - case MLX5HWS_DEFINER_FNAME_VLAN_SECOND_ID_I: - HWS_CLEAR_MATCH_PARAM(mask, misc_parameters.inner_second_vid); - break; - case MLX5HWS_DEFINER_FNAME_IPV4_IHL_O: - HWS_CLEAR_MATCH_PARAM(mask, outer_headers.ipv4_ihl); - break; - case MLX5HWS_DEFINER_FNAME_IPV4_IHL_I: - HWS_CLEAR_MATCH_PARAM(mask, inner_headers.ipv4_ihl); - break; - case MLX5HWS_DEFINER_FNAME_IP_DSCP_O: - HWS_CLEAR_MATCH_PARAM(mask, outer_headers.ip_dscp); - break; - case MLX5HWS_DEFINER_FNAME_IP_DSCP_I: - HWS_CLEAR_MATCH_PARAM(mask, inner_headers.ip_dscp); - break; - case MLX5HWS_DEFINER_FNAME_IP_ECN_O: - HWS_CLEAR_MATCH_PARAM(mask, outer_headers.ip_ecn); - break; - case MLX5HWS_DEFINER_FNAME_IP_ECN_I: - HWS_CLEAR_MATCH_PARAM(mask, inner_headers.ip_ecn); - break; - case MLX5HWS_DEFINER_FNAME_IP_TTL_O: - HWS_CLEAR_MATCH_PARAM(mask, outer_headers.ttl_hoplimit); - break; - case MLX5HWS_DEFINER_FNAME_IP_TTL_I: - HWS_CLEAR_MATCH_PARAM(mask, inner_headers.ttl_hoplimit); - break; - case MLX5HWS_DEFINER_FNAME_IPV4_DST_O: - HWS_CLEAR_MATCH_PARAM(mask, - outer_headers.dst_ipv4_dst_ipv6.ipv6_simple_layout.ipv6_31_0); - break; - case MLX5HWS_DEFINER_FNAME_IPV4_SRC_O: - HWS_CLEAR_MATCH_PARAM(mask, - outer_headers.src_ipv4_src_ipv6.ipv6_simple_layout.ipv6_31_0); - break; - case MLX5HWS_DEFINER_FNAME_IPV4_DST_I: - HWS_CLEAR_MATCH_PARAM(mask, - inner_headers.dst_ipv4_dst_ipv6.ipv6_simple_layout.ipv6_31_0); - break; - case MLX5HWS_DEFINER_FNAME_IPV4_SRC_I: - HWS_CLEAR_MATCH_PARAM(mask, - inner_headers.src_ipv4_src_ipv6.ipv6_simple_layout.ipv6_31_0); - break; - case MLX5HWS_DEFINER_FNAME_IP_FRAG_O: - HWS_CLEAR_MATCH_PARAM(mask, outer_headers.frag); - break; - case MLX5HWS_DEFINER_FNAME_IP_FRAG_I: - HWS_CLEAR_MATCH_PARAM(mask, inner_headers.frag); - break; - case MLX5HWS_DEFINER_FNAME_IPV6_FLOW_LABEL_O: - HWS_CLEAR_MATCH_PARAM(mask, - misc_parameters.outer_ipv6_flow_label); - break; - case MLX5HWS_DEFINER_FNAME_IPV6_FLOW_LABEL_I: - HWS_CLEAR_MATCH_PARAM(mask, - misc_parameters.inner_ipv6_flow_label); - break; - case MLX5HWS_DEFINER_FNAME_IPV6_DST_127_96_O: - case MLX5HWS_DEFINER_FNAME_IPV6_DST_95_64_O: - case MLX5HWS_DEFINER_FNAME_IPV6_DST_63_32_O: - case MLX5HWS_DEFINER_FNAME_IPV6_DST_31_0_O: - HWS_CLEAR_MATCH_PARAM(mask, - outer_headers.dst_ipv4_dst_ipv6.ipv6_simple_layout.ipv6_127_96); - HWS_CLEAR_MATCH_PARAM(mask, - outer_headers.dst_ipv4_dst_ipv6.ipv6_simple_layout.ipv6_95_64); - HWS_CLEAR_MATCH_PARAM(mask, - outer_headers.dst_ipv4_dst_ipv6.ipv6_simple_layout.ipv6_63_32); - HWS_CLEAR_MATCH_PARAM(mask, - outer_headers.dst_ipv4_dst_ipv6.ipv6_simple_layout.ipv6_31_0); - break; - case MLX5HWS_DEFINER_FNAME_IPV6_SRC_127_96_O: - case MLX5HWS_DEFINER_FNAME_IPV6_SRC_95_64_O: - case MLX5HWS_DEFINER_FNAME_IPV6_SRC_63_32_O: - case MLX5HWS_DEFINER_FNAME_IPV6_SRC_31_0_O: - HWS_CLEAR_MATCH_PARAM(mask, - outer_headers.src_ipv4_src_ipv6.ipv6_simple_layout.ipv6_127_96); - HWS_CLEAR_MATCH_PARAM(mask, - outer_headers.src_ipv4_src_ipv6.ipv6_simple_layout.ipv6_95_64); - HWS_CLEAR_MATCH_PARAM(mask, - outer_headers.src_ipv4_src_ipv6.ipv6_simple_layout.ipv6_63_32); - HWS_CLEAR_MATCH_PARAM(mask, - outer_headers.src_ipv4_src_ipv6.ipv6_simple_layout.ipv6_31_0); - break; - case MLX5HWS_DEFINER_FNAME_IPV6_DST_127_96_I: - case MLX5HWS_DEFINER_FNAME_IPV6_DST_95_64_I: - case MLX5HWS_DEFINER_FNAME_IPV6_DST_63_32_I: - case MLX5HWS_DEFINER_FNAME_IPV6_DST_31_0_I: - HWS_CLEAR_MATCH_PARAM(mask, - inner_headers.dst_ipv4_dst_ipv6.ipv6_simple_layout.ipv6_127_96); - HWS_CLEAR_MATCH_PARAM(mask, - inner_headers.dst_ipv4_dst_ipv6.ipv6_simple_layout.ipv6_95_64); - HWS_CLEAR_MATCH_PARAM(mask, - inner_headers.dst_ipv4_dst_ipv6.ipv6_simple_layout.ipv6_63_32); - HWS_CLEAR_MATCH_PARAM(mask, - inner_headers.dst_ipv4_dst_ipv6.ipv6_simple_layout.ipv6_31_0); - break; - case MLX5HWS_DEFINER_FNAME_IPV6_SRC_127_96_I: - case MLX5HWS_DEFINER_FNAME_IPV6_SRC_95_64_I: - case MLX5HWS_DEFINER_FNAME_IPV6_SRC_63_32_I: - case MLX5HWS_DEFINER_FNAME_IPV6_SRC_31_0_I: - HWS_CLEAR_MATCH_PARAM(mask, - inner_headers.src_ipv4_src_ipv6.ipv6_simple_layout.ipv6_127_96); - HWS_CLEAR_MATCH_PARAM(mask, - inner_headers.src_ipv4_src_ipv6.ipv6_simple_layout.ipv6_95_64); - HWS_CLEAR_MATCH_PARAM(mask, - inner_headers.src_ipv4_src_ipv6.ipv6_simple_layout.ipv6_63_32); - HWS_CLEAR_MATCH_PARAM(mask, - inner_headers.src_ipv4_src_ipv6.ipv6_simple_layout.ipv6_31_0); - break; - case MLX5HWS_DEFINER_FNAME_IP_PROTOCOL_O: - HWS_CLEAR_MATCH_PARAM(mask, outer_headers.ip_protocol); - break; - case MLX5HWS_DEFINER_FNAME_IP_PROTOCOL_I: - HWS_CLEAR_MATCH_PARAM(mask, inner_headers.ip_protocol); - break; - case MLX5HWS_DEFINER_FNAME_L4_SPORT_O: - HWS_CLEAR_MATCH_PARAM(mask, outer_headers.tcp_sport); - HWS_CLEAR_MATCH_PARAM(mask, outer_headers.udp_sport); - break; - case MLX5HWS_DEFINER_FNAME_L4_SPORT_I: - HWS_CLEAR_MATCH_PARAM(mask, inner_headers.tcp_dport); - HWS_CLEAR_MATCH_PARAM(mask, inner_headers.udp_dport); - break; - case MLX5HWS_DEFINER_FNAME_L4_DPORT_O: - HWS_CLEAR_MATCH_PARAM(mask, outer_headers.tcp_dport); - HWS_CLEAR_MATCH_PARAM(mask, outer_headers.udp_dport); - break; - case MLX5HWS_DEFINER_FNAME_L4_DPORT_I: - HWS_CLEAR_MATCH_PARAM(mask, inner_headers.tcp_dport); - HWS_CLEAR_MATCH_PARAM(mask, inner_headers.udp_dport); - break; - case MLX5HWS_DEFINER_FNAME_TCP_FLAGS_O: - HWS_CLEAR_MATCH_PARAM(mask, outer_headers.tcp_flags); - break; - case MLX5HWS_DEFINER_FNAME_TCP_ACK_NUM: - case MLX5HWS_DEFINER_FNAME_TCP_SEQ_NUM: - HWS_CLEAR_MATCH_PARAM(mask, - misc_parameters_3.outer_tcp_seq_num); - HWS_CLEAR_MATCH_PARAM(mask, - misc_parameters_3.outer_tcp_ack_num); - HWS_CLEAR_MATCH_PARAM(mask, - misc_parameters_3.inner_tcp_seq_num); - HWS_CLEAR_MATCH_PARAM(mask, - misc_parameters_3.inner_tcp_ack_num); - break; - case MLX5HWS_DEFINER_FNAME_GTP_TEID: - HWS_CLEAR_MATCH_PARAM(mask, misc_parameters_3.gtpu_teid); - break; - case MLX5HWS_DEFINER_FNAME_GTP_MSG_TYPE: - HWS_CLEAR_MATCH_PARAM(mask, misc_parameters_3.gtpu_msg_type); - HWS_CLEAR_MATCH_PARAM(mask, misc_parameters_3.gtpu_msg_flags); - break; - case MLX5HWS_DEFINER_FNAME_GTPU_FIRST_EXT_DW0: - HWS_CLEAR_MATCH_PARAM(mask, - misc_parameters_3.gtpu_first_ext_dw_0); - HWS_CLEAR_MATCH_PARAM(mask, misc_parameters_3.gtpu_dw_0); - break; - case MLX5HWS_DEFINER_FNAME_GTPU_DW2: - HWS_CLEAR_MATCH_PARAM(mask, misc_parameters_3.gtpu_dw_2); - break; - case MLX5HWS_DEFINER_FNAME_FLEX_PARSER_0: - case MLX5HWS_DEFINER_FNAME_FLEX_PARSER_1: - case MLX5HWS_DEFINER_FNAME_FLEX_PARSER_2: - case MLX5HWS_DEFINER_FNAME_FLEX_PARSER_3: - case MLX5HWS_DEFINER_FNAME_FLEX_PARSER_4: - case MLX5HWS_DEFINER_FNAME_FLEX_PARSER_5: - case MLX5HWS_DEFINER_FNAME_FLEX_PARSER_6: - case MLX5HWS_DEFINER_FNAME_FLEX_PARSER_7: - HWS_CLEAR_MATCH_PARAM(mask, - misc_parameters_2.outer_first_mpls_over_gre); - HWS_CLEAR_MATCH_PARAM(mask, - misc_parameters_2.outer_first_mpls_over_udp); - HWS_CLEAR_MATCH_PARAM(mask, - misc_parameters_3.geneve_tlv_option_0_data); - HWS_CLEAR_MATCH_PARAM(mask, - misc_parameters_4.prog_sample_field_id_0); - HWS_CLEAR_MATCH_PARAM(mask, - misc_parameters_4.prog_sample_field_value_0); - HWS_CLEAR_MATCH_PARAM(mask, - misc_parameters_4.prog_sample_field_value_1); - HWS_CLEAR_MATCH_PARAM(mask, - misc_parameters_4.prog_sample_field_id_2); - HWS_CLEAR_MATCH_PARAM(mask, - misc_parameters_4.prog_sample_field_value_2); - HWS_CLEAR_MATCH_PARAM(mask, - misc_parameters_4.prog_sample_field_id_3); - HWS_CLEAR_MATCH_PARAM(mask, - misc_parameters_4.prog_sample_field_value_3); - break; - case MLX5HWS_DEFINER_FNAME_VXLAN_VNI: - HWS_CLEAR_MATCH_PARAM(mask, misc_parameters.vxlan_vni); - break; - case MLX5HWS_DEFINER_FNAME_VXLAN_GPE_FLAGS: - HWS_CLEAR_MATCH_PARAM(mask, - misc_parameters_3.outer_vxlan_gpe_flags); - break; - case MLX5HWS_DEFINER_FNAME_VXLAN_GPE_RSVD0: - break; - case MLX5HWS_DEFINER_FNAME_VXLAN_GPE_PROTO: - HWS_CLEAR_MATCH_PARAM(mask, - misc_parameters_3.outer_vxlan_gpe_next_protocol); - break; - case MLX5HWS_DEFINER_FNAME_VXLAN_GPE_VNI: - HWS_CLEAR_MATCH_PARAM(mask, - misc_parameters_3.outer_vxlan_gpe_vni); - break; - case MLX5HWS_DEFINER_FNAME_GENEVE_OPT_LEN: - HWS_CLEAR_MATCH_PARAM(mask, misc_parameters.geneve_opt_len); - break; - case MLX5HWS_DEFINER_FNAME_GENEVE_OAM: - HWS_CLEAR_MATCH_PARAM(mask, misc_parameters.geneve_oam); - break; - case MLX5HWS_DEFINER_FNAME_GENEVE_PROTO: - HWS_CLEAR_MATCH_PARAM(mask, - misc_parameters.geneve_protocol_type); - break; - case MLX5HWS_DEFINER_FNAME_GENEVE_VNI: - HWS_CLEAR_MATCH_PARAM(mask, misc_parameters.geneve_vni); - break; - case MLX5HWS_DEFINER_FNAME_SOURCE_QP: - HWS_CLEAR_MATCH_PARAM(mask, misc_parameters.source_sqn); - break; - case MLX5HWS_DEFINER_FNAME_SOURCE_GVMI: - HWS_CLEAR_MATCH_PARAM(mask, misc_parameters.source_port); - HWS_CLEAR_MATCH_PARAM(mask, - misc_parameters.source_eswitch_owner_vhca_id); - break; - case MLX5HWS_DEFINER_FNAME_REG_0: - HWS_CLEAR_MATCH_PARAM(mask, misc_parameters_2.metadata_reg_c_0); - break; - case MLX5HWS_DEFINER_FNAME_REG_1: - HWS_CLEAR_MATCH_PARAM(mask, misc_parameters_2.metadata_reg_c_1); - break; - case MLX5HWS_DEFINER_FNAME_REG_2: - HWS_CLEAR_MATCH_PARAM(mask, misc_parameters_2.metadata_reg_c_2); - break; - case MLX5HWS_DEFINER_FNAME_REG_3: - HWS_CLEAR_MATCH_PARAM(mask, misc_parameters_2.metadata_reg_c_3); - break; - case MLX5HWS_DEFINER_FNAME_REG_4: - HWS_CLEAR_MATCH_PARAM(mask, misc_parameters_2.metadata_reg_c_4); - break; - case MLX5HWS_DEFINER_FNAME_REG_5: - HWS_CLEAR_MATCH_PARAM(mask, misc_parameters_2.metadata_reg_c_5); - break; - case MLX5HWS_DEFINER_FNAME_REG_7: - HWS_CLEAR_MATCH_PARAM(mask, misc_parameters_2.metadata_reg_c_7); - break; - case MLX5HWS_DEFINER_FNAME_REG_A: - HWS_CLEAR_MATCH_PARAM(mask, misc_parameters_2.metadata_reg_a); - break; - case MLX5HWS_DEFINER_FNAME_GRE_C: - HWS_CLEAR_MATCH_PARAM(mask, misc_parameters.gre_c_present); - break; - case MLX5HWS_DEFINER_FNAME_GRE_K: - HWS_CLEAR_MATCH_PARAM(mask, misc_parameters.gre_k_present); - break; - case MLX5HWS_DEFINER_FNAME_GRE_S: - HWS_CLEAR_MATCH_PARAM(mask, misc_parameters.gre_s_present); - break; - case MLX5HWS_DEFINER_FNAME_GRE_PROTOCOL: - HWS_CLEAR_MATCH_PARAM(mask, misc_parameters.gre_protocol); - break; - case MLX5HWS_DEFINER_FNAME_GRE_OPT_KEY: - HWS_CLEAR_MATCH_PARAM(mask, misc_parameters.gre_key.key); - break; - case MLX5HWS_DEFINER_FNAME_ICMP_DW1: - HWS_CLEAR_MATCH_PARAM(mask, misc_parameters_3.icmp_header_data); - HWS_CLEAR_MATCH_PARAM(mask, misc_parameters_3.icmp_type); - HWS_CLEAR_MATCH_PARAM(mask, misc_parameters_3.icmp_code); - HWS_CLEAR_MATCH_PARAM(mask, - misc_parameters_3.icmpv6_header_data); - HWS_CLEAR_MATCH_PARAM(mask, misc_parameters_3.icmpv6_type); - HWS_CLEAR_MATCH_PARAM(mask, misc_parameters_3.icmpv6_code); - break; - case MLX5HWS_DEFINER_FNAME_MPLS0_O: - HWS_CLEAR_MATCH_PARAM(mask, misc_parameters_2.outer_first_mpls); - break; - case MLX5HWS_DEFINER_FNAME_MPLS0_I: - HWS_CLEAR_MATCH_PARAM(mask, misc_parameters_2.inner_first_mpls); - break; - case MLX5HWS_DEFINER_FNAME_TNL_HDR_0: - HWS_CLEAR_MATCH_PARAM(mask, misc_parameters_5.tunnel_header_0); - break; - case MLX5HWS_DEFINER_FNAME_TNL_HDR_1: - HWS_CLEAR_MATCH_PARAM(mask, misc_parameters_5.tunnel_header_1); - break; - case MLX5HWS_DEFINER_FNAME_TNL_HDR_2: - HWS_CLEAR_MATCH_PARAM(mask, misc_parameters_5.tunnel_header_2); - break; - case MLX5HWS_DEFINER_FNAME_TNL_HDR_3: - HWS_CLEAR_MATCH_PARAM(mask, misc_parameters_5.tunnel_header_3); - break; - case MLX5HWS_DEFINER_FNAME_FLEX_PARSER0_OK: - case MLX5HWS_DEFINER_FNAME_FLEX_PARSER1_OK: - case MLX5HWS_DEFINER_FNAME_FLEX_PARSER2_OK: - case MLX5HWS_DEFINER_FNAME_FLEX_PARSER3_OK: - case MLX5HWS_DEFINER_FNAME_FLEX_PARSER4_OK: - case MLX5HWS_DEFINER_FNAME_FLEX_PARSER5_OK: - case MLX5HWS_DEFINER_FNAME_FLEX_PARSER6_OK: - case MLX5HWS_DEFINER_FNAME_FLEX_PARSER7_OK: - /* assuming this is flex parser for geneve option */ - if ((fname =3D=3D MLX5HWS_DEFINER_FNAME_FLEX_PARSER0_OK && - ctx->caps->flex_parser_id_geneve_tlv_option_0 !=3D 0) || - (fname =3D=3D MLX5HWS_DEFINER_FNAME_FLEX_PARSER1_OK && - ctx->caps->flex_parser_id_geneve_tlv_option_0 !=3D 1) || - (fname =3D=3D MLX5HWS_DEFINER_FNAME_FLEX_PARSER2_OK && - ctx->caps->flex_parser_id_geneve_tlv_option_0 !=3D 2) || - (fname =3D=3D MLX5HWS_DEFINER_FNAME_FLEX_PARSER3_OK && - ctx->caps->flex_parser_id_geneve_tlv_option_0 !=3D 3) || - (fname =3D=3D MLX5HWS_DEFINER_FNAME_FLEX_PARSER4_OK && - ctx->caps->flex_parser_id_geneve_tlv_option_0 !=3D 4) || - (fname =3D=3D MLX5HWS_DEFINER_FNAME_FLEX_PARSER5_OK && - ctx->caps->flex_parser_id_geneve_tlv_option_0 !=3D 5) || - (fname =3D=3D MLX5HWS_DEFINER_FNAME_FLEX_PARSER6_OK && - ctx->caps->flex_parser_id_geneve_tlv_option_0 !=3D 6) || - (fname =3D=3D MLX5HWS_DEFINER_FNAME_FLEX_PARSER7_OK && - ctx->caps->flex_parser_id_geneve_tlv_option_0 !=3D 7)) { - mlx5hws_err(ctx, - "Complex params: unsupported field %s (%d), flex parser ID for gen= eve is %d\n", - mlx5hws_definer_fname_to_str(fname), fname, - caps->flex_parser_id_geneve_tlv_option_0); - break; - } - HWS_CLEAR_MATCH_PARAM(mask, - misc_parameters.geneve_tlv_option_0_exist); - break; - case MLX5HWS_DEFINER_FNAME_REG_6: - default: - mlx5hws_err(ctx, "Complex params: unsupported field %s (%d)\n", - mlx5hws_definer_fname_to_str(fname), fname); - break; - } + return hws_match_params_exceeds_definer(ctx, match_criteria_enable, + mask, true); } =20 -static bool -hws_bwc_matcher_complex_params_comb_is_valid(struct mlx5hws_definer_fc *fc, - int fc_sz, - u32 combination_num) +static int +hws_get_last_set_dword_idx(const struct mlx5hws_match_parameters *mask) { - bool m1[MLX5HWS_DEFINER_FNAME_MAX] =3D {0}; - bool m2[MLX5HWS_DEFINER_FNAME_MAX] =3D {0}; - bool is_first_matcher; int i; =20 - for (i =3D 0; i < fc_sz; i++) { - is_first_matcher =3D !(combination_num & BIT(i)); - if (is_first_matcher) - m1[fc[i].fname] =3D true; - else - m2[fc[i].fname] =3D true; - } - - /* Not all the fields can be split into separate matchers. - * Some should be together on the same matcher. - * For example, IPv6 parts - the whole IPv6 address should be on the - * same matcher in order for us to deduce if it's IPv6 or IPv4 address. - */ - if (m1[MLX5HWS_DEFINER_FNAME_IP_FRAG_O] && - (m2[MLX5HWS_DEFINER_FNAME_ETH_SMAC_15_0_O] || - m2[MLX5HWS_DEFINER_FNAME_ETH_SMAC_47_16_O] || - m2[MLX5HWS_DEFINER_FNAME_ETH_DMAC_15_0_O] || - m2[MLX5HWS_DEFINER_FNAME_ETH_DMAC_47_16_O])) - return false; - - if (m2[MLX5HWS_DEFINER_FNAME_IP_FRAG_O] && - (m1[MLX5HWS_DEFINER_FNAME_ETH_SMAC_15_0_O] || - m1[MLX5HWS_DEFINER_FNAME_ETH_SMAC_47_16_O] || - m1[MLX5HWS_DEFINER_FNAME_ETH_DMAC_15_0_O] || - m1[MLX5HWS_DEFINER_FNAME_ETH_DMAC_47_16_O])) - return false; + for (i =3D mask->match_sz / 4 - 1; i >=3D 0; i--) + if (mask->match_buf[i]) + return i; =20 - if (m1[MLX5HWS_DEFINER_FNAME_IP_FRAG_I] && - (m2[MLX5HWS_DEFINER_FNAME_ETH_SMAC_47_16_I] || - m2[MLX5HWS_DEFINER_FNAME_ETH_SMAC_15_0_I] || - m2[MLX5HWS_DEFINER_FNAME_ETH_DMAC_47_16_I] || - m2[MLX5HWS_DEFINER_FNAME_ETH_DMAC_15_0_I])) - return false; + return -1; +} =20 - if (m2[MLX5HWS_DEFINER_FNAME_IP_FRAG_I] && - (m1[MLX5HWS_DEFINER_FNAME_ETH_SMAC_47_16_I] || - m1[MLX5HWS_DEFINER_FNAME_ETH_SMAC_15_0_I] || - m1[MLX5HWS_DEFINER_FNAME_ETH_DMAC_47_16_I] || - m1[MLX5HWS_DEFINER_FNAME_ETH_DMAC_15_0_I])) - return false; +static bool hws_match_mask_is_empty(const struct mlx5hws_match_parameters = *mask) +{ + return hws_get_last_set_dword_idx(mask) =3D=3D -1; +} =20 - /* Don't split outer IPv6 dest address. */ - if ((m1[MLX5HWS_DEFINER_FNAME_IPV6_DST_127_96_O] || - m1[MLX5HWS_DEFINER_FNAME_IPV6_DST_95_64_O] || - m1[MLX5HWS_DEFINER_FNAME_IPV6_DST_63_32_O] || - m1[MLX5HWS_DEFINER_FNAME_IPV6_DST_31_0_O]) && - (m2[MLX5HWS_DEFINER_FNAME_IPV6_DST_127_96_O] || - m2[MLX5HWS_DEFINER_FNAME_IPV6_DST_95_64_O] || - m2[MLX5HWS_DEFINER_FNAME_IPV6_DST_63_32_O] || - m2[MLX5HWS_DEFINER_FNAME_IPV6_DST_31_0_O])) - return false; +static bool hws_dword_is_inner_ipaddr_off(int dword_off) +{ + /* IPv4 and IPv6 addresses share the same entry via a union, and the + * source and dest addresses are contiguous in the fte_match_param. So + * we need to check 8 words. + */ + static const int inner_ip_dword_off =3D + __mlx5_dw_off(fte_match_param, inner_headers.src_ipv4_src_ipv6); =20 - /* Don't split outer IPv6 source address. */ - if ((m1[MLX5HWS_DEFINER_FNAME_IPV6_SRC_127_96_O] || - m1[MLX5HWS_DEFINER_FNAME_IPV6_SRC_95_64_O] || - m1[MLX5HWS_DEFINER_FNAME_IPV6_SRC_63_32_O] || - m1[MLX5HWS_DEFINER_FNAME_IPV6_SRC_31_0_O]) && - (m2[MLX5HWS_DEFINER_FNAME_IPV6_SRC_127_96_O] || - m2[MLX5HWS_DEFINER_FNAME_IPV6_SRC_95_64_O] || - m2[MLX5HWS_DEFINER_FNAME_IPV6_SRC_63_32_O] || - m2[MLX5HWS_DEFINER_FNAME_IPV6_SRC_31_0_O])) - return false; + return dword_off >=3D inner_ip_dword_off && + dword_off < inner_ip_dword_off + 8; +} =20 - /* Don't split inner IPv6 dest address. */ - if ((m1[MLX5HWS_DEFINER_FNAME_IPV6_DST_127_96_I] || - m1[MLX5HWS_DEFINER_FNAME_IPV6_DST_95_64_I] || - m1[MLX5HWS_DEFINER_FNAME_IPV6_DST_63_32_I] || - m1[MLX5HWS_DEFINER_FNAME_IPV6_DST_31_0_I]) && - (m2[MLX5HWS_DEFINER_FNAME_IPV6_DST_127_96_I] || - m2[MLX5HWS_DEFINER_FNAME_IPV6_DST_95_64_I] || - m2[MLX5HWS_DEFINER_FNAME_IPV6_DST_63_32_I] || - m2[MLX5HWS_DEFINER_FNAME_IPV6_DST_31_0_I])) - return false; +static bool hws_dword_is_outer_ipaddr_off(int dword_off) +{ + static const int outer_ip_dword_off =3D + __mlx5_dw_off(fte_match_param, outer_headers.src_ipv4_src_ipv6); =20 - /* Don't split inner IPv6 source address. */ - if ((m1[MLX5HWS_DEFINER_FNAME_IPV6_SRC_127_96_I] || - m1[MLX5HWS_DEFINER_FNAME_IPV6_SRC_95_64_I] || - m1[MLX5HWS_DEFINER_FNAME_IPV6_SRC_63_32_I] || - m1[MLX5HWS_DEFINER_FNAME_IPV6_SRC_31_0_I]) && - (m2[MLX5HWS_DEFINER_FNAME_IPV6_SRC_127_96_I] || - m2[MLX5HWS_DEFINER_FNAME_IPV6_SRC_95_64_I] || - m2[MLX5HWS_DEFINER_FNAME_IPV6_SRC_63_32_I] || - m2[MLX5HWS_DEFINER_FNAME_IPV6_SRC_31_0_I])) - return false; + return dword_off >=3D outer_ip_dword_off && + dword_off < outer_ip_dword_off + 8; +} =20 - /* Don't split GRE parameters. */ - if ((m1[MLX5HWS_DEFINER_FNAME_GRE_C] || - m1[MLX5HWS_DEFINER_FNAME_GRE_K] || - m1[MLX5HWS_DEFINER_FNAME_GRE_S] || - m1[MLX5HWS_DEFINER_FNAME_GRE_PROTOCOL]) && - (m2[MLX5HWS_DEFINER_FNAME_GRE_C] || - m2[MLX5HWS_DEFINER_FNAME_GRE_K] || - m2[MLX5HWS_DEFINER_FNAME_GRE_S] || - m2[MLX5HWS_DEFINER_FNAME_GRE_PROTOCOL])) - return false; +static void hws_add_dword_to_mask(struct mlx5hws_match_parameters *mask, + const struct mlx5hws_match_parameters *orig, + int dword_idx, bool *added_inner_ipv, + bool *added_outer_ipv) +{ + mask->match_buf[dword_idx] |=3D orig->match_buf[dword_idx]; =20 - /* Don't split TCP ack/seq numbers. */ - if ((m1[MLX5HWS_DEFINER_FNAME_TCP_ACK_NUM] || - m1[MLX5HWS_DEFINER_FNAME_TCP_SEQ_NUM]) && - (m2[MLX5HWS_DEFINER_FNAME_TCP_ACK_NUM] || - m2[MLX5HWS_DEFINER_FNAME_TCP_SEQ_NUM])) - return false; + *added_inner_ipv =3D false; + *added_outer_ipv =3D false; =20 - /* Don't split flex parser. */ - if ((m1[MLX5HWS_DEFINER_FNAME_FLEX_PARSER_0] || - m1[MLX5HWS_DEFINER_FNAME_FLEX_PARSER_1] || - m1[MLX5HWS_DEFINER_FNAME_FLEX_PARSER_2] || - m1[MLX5HWS_DEFINER_FNAME_FLEX_PARSER_3] || - m1[MLX5HWS_DEFINER_FNAME_FLEX_PARSER_4] || - m1[MLX5HWS_DEFINER_FNAME_FLEX_PARSER_5] || - m1[MLX5HWS_DEFINER_FNAME_FLEX_PARSER_6] || - m1[MLX5HWS_DEFINER_FNAME_FLEX_PARSER_7]) && - (m2[MLX5HWS_DEFINER_FNAME_FLEX_PARSER_0] || - m2[MLX5HWS_DEFINER_FNAME_FLEX_PARSER_1] || - m2[MLX5HWS_DEFINER_FNAME_FLEX_PARSER_2] || - m2[MLX5HWS_DEFINER_FNAME_FLEX_PARSER_3] || - m2[MLX5HWS_DEFINER_FNAME_FLEX_PARSER_4] || - m2[MLX5HWS_DEFINER_FNAME_FLEX_PARSER_5] || - m2[MLX5HWS_DEFINER_FNAME_FLEX_PARSER_6] || - m2[MLX5HWS_DEFINER_FNAME_FLEX_PARSER_7])) - return false; + /* Any IP address fragment must be accompanied by a match on IP version. + * Use the `added_ipv` variables to keep track if we added IP versions + * specifically for this dword, so that we can roll them back if the + * match params become too large to fit into a definer. + */ + if (hws_dword_is_inner_ipaddr_off(dword_idx) && + !MLX5_GET(fte_match_param, mask->match_buf, + inner_headers.ip_version)) { + MLX5_SET(fte_match_param, mask->match_buf, + inner_headers.ip_version, 0xf); + *added_inner_ipv =3D true; + } + if (hws_dword_is_outer_ipaddr_off(dword_idx) && + !MLX5_GET(fte_match_param, mask->match_buf, + outer_headers.ip_version)) { + MLX5_SET(fte_match_param, mask->match_buf, + outer_headers.ip_version, 0xf); + *added_outer_ipv =3D true; + } +} =20 - return true; +static void hws_remove_dword_from_mask(struct mlx5hws_match_parameters *ma= sk, + int dword_idx, bool added_inner_ipv, + bool added_outer_ipv) +{ + mask->match_buf[dword_idx] =3D 0; + if (added_inner_ipv) + MLX5_SET(fte_match_param, mask->match_buf, + inner_headers.ip_version, 0); + if (added_outer_ipv) + MLX5_SET(fte_match_param, mask->match_buf, + outer_headers.ip_version, 0); } =20 -static void -hws_bwc_matcher_complex_params_comb_create(struct mlx5hws_context *ctx, - struct mlx5hws_match_parameters *m, - struct mlx5hws_match_parameters *m1, - struct mlx5hws_match_parameters *m2, - struct mlx5hws_definer_fc *fc, - int fc_sz, - u32 combination_num) +/* Avoid leaving a single lower dword in `mask` if there are others presen= t in + * `orig`. Splitting IPv6 addresses like this causes them to be interprete= d as + * IPv4. + */ +static void hws_avoid_ipv6_split_of(struct mlx5hws_match_parameters *orig, + struct mlx5hws_match_parameters *mask, + int off) { - bool is_first_matcher; - int i; + /* Masks are allocated to a full fte_match_param, but it can't hurt to + * double check. + */ + if (orig->match_sz <=3D off + 3 || mask->match_sz <=3D off + 3) + return; =20 - memcpy(m1->match_buf, m->match_buf, m->match_sz); - memcpy(m2->match_buf, m->match_buf, m->match_sz); + /* Lower dword is not set, nothing to do. */ + if (!mask->match_buf[off + 3]) + return; =20 - for (i =3D 0; i < fc_sz; i++) { - is_first_matcher =3D !(combination_num & BIT(i)); - hws_bwc_matcher_complex_params_clear_fld(ctx, - fc[i].fname, - is_first_matcher ? - m2 : m1); - } + /* Higher dwords also present in `mask`, no ambiguity. */ + if (mask->match_buf[off] || mask->match_buf[off + 1] || + mask->match_buf[off + 2]) + return; + + /* There are no higher dwords in `orig`, i.e. we match on IPv4. */ + if (!orig->match_buf[off] && !orig->match_buf[off + 1] && + !orig->match_buf[off + 2]) + return; =20 - MLX5_SET(fte_match_param, m2->match_buf, - misc_parameters_2.metadata_reg_c_6, -1); + /* Put the lower dword back in `orig`. It is always safe to do this, the + * dword will just be picked up in the next submask. + */ + orig->match_buf[off + 3] =3D mask->match_buf[off + 3]; + mask->match_buf[off + 3] =3D 0; } =20 -static void -hws_bwc_matcher_complex_params_destroy(struct mlx5hws_match_parameters *ma= sk_1, - struct mlx5hws_match_parameters *mask_2) +static void hws_avoid_ipv6_split(struct mlx5hws_match_parameters *orig, + struct mlx5hws_match_parameters *mask) { - kfree(mask_1->match_buf); - kfree(mask_2->match_buf); + hws_avoid_ipv6_split_of(orig, mask, + __mlx5_dw_off(fte_match_param, + outer_headers.src_ipv4_src_ipv6)); + hws_avoid_ipv6_split_of(orig, mask, + __mlx5_dw_off(fte_match_param, + outer_headers.dst_ipv4_dst_ipv6)); + hws_avoid_ipv6_split_of(orig, mask, + __mlx5_dw_off(fte_match_param, + inner_headers.src_ipv4_src_ipv6)); + hws_avoid_ipv6_split_of(orig, mask, + __mlx5_dw_off(fte_match_param, + inner_headers.dst_ipv4_dst_ipv6)); } =20 -static int -hws_bwc_matcher_complex_params_create(struct mlx5hws_context *ctx, - u8 match_criteria, - struct mlx5hws_match_parameters *mask, - struct mlx5hws_match_parameters *mask_1, - struct mlx5hws_match_parameters *mask_2) +/* Build a subset of the `orig` match parameters into `mask`. This subset = is + * guaranteed to fit in a single definer an as such is a candidate for bei= ng a + * part of a complex matcher. Upon successful execution, the match params = that + * go into `mask` are cleared from `orig`. + */ +static int hws_get_simple_params(struct mlx5hws_context *ctx, u8 match_cri= teria, + struct mlx5hws_match_parameters *orig, + struct mlx5hws_match_parameters *mask) { - struct mlx5hws_definer_fc *fc; - u32 num_of_combinations; - int fc_sz =3D 0; - int res =3D 0; - u32 i; - - if (MLX5_GET(fte_match_param, mask->match_buf, - misc_parameters_2.metadata_reg_c_6)) { - mlx5hws_err(ctx, "Complex matcher: REG_C_6 matching is reserved\n"); - res =3D -EINVAL; - goto out; - } + bool added_inner_ipv, added_outer_ipv; + int dword_idx; + u32 *backup; + int ret; =20 - mask_1->match_buf =3D kzalloc(MLX5_ST_SZ_BYTES(fte_match_param), - GFP_KERNEL); - mask_2->match_buf =3D kzalloc(MLX5_ST_SZ_BYTES(fte_match_param), - GFP_KERNEL); - if (!mask_1->match_buf || !mask_2->match_buf) { - mlx5hws_err(ctx, "Complex matcher: failed to allocate match_param\n"); - res =3D -ENOMEM; - goto free_params; - } + dword_idx =3D hws_get_last_set_dword_idx(orig); + /* Nothing to do, we consumed all of the match params before. */ + if (dword_idx =3D=3D -1) + return 0; =20 - mask_1->match_sz =3D mask->match_sz; - mask_2->match_sz =3D mask->match_sz; + backup =3D kzalloc(MLX5_ST_SZ_BYTES(fte_match_param), GFP_KERNEL); + if (!backup) + return -ENOMEM; =20 - fc =3D mlx5hws_definer_conv_match_params_to_compressed_fc(ctx, - match_criteria, - mask->match_buf, - &fc_sz); - if (!fc) { - res =3D -ENOMEM; - goto free_params; - } + while (1) { + dword_idx =3D hws_get_last_set_dword_idx(orig); + /* Nothing to do, we consumed all of the original match params + * into this subset, which still fits into a single matcher. + */ + if (dword_idx =3D=3D -1) { + ret =3D 0; + goto free_backup; + } =20 - if (fc_sz >=3D sizeof(num_of_combinations) * BITS_PER_BYTE) { - mlx5hws_err(ctx, - "Complex matcher: too many match parameters (%d)\n", - fc_sz); - res =3D -EINVAL; - goto free_fc; + memcpy(backup, mask->match_buf, mask->match_sz); + + /* Try to add this dword to the current subset. */ + hws_add_dword_to_mask(mask, orig, dword_idx, &added_inner_ipv, + &added_outer_ipv); + + if (hws_match_params_exceeds_definer(ctx, match_criteria, mask, + false)) { + /* We just added a match param that makes the definer + * too large. Revert and return what we had before. + * Note that we can't just zero out the affected fields, + * because it's possible that the dword we're looking at + * wasn't zero before (e.g. it included auto-added + * matches in IP version. This is why we employ the + * rather cumbersome memcpy for backing up. + */ + memcpy(mask->match_buf, backup, mask->match_sz); + /* Possible future improvement: We can't add any more + * dwords, but it may be possible to squeeze in + * individual bytes, as definers have special slots for + * those. + * + * For now, keep the code simple. This results in an + * extra submatcher in some cases, but it's good enough. + */ + ret =3D 0; + break; + } + + /* The current subset of match params still fits in a single + * definer. Remove the dword from the original mask. + * + * Also remove any explicit match on IP version if we just + * included one here. We will still automatically add it to + * accompany any IP address fragment, but do not need to + * consider it by itself. + */ + hws_remove_dword_from_mask(orig, dword_idx, added_inner_ipv, + added_outer_ipv); } =20 - /* We have list of all the match fields from the match parameter. - * Now try all the possibilities of splitting them into two match - * buffers and look for the supported combination. + /* Make sure we have not picked up a single lower dword of an IPv6 + * address, as the firmware will erroneously treat it as an IPv4 + * address. */ - num_of_combinations =3D 1 << fc_sz; + hws_avoid_ipv6_split(orig, mask); =20 - /* Start from combination at index 1 - we know that 0 is unsupported */ - for (i =3D 1; i < num_of_combinations; i++) { - if (!hws_bwc_matcher_complex_params_comb_is_valid(fc, fc_sz, i)) - continue; +free_backup: + kfree(backup); =20 - hws_bwc_matcher_complex_params_comb_create(ctx, - mask, mask_1, mask_2, - fc, fc_sz, i); - /* We now have two separate sets of match params. - * Check if each of them can be used in its own matcher. + return ret; +} + +static int +hws_bwc_matcher_split_mask(struct mlx5hws_context *ctx, u8 match_criteria, + const struct mlx5hws_match_parameters *mask, + struct mlx5hws_match_parameters *submasks, + int *num_submasks) +{ + struct mlx5hws_match_parameters mask_copy; + int ret, i =3D 0; + + mask_copy.match_sz =3D MLX5_ST_SZ_BYTES(fte_match_param); + mask_copy.match_buf =3D kzalloc(mask_copy.match_sz, GFP_KERNEL); + if (!mask_copy.match_buf) + return -ENOMEM; + + memcpy(mask_copy.match_buf, mask->match_buf, mask->match_sz); + + while (!hws_match_mask_is_empty(&mask_copy)) { + if (i >=3D MLX5HWS_BWC_COMPLEX_MAX_SUBMATCHERS) { + mlx5hws_err(ctx, + "Complex matcher: mask too large for %d matchers\n", + MLX5HWS_BWC_COMPLEX_MAX_SUBMATCHERS); + ret =3D -E2BIG; + goto free_copy; + } + /* All but the first matcher need to match on register C6 to + * connect pieces of the complex rule together. */ - if (!mlx5hws_bwc_match_params_is_complex(ctx, - match_criteria, - mask_1) && - !mlx5hws_bwc_match_params_is_complex(ctx, - match_criteria, - mask_2)) - break; + if (i > 0) { + MLX5_SET(fte_match_param, submasks[i].match_buf, + misc_parameters_2.metadata_reg_c_6, -1); + match_criteria |=3D MLX5HWS_DEFINER_MATCH_CRITERIA_MISC2; + } + ret =3D hws_get_simple_params(ctx, match_criteria, &mask_copy, + &submasks[i]); + if (ret < 0) + goto free_copy; + i++; } =20 - if (i =3D=3D num_of_combinations) { - /* We've scanned all the combinations, but to no avail */ - mlx5hws_err(ctx, "Complex matcher: couldn't find match params combinatio= n\n"); - res =3D -EINVAL; - goto free_fc; - } + *num_submasks =3D i; + ret =3D 0; =20 - kfree(fc); - return 0; +free_copy: + kfree(mask_copy.match_buf); =20 -free_fc: - kfree(fc); -free_params: - hws_bwc_matcher_complex_params_destroy(mask_1, mask_2); -out: - return res; + return ret; } =20 -static int -hws_bwc_isolated_table_create(struct mlx5hws_bwc_matcher *bwc_matcher, - struct mlx5hws_table *table) +static struct mlx5hws_table * +hws_isolated_table_create(const struct mlx5hws_bwc_matcher *cmatcher) { + struct mlx5hws_bwc_complex_submatcher *first_subm; struct mlx5hws_cmd_ft_modify_attr ft_attr =3D {0}; - struct mlx5hws_context *ctx =3D table->ctx; struct mlx5hws_table_attr tbl_attr =3D {0}; - struct mlx5hws_table *isolated_tbl; - int ret =3D 0; + struct mlx5hws_table *orig_tbl; + struct mlx5hws_context *ctx; + struct mlx5hws_table *tbl; + int ret; =20 - tbl_attr.type =3D table->type; - tbl_attr.level =3D table->level; + first_subm =3D &cmatcher->complex->submatchers[0]; + orig_tbl =3D first_subm->tbl; + ctx =3D orig_tbl->ctx; =20 - bwc_matcher->complex->isolated_tbl =3D - mlx5hws_table_create(ctx, &tbl_attr); - isolated_tbl =3D bwc_matcher->complex->isolated_tbl; - if (!isolated_tbl) - return -EINVAL; + tbl_attr.type =3D orig_tbl->type; + tbl_attr.level =3D orig_tbl->level; + tbl =3D mlx5hws_table_create(ctx, &tbl_attr); + if (!tbl) + return ERR_PTR(-EINVAL); =20 - /* Set the default miss of the isolated table to - * point to the end anchor of the original matcher. + /* Set the default miss of the isolated table to point + * to the end anchor of the original matcher. */ - mlx5hws_cmd_set_attr_connect_miss_tbl(ctx, - isolated_tbl->fw_ft_type, - isolated_tbl->type, - &ft_attr); - ft_attr.table_miss_id =3D bwc_matcher->matcher->end_ft_id; - - ret =3D mlx5hws_cmd_flow_table_modify(ctx->mdev, - &ft_attr, - isolated_tbl->ft_id); + mlx5hws_cmd_set_attr_connect_miss_tbl(ctx, tbl->fw_ft_type, + tbl->type, &ft_attr); + ft_attr.table_miss_id =3D first_subm->bwc_matcher->matcher->end_ft_id; + + ret =3D mlx5hws_cmd_flow_table_modify(ctx->mdev, &ft_attr, tbl->ft_id); if (ret) { - mlx5hws_err(ctx, "Failed setting isolated tbl default miss\n"); + mlx5hws_err(ctx, "Complex matcher: failed to set isolated tbl default mi= ss\n"); goto destroy_tbl; } =20 - return 0; + return tbl; =20 destroy_tbl: - mlx5hws_table_destroy(isolated_tbl); - return ret; + mlx5hws_table_destroy(tbl); + + return ERR_PTR(ret); } =20 -static void hws_bwc_isolated_table_destroy(struct mlx5hws_table *isolated_= tbl) +static int hws_submatcher_init_first(struct mlx5hws_bwc_matcher *cmatcher, + struct mlx5hws_table *table, u32 priority, + u8 match_criteria, + struct mlx5hws_match_parameters *mask) { - /* This table is isolated - no table is pointing to it, no need to - * disconnect it from anywhere, it won't affect any other table's miss. + enum mlx5hws_action_type action_types[HWS_NUM_CHAIN_ACTIONS]; + struct mlx5hws_bwc_complex_submatcher *subm; + int ret; + + subm =3D &cmatcher->complex->submatchers[0]; + + /* The first submatcher lives in the original table and does not have an + * associated jump to table action. It also points to the outer complex + * matcher. */ - mlx5hws_table_destroy(isolated_tbl); + subm->tbl =3D table; + subm->action_tbl =3D NULL; + subm->bwc_matcher =3D cmatcher; + + action_types[0] =3D MLX5HWS_ACTION_TYP_MODIFY_HDR; + action_types[1] =3D MLX5HWS_ACTION_TYP_TBL; + action_types[2] =3D MLX5HWS_ACTION_TYP_LAST; + + ret =3D mlx5hws_bwc_matcher_create_simple(subm->bwc_matcher, subm->tbl, + priority, match_criteria, mask, + action_types); + if (ret) + return ret; + + subm->bwc_matcher->matcher_type =3D MLX5HWS_BWC_MATCHER_COMPLEX_FIRST; + + ret =3D rhashtable_init(&subm->rules_hash, &hws_rules_hash_params); + if (ret) + goto destroy_matcher; + mutex_init(&subm->hash_lock); + ida_init(&subm->chain_ida); + + return 0; + +destroy_matcher: + mlx5hws_bwc_matcher_destroy_simple(subm->bwc_matcher); + + return ret; } =20 -static int -hws_bwc_isolated_matcher_create(struct mlx5hws_bwc_matcher *bwc_matcher, - struct mlx5hws_table *table, - u8 match_criteria_enable, - struct mlx5hws_match_parameters *mask) +static int hws_submatcher_init(struct mlx5hws_bwc_matcher *cmatcher, int i= dx, + struct mlx5hws_table *table, u32 priority, + u8 match_criteria, + struct mlx5hws_match_parameters *mask) { - struct mlx5hws_table *isolated_tbl =3D bwc_matcher->complex->isolated_tbl; - struct mlx5hws_bwc_matcher *isolated_bwc_matcher; - struct mlx5hws_context *ctx =3D table->ctx; + enum mlx5hws_action_type action_types[HWS_NUM_CHAIN_ACTIONS]; + struct mlx5hws_bwc_complex_submatcher *subm; + bool is_last; int ret; =20 - isolated_bwc_matcher =3D kzalloc(sizeof(*bwc_matcher), GFP_KERNEL); - if (!isolated_bwc_matcher) - return -ENOMEM; + if (!idx) + return hws_submatcher_init_first(cmatcher, table, priority, + match_criteria, mask); =20 - bwc_matcher->complex->isolated_bwc_matcher =3D isolated_bwc_matcher; + subm =3D &cmatcher->complex->submatchers[idx]; + is_last =3D idx =3D=3D cmatcher->complex->num_submatchers - 1; =20 - /* Isolated BWC matcher needs access to the first BWC matcher */ - isolated_bwc_matcher->complex_first_bwc_matcher =3D bwc_matcher; + subm->tbl =3D hws_isolated_table_create(cmatcher); + if (IS_ERR(subm->tbl)) + return PTR_ERR(subm->tbl); =20 - /* Isolated matcher needs to match on REG_C_6, - * so make sure its criteria bit is on. + subm->action_tbl =3D + mlx5hws_action_create_dest_table(subm->tbl->ctx, subm->tbl, + MLX5HWS_ACTION_FLAG_HWS_FDB); + if (!subm->action_tbl) { + ret =3D -EINVAL; + goto destroy_tbl; + } + + subm->bwc_matcher =3D kzalloc(sizeof(*subm->bwc_matcher), GFP_KERNEL); + if (!subm->bwc_matcher) { + ret =3D -ENOMEM; + goto destroy_action; + } + + /* Every matcher other than the first also matches of register C6 to + * bind subrules together in the complex rule using the chain ids. */ - match_criteria_enable |=3D MLX5HWS_DEFINER_MATCH_CRITERIA_MISC2; - - ret =3D mlx5hws_bwc_matcher_create_simple(isolated_bwc_matcher, - isolated_tbl, - 0, - match_criteria_enable, - mask, - NULL); - if (ret) { - mlx5hws_err(ctx, "Complex matcher: failed creating isolated BWC matcher\= n"); + match_criteria |=3D MLX5HWS_DEFINER_MATCH_CRITERIA_MISC2; + + action_types[0] =3D MLX5HWS_ACTION_TYP_MODIFY_HDR; + action_types[1] =3D MLX5HWS_ACTION_TYP_TBL; + action_types[2] =3D MLX5HWS_ACTION_TYP_LAST; + + /* Every matcher other than the last sets register C6 and jumps to the + * next submatcher's table. The final submatcher will use the + * user-supplied actions and will attach an action template at rule + * insertion time. + */ + ret =3D mlx5hws_bwc_matcher_create_simple(subm->bwc_matcher, subm->tbl, + priority, match_criteria, mask, + is_last ? NULL : action_types); + if (ret) goto free_matcher; - } + + subm->bwc_matcher->matcher_type =3D + MLX5HWS_BWC_MATCHER_COMPLEX_SUBMATCHER; + + ret =3D rhashtable_init(&subm->rules_hash, &hws_rules_hash_params); + if (ret) + goto destroy_matcher; + mutex_init(&subm->hash_lock); + ida_init(&subm->chain_ida); =20 return 0; =20 +destroy_matcher: + mlx5hws_bwc_matcher_destroy_simple(subm->bwc_matcher); free_matcher: - kfree(bwc_matcher->complex->isolated_bwc_matcher); + kfree(subm->bwc_matcher); +destroy_action: + mlx5hws_action_destroy(subm->action_tbl); +destroy_tbl: + mlx5hws_table_destroy(subm->tbl); + return ret; } =20 -static void -hws_bwc_isolated_matcher_destroy(struct mlx5hws_bwc_matcher *bwc_matcher) +static void hws_submatcher_destroy(struct mlx5hws_bwc_matcher *cmatcher, + int idx) { - mlx5hws_bwc_matcher_destroy_simple(bwc_matcher); - kfree(bwc_matcher); + struct mlx5hws_bwc_complex_submatcher *subm; + + subm =3D &cmatcher->complex->submatchers[idx]; + + ida_destroy(&subm->chain_ida); + mutex_destroy(&subm->hash_lock); + rhashtable_destroy(&subm->rules_hash); + + if (subm->bwc_matcher) { + mlx5hws_bwc_matcher_destroy_simple(subm->bwc_matcher); + if (idx) + kfree(subm->bwc_matcher); + } + + /* We own all of the isolated tables, but not the original one. */ + if (idx) { + mlx5hws_action_destroy(subm->action_tbl); + mlx5hws_table_destroy(subm->tbl); + } } =20 static int -hws_bwc_isolated_actions_create(struct mlx5hws_bwc_matcher *bwc_matcher, - struct mlx5hws_table *table) +hws_complex_data_actions_init(struct mlx5hws_bwc_matcher_complex_data *cda= ta) { - struct mlx5hws_table *isolated_tbl =3D bwc_matcher->complex->isolated_tbl; + struct mlx5hws_context *ctx =3D cdata->submatchers[0].tbl->ctx; u8 modify_hdr_action[MLX5_ST_SZ_BYTES(set_action_in)] =3D {0}; - struct mlx5hws_context *ctx =3D table->ctx; struct mlx5hws_action_mh_pattern ptrn; int ret =3D 0; =20 - /* Create action to jump to isolated table */ - - bwc_matcher->complex->action_go_to_tbl =3D - mlx5hws_action_create_dest_table(ctx, - isolated_tbl, - MLX5HWS_ACTION_FLAG_HWS_FDB); - if (!bwc_matcher->complex->action_go_to_tbl) { - mlx5hws_err(ctx, "Complex matcher: failed to create go-to-tbl action\n"); - return -EINVAL; - } - /* Create modify header action to set REG_C_6 */ - MLX5_SET(set_action_in, modify_hdr_action, action_type, MLX5_MODIFICATION_TYPE_SET); MLX5_SET(set_action_in, modify_hdr_action, @@ -895,19 +553,18 @@ hws_bwc_isolated_actions_create(struct mlx5hws_bwc_ma= tcher *bwc_matcher, ptrn.data =3D (void *)modify_hdr_action; ptrn.sz =3D MLX5HWS_ACTION_DOUBLE_SIZE; =20 - bwc_matcher->complex->action_metadata =3D + cdata->action_metadata =3D mlx5hws_action_create_modify_header(ctx, 1, &ptrn, 0, MLX5HWS_ACTION_FLAG_HWS_FDB); - if (!bwc_matcher->complex->action_metadata) { - ret =3D -EINVAL; - goto destroy_action_go_to_tbl; + if (!cdata->action_metadata) { + mlx5hws_err(ctx, "Complex matcher: failed to create set reg C6 action\n"= ); + return -EINVAL; } =20 /* Create last action */ - - bwc_matcher->complex->action_last =3D + cdata->action_last =3D mlx5hws_action_create_last(ctx, MLX5HWS_ACTION_FLAG_HWS_FDB); - if (!bwc_matcher->complex->action_last) { + if (!cdata->action_last) { mlx5hws_err(ctx, "Complex matcher: failed to create last action\n"); ret =3D -EINVAL; goto destroy_action_metadata; @@ -916,196 +573,130 @@ hws_bwc_isolated_actions_create(struct mlx5hws_bwc_= matcher *bwc_matcher, return 0; =20 destroy_action_metadata: - mlx5hws_action_destroy(bwc_matcher->complex->action_metadata); -destroy_action_go_to_tbl: - mlx5hws_action_destroy(bwc_matcher->complex->action_go_to_tbl); + mlx5hws_action_destroy(cdata->action_metadata); + return ret; } =20 static void -hws_bwc_isolated_actions_destroy(struct mlx5hws_bwc_matcher *bwc_matcher) +hws_complex_data_actions_destroy(struct mlx5hws_bwc_matcher_complex_data *= cdata) { - mlx5hws_action_destroy(bwc_matcher->complex->action_last); - mlx5hws_action_destroy(bwc_matcher->complex->action_metadata); - mlx5hws_action_destroy(bwc_matcher->complex->action_go_to_tbl); + mlx5hws_action_destroy(cdata->action_last); + mlx5hws_action_destroy(cdata->action_metadata); } =20 int mlx5hws_bwc_matcher_create_complex(struct mlx5hws_bwc_matcher *bwc_mat= cher, struct mlx5hws_table *table, - u32 priority, - u8 match_criteria_enable, + u32 priority, u8 match_criteria_enable, struct mlx5hws_match_parameters *mask) { - enum mlx5hws_action_type complex_init_action_types[3]; - struct mlx5hws_bwc_matcher *isolated_bwc_matcher; - struct mlx5hws_match_parameters mask_1 =3D {0}; - struct mlx5hws_match_parameters mask_2 =3D {0}; + struct mlx5hws_match_parameters + submasks[MLX5HWS_BWC_COMPLEX_MAX_SUBMATCHERS] =3D {0}; + struct mlx5hws_bwc_matcher_complex_data *cdata; struct mlx5hws_context *ctx =3D table->ctx; - int ret; - - ret =3D hws_bwc_matcher_complex_params_create(table->ctx, - match_criteria_enable, - mask, &mask_1, &mask_2); - if (ret) - goto err; - - bwc_matcher->complex =3D - kzalloc(sizeof(*bwc_matcher->complex), GFP_KERNEL); - if (!bwc_matcher->complex) { - ret =3D -ENOMEM; - goto free_masks; - } + int num_submatchers; + int i, ret; =20 - ret =3D rhashtable_init(&bwc_matcher->complex->refcount_hash, - &hws_refcount_hash); - if (ret) { - mlx5hws_err(ctx, "Complex matcher: failed to initialize rhashtable\n"); - goto free_complex; + for (i =3D 0; i < ARRAY_SIZE(submasks); i++) { + submasks[i].match_sz =3D MLX5_ST_SZ_BYTES(fte_match_param); + submasks[i].match_buf =3D kzalloc(submasks[i].match_sz, + GFP_KERNEL); + if (!submasks[i].match_buf) { + ret =3D -ENOMEM; + goto free_submasks; + } } =20 - mutex_init(&bwc_matcher->complex->hash_lock); - ida_init(&bwc_matcher->complex->metadata_ida); - - /* Create initial action template for the first matcher. - * Usually the initial AT is just dummy, but in case of complex - * matcher we know exactly which actions should it have. - */ - - complex_init_action_types[0] =3D MLX5HWS_ACTION_TYP_MODIFY_HDR; - complex_init_action_types[1] =3D MLX5HWS_ACTION_TYP_TBL; - complex_init_action_types[2] =3D MLX5HWS_ACTION_TYP_LAST; - - /* Create the first matcher */ - - ret =3D mlx5hws_bwc_matcher_create_simple(bwc_matcher, - table, - priority, - match_criteria_enable, - &mask_1, - complex_init_action_types); + ret =3D hws_bwc_matcher_split_mask(ctx, match_criteria_enable, mask, + submasks, &num_submatchers); if (ret) - goto destroy_ida; + goto free_submasks; =20 - /* Create isolated table to hold the second isolated matcher */ - - ret =3D hws_bwc_isolated_table_create(bwc_matcher, table); - if (ret) { - mlx5hws_err(ctx, "Complex matcher: failed creating isolated table\n"); - goto destroy_first_matcher; + cdata =3D kzalloc(sizeof(*cdata), GFP_KERNEL); + if (!cdata) { + ret =3D -ENOMEM; + goto free_submasks; } =20 - /* Now create the second BWC matcher - the isolated one */ + bwc_matcher->complex =3D cdata; + cdata->num_submatchers =3D num_submatchers; =20 - ret =3D hws_bwc_isolated_matcher_create(bwc_matcher, table, - match_criteria_enable, &mask_2); - if (ret) { - mlx5hws_err(ctx, "Complex matcher: failed creating isolated matcher\n"); - goto destroy_isolated_tbl; + for (i =3D 0; i < num_submatchers; i++) { + ret =3D hws_submatcher_init(bwc_matcher, i, table, priority, + match_criteria_enable, &submasks[i]); + if (ret) + goto destroy_submatchers; } =20 - /* Create action for isolated matcher's rules */ - - ret =3D hws_bwc_isolated_actions_create(bwc_matcher, table); - if (ret) { - mlx5hws_err(ctx, "Complex matcher: failed creating isolated actions\n"); - goto destroy_isolated_matcher; - } + ret =3D hws_complex_data_actions_init(cdata); + if (ret) + goto destroy_submatchers; =20 - hws_bwc_matcher_complex_params_destroy(&mask_1, &mask_2); - return 0; + ret =3D 0; + goto free_submasks; =20 -destroy_isolated_matcher: - isolated_bwc_matcher =3D bwc_matcher->complex->isolated_bwc_matcher; - hws_bwc_isolated_matcher_destroy(isolated_bwc_matcher); -destroy_isolated_tbl: - hws_bwc_isolated_table_destroy(bwc_matcher->complex->isolated_tbl); -destroy_first_matcher: - mlx5hws_bwc_matcher_destroy_simple(bwc_matcher); -destroy_ida: - ida_destroy(&bwc_matcher->complex->metadata_ida); - mutex_destroy(&bwc_matcher->complex->hash_lock); - rhashtable_destroy(&bwc_matcher->complex->refcount_hash); -free_complex: - kfree(bwc_matcher->complex); +destroy_submatchers: + while (i--) + hws_submatcher_destroy(bwc_matcher, i); + kfree(cdata); bwc_matcher->complex =3D NULL; -free_masks: - hws_bwc_matcher_complex_params_destroy(&mask_1, &mask_2); -err: + +free_submasks: + for (i =3D 0; i < ARRAY_SIZE(submasks); i++) + kfree(submasks[i].match_buf); + return ret; } =20 void mlx5hws_bwc_matcher_destroy_complex(struct mlx5hws_bwc_matcher *bwc_matche= r) { - struct mlx5hws_bwc_matcher *isolated_bwc_matcher =3D - bwc_matcher->complex->isolated_bwc_matcher; - - hws_bwc_isolated_actions_destroy(bwc_matcher); - hws_bwc_isolated_matcher_destroy(isolated_bwc_matcher); - hws_bwc_isolated_table_destroy(bwc_matcher->complex->isolated_tbl); - mlx5hws_bwc_matcher_destroy_simple(bwc_matcher); - ida_destroy(&bwc_matcher->complex->metadata_ida); - mutex_destroy(&bwc_matcher->complex->hash_lock); - rhashtable_destroy(&bwc_matcher->complex->refcount_hash); + int i; + + hws_complex_data_actions_destroy(bwc_matcher->complex); + for (i =3D 0; i < bwc_matcher->complex->num_submatchers; i++) + hws_submatcher_destroy(bwc_matcher, i); kfree(bwc_matcher->complex); bwc_matcher->complex =3D NULL; } =20 -static void -hws_bwc_matcher_complex_hash_lock(struct mlx5hws_bwc_matcher *bwc_matcher) -{ - mutex_lock(&bwc_matcher->complex->hash_lock); -} - -static void -hws_bwc_matcher_complex_hash_unlock(struct mlx5hws_bwc_matcher *bwc_matche= r) -{ - mutex_unlock(&bwc_matcher->complex->hash_lock); -} - static int -hws_bwc_rule_complex_hash_node_get(struct mlx5hws_bwc_rule *bwc_rule, - struct mlx5hws_match_parameters *params) +hws_complex_get_subrule_data(struct mlx5hws_bwc_rule *bwc_rule, + struct mlx5hws_bwc_complex_submatcher *subm, + u32 *match_params) +__must_hold(&subm->hash_lock) { - struct mlx5hws_bwc_matcher *bwc_matcher =3D bwc_rule->bwc_matcher; - struct mlx5hws_bwc_complex_rule_hash_node *node, *old_node; - struct rhashtable *refcount_hash; - int ret, i; - - bwc_rule->complex_hash_node =3D NULL; + struct mlx5hws_bwc_matcher *bwc_matcher =3D subm->bwc_matcher; + struct mlx5hws_bwc_complex_subrule_data *sr_data, *old_data; + struct mlx5hws_match_template *mt; + int ret; =20 - node =3D kzalloc(sizeof(*node), GFP_KERNEL); - if (unlikely(!node)) + sr_data =3D kzalloc(sizeof(*sr_data), GFP_KERNEL); + if (!sr_data) return -ENOMEM; =20 - ret =3D ida_alloc(&bwc_matcher->complex->metadata_ida, GFP_KERNEL); + ret =3D ida_alloc(&subm->chain_ida, GFP_KERNEL); if (ret < 0) - goto err_free_node; - node->tag =3D ret; + goto free_sr_data; + sr_data->chain_id =3D ret; =20 - refcount_set(&node->refcount, 1); + refcount_set(&sr_data->refcount, 1); =20 - /* Clear match buffer - turn off all the unrelated fields - * in accordance with the match params mask for the first - * matcher out of the two parts of the complex matcher. - * The resulting mask is the key for the hash. - */ - for (i =3D 0; i < MLX5_ST_SZ_DW_MATCH_PARAM; i++) - node->match_buf[i] =3D params->match_buf[i] & - bwc_matcher->mt->match_param[i]; - - refcount_hash =3D &bwc_matcher->complex->refcount_hash; - old_node =3D rhashtable_lookup_get_insert_fast(refcount_hash, - &node->hash_node, - hws_refcount_hash); - if (IS_ERR(old_node)) { - ret =3D PTR_ERR(old_node); - goto err_free_ida; + mt =3D bwc_matcher->matcher->mt; + mlx5hws_definer_create_tag(match_params, mt->fc, mt->fc_sz, + (u8 *)&sr_data->match_tag); + + old_data =3D rhashtable_lookup_get_insert_fast(&subm->rules_hash, + &sr_data->hash_node, + hws_rules_hash_params); + if (IS_ERR(old_data)) { + ret =3D PTR_ERR(old_data); + goto free_ida; } =20 - if (old_node) { + if (old_data) { /* Rule with the same tag already exists - update refcount */ - refcount_inc(&old_node->refcount); + refcount_inc(&old_data->refcount); /* Let the new rule use the same tag as the existing rule. * Note that we don't have any indication for the rule creation * process that a rule with similar matching params already @@ -1114,247 +705,283 @@ hws_bwc_rule_complex_hash_node_get(struct mlx5hws_= bwc_rule *bwc_rule, * There's some performance advantage in skipping such cases, * so this is left for future optimizations. */ - ida_free(&bwc_matcher->complex->metadata_ida, node->tag); - kfree(node); - node =3D old_node; + bwc_rule->subrule_data =3D old_data; + ret =3D 0; + goto free_ida; } =20 - bwc_rule->complex_hash_node =3D node; + bwc_rule->subrule_data =3D sr_data; return 0; =20 -err_free_ida: - ida_free(&bwc_matcher->complex->metadata_ida, node->tag); -err_free_node: - kfree(node); +free_ida: + ida_free(&subm->chain_ida, sr_data->chain_id); +free_sr_data: + kfree(sr_data); + return ret; } =20 static void -hws_bwc_rule_complex_hash_node_put(struct mlx5hws_bwc_rule *bwc_rule, - bool *is_last_rule) +hws_complex_put_subrule_data(struct mlx5hws_bwc_rule *bwc_rule, + struct mlx5hws_bwc_complex_submatcher *subm, + bool *is_last_rule) +__must_hold(&subm->hash_lock) { - struct mlx5hws_bwc_matcher *bwc_matcher =3D bwc_rule->bwc_matcher; - struct mlx5hws_bwc_complex_rule_hash_node *node; + struct mlx5hws_bwc_complex_subrule_data *sr_data; =20 if (is_last_rule) *is_last_rule =3D false; =20 - node =3D bwc_rule->complex_hash_node; - if (refcount_dec_and_test(&node->refcount)) { - rhashtable_remove_fast(&bwc_matcher->complex->refcount_hash, - &node->hash_node, - hws_refcount_hash); - ida_free(&bwc_matcher->complex->metadata_ida, node->tag); - kfree(node); + sr_data =3D bwc_rule->subrule_data; + if (refcount_dec_and_test(&sr_data->refcount)) { + rhashtable_remove_fast(&subm->rules_hash, + &sr_data->hash_node, + hws_rules_hash_params); + ida_free(&subm->chain_ida, sr_data->chain_id); + kfree(sr_data); if (is_last_rule) *is_last_rule =3D true; } =20 - bwc_rule->complex_hash_node =3D NULL; + bwc_rule->subrule_data =3D NULL; } =20 -int mlx5hws_bwc_rule_create_complex(struct mlx5hws_bwc_rule *bwc_rule, - struct mlx5hws_match_parameters *params, - u32 flow_source, - struct mlx5hws_rule_action rule_actions[], - u16 bwc_queue_idx) +static int hws_complex_subrule_create(struct mlx5hws_bwc_matcher *cmatcher, + struct mlx5hws_bwc_rule *subrule, + u32 *match_params, u32 flow_source, + int bwc_queue_idx, int subm_idx, + struct mlx5hws_rule_action *actions, + u32 *chain_id) { - struct mlx5hws_bwc_matcher *bwc_matcher =3D bwc_rule->bwc_matcher; - struct mlx5hws_context *ctx =3D bwc_matcher->matcher->tbl->ctx; + struct mlx5hws_rule_action chain_actions[HWS_NUM_CHAIN_ACTIONS] =3D {0}; u8 modify_hdr_action[MLX5_ST_SZ_BYTES(set_action_in)] =3D {0}; - struct mlx5hws_rule_action rule_actions_1[3] =3D {0}; - struct mlx5hws_bwc_matcher *isolated_bwc_matcher; - u32 *match_buf_2; - u32 metadata_val; - int ret =3D 0; + struct mlx5hws_bwc_matcher_complex_data *cdata; + struct mlx5hws_bwc_complex_submatcher *subm; + int ret; =20 - isolated_bwc_matcher =3D bwc_matcher->complex->isolated_bwc_matcher; - bwc_rule->isolated_bwc_rule =3D - mlx5hws_bwc_rule_alloc(isolated_bwc_matcher); - if (unlikely(!bwc_rule->isolated_bwc_rule)) - return -ENOMEM; + cdata =3D cmatcher->complex; + subm =3D &cdata->submatchers[subm_idx]; =20 - hws_bwc_matcher_complex_hash_lock(bwc_matcher); + mutex_lock(&subm->hash_lock); =20 - /* Get a new hash node for this complex rule. - * If this is a unique set of match params for the first matcher, - * we will get a new hash node with newly allocated IDA. - * Otherwise we will get an existing node with IDA and updated refcount. - */ - ret =3D hws_bwc_rule_complex_hash_node_get(bwc_rule, params); - if (unlikely(ret)) { - mlx5hws_err(ctx, "Complex rule: failed getting RHT node for this rule\n"= ); - goto free_isolated_rule; + ret =3D hws_complex_get_subrule_data(subrule, subm, match_params); + if (ret) + goto unlock; + + *chain_id =3D subrule->subrule_data->chain_id; + + if (!actions) { + MLX5_SET(set_action_in, modify_hdr_action, data, *chain_id); + chain_actions[0].action =3D cdata->action_metadata; + chain_actions[0].modify_header.data =3D modify_hdr_action; + chain_actions[1].action =3D + cdata->submatchers[subm_idx + 1].action_tbl; + chain_actions[2].action =3D cdata->action_last; + actions =3D chain_actions; } =20 - /* No need to clear match buffer's fields in accordance to what - * will actually be matched on first and second matchers. - * Both matchers were created with the appropriate masks - * and each of them holds the appropriate field copy array, - * so rule creation will use only the fields that will be copied - * in accordance with setters in field copy array. - * We do, however, need to temporary allocate match buffer - * for the second (isolated) rule in order to not modify - * user's match params buffer. - */ - - match_buf_2 =3D kmemdup(params->match_buf, - MLX5_ST_SZ_BYTES(fte_match_param), - GFP_KERNEL); - if (unlikely(!match_buf_2)) { - mlx5hws_err(ctx, "Complex rule: failed allocating match_buf\n"); - ret =3D -ENOMEM; - goto hash_node_put; + ret =3D mlx5hws_bwc_rule_create_simple(subrule, match_params, actions, + flow_source, bwc_queue_idx); + if (ret) { + goto put_subrule_data; + goto unlock; } =20 - /* On 2nd matcher, use unique 32-bit ID as a matching tag */ - metadata_val =3D bwc_rule->complex_hash_node->tag; - MLX5_SET(fte_match_param, match_buf_2, - misc_parameters_2.metadata_reg_c_6, metadata_val); - - /* Isolated rule's rule_actions contain all the original actions */ - ret =3D mlx5hws_bwc_rule_create_simple(bwc_rule->isolated_bwc_rule, - match_buf_2, - rule_actions, - flow_source, - bwc_queue_idx); - kfree(match_buf_2); - if (unlikely(ret)) { - mlx5hws_err(ctx, - "Complex rule: failed creating isolated BWC rule (%d)\n", - ret); - goto hash_node_put; - } + ret =3D 0; + goto unlock; =20 - /* First rule's rule_actions contain setting metadata and - * jump to isolated table that contains the second matcher. - * Set metadata value to a unique value for this rule. - */ +put_subrule_data: + hws_complex_put_subrule_data(subrule, subm, NULL); +unlock: + mutex_unlock(&subm->hash_lock); =20 - MLX5_SET(set_action_in, modify_hdr_action, - action_type, MLX5_MODIFICATION_TYPE_SET); - MLX5_SET(set_action_in, modify_hdr_action, - field, MLX5_MODI_META_REG_C_6); - MLX5_SET(set_action_in, modify_hdr_action, - length, 0); /* zero means length of 32 */ - MLX5_SET(set_action_in, modify_hdr_action, - offset, 0); - MLX5_SET(set_action_in, modify_hdr_action, - data, metadata_val); + return ret; +} =20 - rule_actions_1[0].action =3D bwc_matcher->complex->action_metadata; - rule_actions_1[0].modify_header.offset =3D 0; - rule_actions_1[0].modify_header.data =3D modify_hdr_action; +static int hws_complex_subrule_destroy(struct mlx5hws_bwc_rule *bwc_rule, + struct mlx5hws_bwc_matcher *cmatcher, + int subm_idx) +{ + struct mlx5hws_bwc_matcher_complex_data *cdata; + struct mlx5hws_bwc_complex_submatcher *subm; + struct mlx5hws_context *ctx; + bool is_last_rule; + int ret =3D 0; =20 - rule_actions_1[1].action =3D bwc_matcher->complex->action_go_to_tbl; - rule_actions_1[2].action =3D bwc_matcher->complex->action_last; + cdata =3D cmatcher->complex; + subm =3D &cdata->submatchers[subm_idx]; + ctx =3D subm->tbl->ctx; =20 - ret =3D mlx5hws_bwc_rule_create_simple(bwc_rule, - params->match_buf, - rule_actions_1, - flow_source, - bwc_queue_idx); + mutex_lock(&subm->hash_lock); =20 - if (unlikely(ret)) { + hws_complex_put_subrule_data(bwc_rule, subm, &is_last_rule); + bwc_rule->rule->skip_delete =3D !is_last_rule; + ret =3D mlx5hws_bwc_rule_destroy_simple(bwc_rule); + if (unlikely(ret)) mlx5hws_err(ctx, - "Complex rule: failed creating first BWC rule (%d)\n", - ret); - goto destroy_isolated_rule; - } + "Complex rule: failed to delete subrule %d (%d)\n", + subm_idx, ret); =20 - hws_bwc_matcher_complex_hash_unlock(bwc_matcher); + if (subm_idx) + mlx5hws_bwc_rule_free(bwc_rule); =20 - return 0; + mutex_unlock(&subm->hash_lock); =20 -destroy_isolated_rule: - mlx5hws_bwc_rule_destroy_simple(bwc_rule->isolated_bwc_rule); -hash_node_put: - hws_bwc_rule_complex_hash_node_put(bwc_rule, NULL); -free_isolated_rule: - hws_bwc_matcher_complex_hash_unlock(bwc_matcher); - mlx5hws_bwc_rule_free(bwc_rule->isolated_bwc_rule); return ret; } =20 -int mlx5hws_bwc_rule_destroy_complex(struct mlx5hws_bwc_rule *bwc_rule) +int mlx5hws_bwc_rule_create_complex(struct mlx5hws_bwc_rule *bwc_rule, + struct mlx5hws_match_parameters *params, + u32 flow_source, + struct mlx5hws_rule_action rule_actions[], + u16 bwc_queue_idx) { - struct mlx5hws_context *ctx =3D bwc_rule->bwc_matcher->matcher->tbl->ctx; - struct mlx5hws_bwc_rule *isolated_bwc_rule; - int ret_isolated, ret; - bool is_last_rule; + struct mlx5hws_bwc_rule + *subrules[MLX5HWS_BWC_COMPLEX_MAX_SUBMATCHERS] =3D {0}; + struct mlx5hws_bwc_matcher *cmatcher =3D bwc_rule->bwc_matcher; + struct mlx5hws_bwc_matcher_complex_data *cdata; + struct mlx5hws_rule_action *subrule_actions; + struct mlx5hws_bwc_complex_submatcher *subm; + struct mlx5hws_bwc_rule *subrule; + u32 *match_params; + u32 chain_id; + int i, ret; =20 - hws_bwc_matcher_complex_hash_lock(bwc_rule->bwc_matcher); + cdata =3D cmatcher->complex; + if (!cdata) + return -EINVAL; =20 - hws_bwc_rule_complex_hash_node_put(bwc_rule, &is_last_rule); - bwc_rule->rule->skip_delete =3D !is_last_rule; + /* Duplicate user data because we will modify it to set register C6 + * values. For the same reason, make sure that we allocate a full + * match_param even if the user gave us fewer bytes. We need to ensure + * there is space for the match on C6. + */ + match_params =3D kzalloc(MLX5_ST_SZ_BYTES(fte_match_param), GFP_KERNEL); + if (!match_params) + return -ENOMEM; =20 - ret =3D mlx5hws_bwc_rule_destroy_simple(bwc_rule); - if (unlikely(ret)) - mlx5hws_err(ctx, "BWC complex rule: failed destroying first rule\n"); + memcpy(match_params, params->match_buf, params->match_sz); + + ret =3D hws_complex_subrule_create(cmatcher, bwc_rule, match_params, + flow_source, bwc_queue_idx, 0, + NULL, &chain_id); + if (ret) + goto free_match_params; + subrules[0] =3D bwc_rule; + + for (i =3D 1; i < cdata->num_submatchers; i++) { + subm =3D &cdata->submatchers[i]; + subrule =3D mlx5hws_bwc_rule_alloc(subm->bwc_matcher); + if (!subrule) { + ret =3D -ENOMEM; + goto destroy_subrules; + } + + /* Match on the previous subrule's chain_id. This is how + * subrules are connected in steering. + */ + MLX5_SET(fte_match_param, match_params, + misc_parameters_2.metadata_reg_c_6, chain_id); + + /* The last subrule uses the complex rule's user-specified + * actions. Everything else uses the chaining rules based on the + * next table and chain_id. + */ + subrule_actions =3D + i =3D=3D cdata->num_submatchers - 1 ? rule_actions : NULL; + + ret =3D hws_complex_subrule_create(cmatcher, subrule, + match_params, flow_source, + bwc_queue_idx, i, + subrule_actions, &chain_id); + if (ret) { + mlx5hws_bwc_rule_free(subrule); + goto destroy_subrules; + } + + subrules[i] =3D subrule; + } + + for (i =3D 0; i < cdata->num_submatchers - 1; i++) + subrules[i]->next_subrule =3D subrules[i + 1]; =20 - isolated_bwc_rule =3D bwc_rule->isolated_bwc_rule; - ret_isolated =3D mlx5hws_bwc_rule_destroy_simple(isolated_bwc_rule); - if (unlikely(ret_isolated)) - mlx5hws_err(ctx, "BWC complex rule: failed destroying second (isolated) = rule\n"); + kfree(match_params); =20 - hws_bwc_matcher_complex_hash_unlock(bwc_rule->bwc_matcher); + return 0; =20 - mlx5hws_bwc_rule_free(isolated_bwc_rule); +destroy_subrules: + while (i--) + hws_complex_subrule_destroy(subrules[i], cmatcher, i); +free_match_params: + kfree(match_params); =20 - return ret || ret_isolated; + return ret; } =20 -static void -hws_bwc_matcher_clear_hash_rtcs(struct mlx5hws_bwc_matcher *bwc_matcher) +int mlx5hws_bwc_rule_destroy_complex(struct mlx5hws_bwc_rule *bwc_rule) { - struct mlx5hws_bwc_complex_rule_hash_node *node; - struct rhashtable_iter iter; + struct mlx5hws_bwc_matcher *bwc_matcher =3D bwc_rule->bwc_matcher; + struct mlx5hws_bwc_rule + *subrules[MLX5HWS_BWC_COMPLEX_MAX_SUBMATCHERS] =3D {0}; + struct mlx5hws_bwc_matcher_complex_data *cdata; + int i, err, ret_val; + + cdata =3D bwc_matcher->complex; + + /* Construct a list of all the subrules we need to destroy. */ + subrules[0] =3D bwc_rule; + for (i =3D 1; i < cdata->num_submatchers; i++) + subrules[i] =3D subrules[i - 1]->next_subrule; + + ret_val =3D 0; + for (i =3D 0; i < cdata->num_submatchers; i++) { + err =3D hws_complex_subrule_destroy(subrules[i], bwc_matcher, i); + /* If something goes wrong, plow along to destroy all of the + * subrules but return an error upstack. + */ + if (unlikely(err)) + ret_val =3D err; + } =20 - rhashtable_walk_enter(&bwc_matcher->complex->refcount_hash, &iter); - rhashtable_walk_start(&iter); + return ret_val; +} =20 - while ((node =3D rhashtable_walk_next(&iter)) !=3D NULL) { - if (IS_ERR(node)) +static void +hws_bwc_matcher_init_move(struct mlx5hws_bwc_matcher *bwc_matcher) +{ + struct mlx5hws_context *ctx =3D bwc_matcher->matcher->tbl->ctx; + u16 bwc_queues =3D mlx5hws_bwc_queues(ctx); + struct mlx5hws_bwc_rule *bwc_rule; + struct list_head *rules_list; + int i; + + for (i =3D 0; i < bwc_queues; i++) { + rules_list =3D &bwc_matcher->rules[i]; + if (list_empty(rules_list)) continue; - node->rtc_valid =3D false; - } =20 - rhashtable_walk_stop(&iter); - rhashtable_walk_exit(&iter); + list_for_each_entry(bwc_rule, rules_list, list_node) { + if (!bwc_rule->subrule_data) + continue; + bwc_rule->subrule_data->was_moved =3D false; + } + } } =20 -int -mlx5hws_bwc_matcher_move_all_complex(struct mlx5hws_bwc_matcher *bwc_match= er) +int mlx5hws_bwc_matcher_complex_move(struct mlx5hws_bwc_matcher *bwc_match= er) { struct mlx5hws_context *ctx =3D bwc_matcher->matcher->tbl->ctx; struct mlx5hws_matcher *matcher =3D bwc_matcher->matcher; u16 bwc_queues =3D mlx5hws_bwc_queues(ctx); struct mlx5hws_bwc_rule *tmp_bwc_rule; struct mlx5hws_rule_attr rule_attr; - struct mlx5hws_table *isolated_tbl; int move_error =3D 0, poll_error =3D 0; struct mlx5hws_rule *tmp_rule; struct list_head *rules_list; u32 expected_completions =3D 1; - u32 end_ft_id; - int i, ret; + int i, ret =3D 0; =20 - /* We are rehashing the matcher that is the first part of the complex - * matcher. Need to update the isolated matcher to point to the end_ft - * of this new matcher. This needs to be done before moving any rules - * to prevent possible steering loops. - */ - isolated_tbl =3D bwc_matcher->complex->isolated_tbl; - end_ft_id =3D bwc_matcher->matcher->resize_dst->end_ft_id; - ret =3D mlx5hws_matcher_update_end_ft_isolated(isolated_tbl, end_ft_id); - if (ret) { - mlx5hws_err(ctx, - "Failed updating end_ft of isolated matcher (%d)\n", - ret); - return ret; - } - - hws_bwc_matcher_clear_hash_rtcs(bwc_matcher); + hws_bwc_matcher_init_move(bwc_matcher); =20 mlx5hws_bwc_rule_fill_attr(bwc_matcher, 0, 0, &rule_attr); =20 @@ -1369,15 +996,15 @@ mlx5hws_bwc_matcher_move_all_complex(struct mlx5hws_= bwc_matcher *bwc_matcher) /* Check if a rule with similar tag has already * been moved. */ - if (tmp_bwc_rule->complex_hash_node->rtc_valid) { - /* This rule is a duplicate of rule with similar - * tag that has already been moved earlier. - * Just update this rule's RTCs. + if (tmp_bwc_rule->subrule_data->was_moved) { + /* This rule is a duplicate of rule with + * identical tag that has already been moved + * earlier. Just update this rule's RTCs. */ tmp_bwc_rule->rule->rtc_0 =3D - tmp_bwc_rule->complex_hash_node->rtc_0; + tmp_bwc_rule->subrule_data->rtc_0; tmp_bwc_rule->rule->rtc_1 =3D - tmp_bwc_rule->complex_hash_node->rtc_1; + tmp_bwc_rule->subrule_data->rtc_1; tmp_bwc_rule->rule->matcher =3D tmp_bwc_rule->rule->matcher->resize_dst; continue; @@ -1425,12 +1052,12 @@ mlx5hws_bwc_matcher_move_all_complex(struct mlx5hws= _bwc_matcher *bwc_matcher) /* Done moving the rule to the new matcher, * now update RTCs for all the duplicated rules. */ - tmp_bwc_rule->complex_hash_node->rtc_0 =3D + tmp_bwc_rule->subrule_data->rtc_0 =3D tmp_bwc_rule->rule->rtc_0; - tmp_bwc_rule->complex_hash_node->rtc_1 =3D + tmp_bwc_rule->subrule_data->rtc_1 =3D tmp_bwc_rule->rule->rtc_1; =20 - tmp_bwc_rule->complex_hash_node->rtc_valid =3D true; + tmp_bwc_rule->subrule_data->was_moved =3D true; } } =20 @@ -1442,3 +1069,35 @@ mlx5hws_bwc_matcher_move_all_complex(struct mlx5hws_= bwc_matcher *bwc_matcher) =20 return ret; } + +int +mlx5hws_bwc_matcher_complex_move_first(struct mlx5hws_bwc_matcher *bwc_mat= cher) +{ + struct mlx5hws_context *ctx =3D bwc_matcher->matcher->tbl->ctx; + struct mlx5hws_bwc_matcher_complex_data *cdata; + struct mlx5hws_table *isolated_tbl; + u32 end_ft_id; + int i, ret; + + cdata =3D bwc_matcher->complex; + + /* We are rehashing the first submatcher. We need to update the + * subsequent submatchers to point to the end_ft of this new matcher. + * This needs to be done before moving any rules to prevent possible + * steering loops. + */ + end_ft_id =3D bwc_matcher->matcher->resize_dst->end_ft_id; + for (i =3D 1; i < cdata->num_submatchers; i++) { + isolated_tbl =3D cdata->submatchers[i].tbl; + ret =3D mlx5hws_matcher_update_end_ft_isolated(isolated_tbl, + end_ft_id); + if (ret) { + mlx5hws_err(ctx, + "Complex matcher: failed updating end_ft of isolated matcher (%d)\= n", + ret); + return ret; + } + } + + return mlx5hws_bwc_matcher_complex_move(bwc_matcher); +} diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc_compl= ex.h b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc_complex.h index a6887c7e39d5..d07de631ce9f 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc_complex.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc_complex.h @@ -4,25 +4,60 @@ #ifndef HWS_BWC_COMPLEX_H_ #define HWS_BWC_COMPLEX_H_ =20 -struct mlx5hws_bwc_complex_rule_hash_node { - u32 match_buf[MLX5_ST_SZ_DW_MATCH_PARAM]; - u32 tag; +#define MLX5HWS_BWC_COMPLEX_MAX_SUBMATCHERS 4 + +/* A matcher can't contain two rules with the same match tag, but it is po= ssible + * that two different complex rules' subrules have the same match tag. In = that + * case, those subrules correspond to a single rule, and we need to refcou= nt. + */ +struct mlx5hws_bwc_complex_subrule_data { + struct mlx5hws_rule_match_tag match_tag; refcount_t refcount; - bool rtc_valid; + /* The chain_id is what glues individual subrules into larger complex + * rules. It is the value that this subrule writes to register C6, and + * that the next subrule matches against. + */ + u32 chain_id; u32 rtc_0; u32 rtc_1; + /* During rehash we iterate through all the subrules to move them. But + * two or more subrules can share the same physical rule in the + * submatcher, so we use `was_moved` to keep track if a given rule was + * already moved. + */ + bool was_moved; struct rhash_head hash_node; }; =20 +struct mlx5hws_bwc_complex_submatcher { + /* Isolated table that the matcher lives in. Not set for the first + * matcher, which lives in the original table. + */ + struct mlx5hws_table *tbl; + /* Match a rule with this action to go to `tbl`. This is set in all + * submatchers but the first. + */ + struct mlx5hws_action *action_tbl; + /* This submatcher's simple matcher. The first submatcher points to the + * outer (complex) matcher. + */ + struct mlx5hws_bwc_matcher *bwc_matcher; + struct rhashtable rules_hash; + struct ida chain_ida; + struct mutex hash_lock; /* Protect the hash and ida. */ +}; + struct mlx5hws_bwc_matcher_complex_data { - struct mlx5hws_table *isolated_tbl; - struct mlx5hws_bwc_matcher *isolated_bwc_matcher; + struct mlx5hws_bwc_complex_submatcher + submatchers[MLX5HWS_BWC_COMPLEX_MAX_SUBMATCHERS]; + int num_submatchers; + /* Actions used by all but the last submatcher to point to the next + * submatcher in the chain. The last submatcher uses the action template + * from the complex matcher, to perform the actions that the user + * originally requested. + */ struct mlx5hws_action *action_metadata; - struct mlx5hws_action *action_go_to_tbl; struct mlx5hws_action *action_last; - struct rhashtable refcount_hash; - struct mutex hash_lock; /* Protect the refcount rhashtable */ - struct ida metadata_ida; }; =20 bool mlx5hws_bwc_match_params_is_complex(struct mlx5hws_context *ctx, @@ -37,7 +72,10 @@ int mlx5hws_bwc_matcher_create_complex(struct mlx5hws_bw= c_matcher *bwc_matcher, =20 void mlx5hws_bwc_matcher_destroy_complex(struct mlx5hws_bwc_matcher *bwc_m= atcher); =20 -int mlx5hws_bwc_matcher_move_all_complex(struct mlx5hws_bwc_matcher *bwc_m= atcher); +int mlx5hws_bwc_matcher_complex_move(struct mlx5hws_bwc_matcher *bwc_match= er); + +int +mlx5hws_bwc_matcher_complex_move_first(struct mlx5hws_bwc_matcher *bwc_mat= cher); =20 int mlx5hws_bwc_rule_create_complex(struct mlx5hws_bwc_rule *bwc_rule, struct mlx5hws_match_parameters *params, diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/definer.c= b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/definer.c index c4bb6967f74d..82fd122d4284 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/definer.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/definer.c @@ -1831,80 +1831,6 @@ hws_definer_conv_match_params_to_hl(struct mlx5hws_c= ontext *ctx, return ret; } =20 -struct mlx5hws_definer_fc * -mlx5hws_definer_conv_match_params_to_compressed_fc(struct mlx5hws_context = *ctx, - u8 match_criteria_enable, - u32 *match_param, - int *fc_sz) -{ - struct mlx5hws_definer_fc *compressed_fc =3D NULL; - struct mlx5hws_definer_conv_data cd =3D {0}; - struct mlx5hws_definer_fc *fc; - int ret; - - fc =3D hws_definer_alloc_fc(ctx, MLX5HWS_DEFINER_FNAME_MAX); - if (!fc) - return NULL; - - cd.fc =3D fc; - cd.ctx =3D ctx; - - if (match_criteria_enable & MLX5HWS_DEFINER_MATCH_CRITERIA_OUTER) { - ret =3D hws_definer_conv_outer(&cd, match_param); - if (ret) - goto err_free_fc; - } - - if (match_criteria_enable & MLX5HWS_DEFINER_MATCH_CRITERIA_INNER) { - ret =3D hws_definer_conv_inner(&cd, match_param); - if (ret) - goto err_free_fc; - } - - if (match_criteria_enable & MLX5HWS_DEFINER_MATCH_CRITERIA_MISC) { - ret =3D hws_definer_conv_misc(&cd, match_param); - if (ret) - goto err_free_fc; - } - - if (match_criteria_enable & MLX5HWS_DEFINER_MATCH_CRITERIA_MISC2) { - ret =3D hws_definer_conv_misc2(&cd, match_param); - if (ret) - goto err_free_fc; - } - - if (match_criteria_enable & MLX5HWS_DEFINER_MATCH_CRITERIA_MISC3) { - ret =3D hws_definer_conv_misc3(&cd, match_param); - if (ret) - goto err_free_fc; - } - - if (match_criteria_enable & MLX5HWS_DEFINER_MATCH_CRITERIA_MISC4) { - ret =3D hws_definer_conv_misc4(&cd, match_param); - if (ret) - goto err_free_fc; - } - - if (match_criteria_enable & MLX5HWS_DEFINER_MATCH_CRITERIA_MISC5) { - ret =3D hws_definer_conv_misc5(&cd, match_param); - if (ret) - goto err_free_fc; - } - - /* Allocate fc array on mt */ - compressed_fc =3D hws_definer_alloc_compressed_fc(fc); - if (!compressed_fc) { - mlx5hws_err(ctx, - "Convert to compressed fc: failed to set field copy to match templa= te\n"); - goto err_free_fc; - } - *fc_sz =3D hws_definer_get_fc_size(fc); - -err_free_fc: - kfree(fc); - return compressed_fc; -} - static int hws_definer_find_byte_in_tag(struct mlx5hws_definer *definer, u32 hl_byte_off, @@ -2067,7 +1993,7 @@ hws_definer_copy_sel_ctrl(struct mlx5hws_definer_sel_= ctrl *ctrl, static int hws_definer_find_best_match_fit(struct mlx5hws_context *ctx, struct mlx5hws_definer *definer, - u8 *hl) + u8 *hl, bool allow_jumbo) { struct mlx5hws_definer_sel_ctrl ctrl =3D {0}; bool found; @@ -2084,6 +2010,9 @@ hws_definer_find_best_match_fit(struct mlx5hws_contex= t *ctx, return 0; } =20 + if (!allow_jumbo) + return -E2BIG; + /* Try to create a full/limited jumbo definer */ ctrl.allowed_full_dw =3D ctx->caps->full_dw_jumbo_support ? DW_SELECTORS : DW_SELECTORS_MATCH; @@ -2160,7 +2089,8 @@ int mlx5hws_definer_compare(struct mlx5hws_definer *d= efiner_a, int mlx5hws_definer_calc_layout(struct mlx5hws_context *ctx, struct mlx5hws_match_template *mt, - struct mlx5hws_definer *match_definer) + struct mlx5hws_definer *match_definer, + bool allow_jumbo) { u8 *match_hl; int ret; @@ -2182,7 +2112,8 @@ mlx5hws_definer_calc_layout(struct mlx5hws_context *c= tx, } =20 /* Find the match definer layout for header layout match union */ - ret =3D hws_definer_find_best_match_fit(ctx, match_definer, match_hl); + ret =3D hws_definer_find_best_match_fit(ctx, match_definer, match_hl, + allow_jumbo); if (ret) { if (ret =3D=3D -E2BIG) mlx5hws_dbg(ctx, @@ -2370,7 +2301,7 @@ int mlx5hws_definer_mt_init(struct mlx5hws_context *c= tx, struct mlx5hws_definer match_layout =3D {0}; int ret; =20 - ret =3D mlx5hws_definer_calc_layout(ctx, mt, &match_layout); + ret =3D mlx5hws_definer_calc_layout(ctx, mt, &match_layout, true); if (ret) { mlx5hws_err(ctx, "Failed to calculate matcher definer layout\n"); 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Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , , , , Gal Pressman , Moshe Shemesh , Jianbo Liu Subject: [PATCH net-next 2/7] net/mlx5e: Prevent entering switchdev mode with inconsistent netns Date: Mon, 22 Sep 2025 12:01:06 +0300 Message-ID: <1758531671-819655-3-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1758531671-819655-1-git-send-email-tariqt@nvidia.com> References: <1758531671-819655-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF00000146:EE_|BN7PPF49208036B:EE_ X-MS-Office365-Filtering-Correlation-Id: ca40de6f-4d8e-4c40-3ac9-08ddf9b6b1fa X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|36860700013|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?j1EkWjbhQuzRv3hgP5TLkhMVSQsMkQmcDWQBSZyZNbSpjH0P71rZoWbEkVG2?= =?us-ascii?Q?rNSpViQcnVfbmtRwZERpAdi8EMlkDdyHjApIJ1whNRysdqey5VyZVXm2c2vg?= =?us-ascii?Q?zlnha0F9D9XLEbXcuxkRt54qmkB3NZUNlhoqGGmDL3GtANildsiEqZRont52?= =?us-ascii?Q?2HQN+oFYgC+LVpDG8w8gGXuXyUYOb+mIyynzs0gAOeH9kmnM2CC+7i0juHmL?= =?us-ascii?Q?0/xD9qjekwJRFdQDvadW98aX5dXR6MJJTQAyvuHzsKFh2Q/70mcmxco0PPd1?= =?us-ascii?Q?nLMmaKzVE8YMw0xYjI+S2HB7DAeGN/bhXWYtMWp9qeVcSUaX1j9cNxD53Gts?= =?us-ascii?Q?+adJSYCpAw8NaOpyBSzPolOkJu6atAzNIz4thJ1q7SdTns1CBptmrCaenbdB?= =?us-ascii?Q?tvAGlHxIJuK2B0hOj645LmzbX9oG+4f8HxB0F4CquSLzHYgE3R8e92+3ORdp?= =?us-ascii?Q?4wzTwc4cTrs4yLQlWRWZS219zjHVw/ptznNQK64csGSbj3XLknPfzNizbkjk?= =?us-ascii?Q?fgvX1+6EwLr+BAkZaCve28N5io7L+ScrMJFDIWxszrtJIM7OMY7eIpKoU+3Z?= =?us-ascii?Q?c/rdlETBYj5jsuPvI0JATNWkasvKCuIjqEMAkqWsK77TfSkddcoT4Tld2bHw?= =?us-ascii?Q?GBKMVolWH8x/zJ8FKo41OKY8EpBOOs+/zKHR6V+eDGwy1QWJyM3DyPYxZ+wb?= =?us-ascii?Q?FRfnvsNqSPX/a9oFxBSSC+fhmFh7vOFsk8Jsc9/0uTmH7+hZJH+tDRrGSKkp?= =?us-ascii?Q?qSiKuAqketI+lKBObW7eS3FPCD2c+KzMu7RLXKhaX3DIEjvA3H4qHZ1Nf5fA?= =?us-ascii?Q?dm1WF4RmcwQafcFi4TH3p48MZDSUH34jyvONAXNqT+82txVTfv7DAwbUnyFD?= =?us-ascii?Q?pJBf3TdFIhvQazDVLVO2M3bHjTfijsd4/M3ApoPzas4ys2fkguhty1xkctFZ?= =?us-ascii?Q?F19kTJMFkc6XBOxy3dW+TACVk/O/mqsJO69cMZ9XtXgXnz4ayOypjzPHmYBj?= =?us-ascii?Q?VXEzqF4zea3teSWYRxYoazgAg82rNGCcNVpuumnPmO9sjFMp+1Y5BUQv/Fr8?= =?us-ascii?Q?f0YzMPth0t9r+p2d+DhSoskcxXa+jNCzk2RHtFGm2YKjYFxmuBOtxU2hh9DY?= =?us-ascii?Q?R9AIhDOwRf/bopnxQ9qolBVSoJ081OuJLpMyp8voHdMKFd+qg4yWytiknk1e?= =?us-ascii?Q?iMgmo03yFw/AbfKiI9I8M1nC9NcWnWJ3X1mby/+xpnoviE8TJCI9HMaHhI32?= =?us-ascii?Q?iyE4jSKCPTxomUUiScKtWalr3rNdhaiIRJjT4DKKfRPvE1kZAfTDvC9DmPkD?= =?us-ascii?Q?B2jveuTfJ7NcORRgjDxBN5gBn9dEeU5XBYAxeEaZhKbKwgbO2k5hZxgwaKOR?= =?us-ascii?Q?puweQGGWMYLvDQWB5YqxJ66ilIPBChAjrDfWw14Z7KbMjnWUmaz7PwulrUxX?= =?us-ascii?Q?jT4wD1+komgfUIjjzfWpWtnSCcr3UtZE6pFwsBKUjpr3XIoH4X3A3IxpwJkO?= =?us-ascii?Q?QJnjzYvJUfPzlBGsqqWt9b/lSJd36BIZRYSjxUO1XWfta1/+1JXA32spXA?= =?us-ascii?Q?=3D=3D?= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(1800799024)(36860700013)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Sep 2025 09:02:02.0440 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ca40de6f-4d8e-4c40-3ac9-08ddf9b6b1fa X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF00000146.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN7PPF49208036B Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Jianbo Liu When a PF enters switchdev mode, its netdevice becomes the uplink representor but remains in its current network namespace. All other representors (VFs, SFs) are created in the netns of the devlink instance. If the PF's netns has been moved and differs from the devlink's netns, enabling switchdev mode would create a state where the OVS control plane (ovs-vsctl) cannot manage the switch because the PF uplink representor and the other representors are split across different namespaces. To prevent this inconsistent configuration, block the request to enter switchdev mode if the PF netdevice's netns does not match the netns of its devlink instance. As part of this change, the PF's netns is first marked as immutable. This prevents race conditions where the netns could be changed after the check is performed but before the mode transition is complete, and it aligns the PF's behavior with that of the final uplink representor. Signed-off-by: Jianbo Liu Reviewed-by: Cosmin Ratiu Reviewed-by: Jiri Pirko Reviewed-by: Dragos Tatulea Signed-off-by: Tariq Toukan --- .../mellanox/mlx5/core/eswitch_offloads.c | 33 +++++++++++++++++++ 1 file changed, 33 insertions(+) Previously submitted to net: https://lore.kernel.org/all/1757939074-617281-3-git-send-email-tariqt@nvidi= a.com/ diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c b/d= rivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c index bc9838dc5bf8..ff6e0130de38 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c @@ -3772,6 +3772,29 @@ void mlx5_eswitch_unblock_mode(struct mlx5_core_dev = *dev) up_write(&esw->mode_lock); } =20 +/* Returns false only when uplink netdev exists and its netns is different= from + * devlink's netns. True for all others so entering switchdev mode is allo= wed. + */ +static bool mlx5_devlink_netdev_netns_immutable_set(struct devlink *devlin= k, + bool immutable) +{ + struct mlx5_core_dev *mdev =3D devlink_priv(devlink); + struct net_device *netdev; + bool ret; + + netdev =3D mlx5_uplink_netdev_get(mdev); + if (!netdev) + return true; + + rtnl_lock(); + netdev->netns_immutable =3D immutable; + ret =3D net_eq(dev_net(netdev), devlink_net(devlink)); + rtnl_unlock(); + + mlx5_uplink_netdev_put(mdev, netdev); + return ret; +} + int mlx5_devlink_eswitch_mode_set(struct devlink *devlink, u16 mode, struct netlink_ext_ack *extack) { @@ -3814,6 +3837,14 @@ int mlx5_devlink_eswitch_mode_set(struct devlink *de= vlink, u16 mode, esw->eswitch_operation_in_progress =3D true; up_write(&esw->mode_lock); =20 + if (mode =3D=3D DEVLINK_ESWITCH_MODE_SWITCHDEV && + !mlx5_devlink_netdev_netns_immutable_set(devlink, true)) { + NL_SET_ERR_MSG_MOD(extack, + "Can't change E-Switch mode to switchdev when netdev net namespace = has diverged from the devlink's."); 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Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , , , , Gal Pressman , Moshe Shemesh , Carolina Jubran Subject: [PATCH net-next 3/7] net/mlx5: Improve QoS error messages with actual depth values Date: Mon, 22 Sep 2025 12:01:07 +0300 Message-ID: <1758531671-819655-4-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1758531671-819655-1-git-send-email-tariqt@nvidia.com> References: <1758531671-819655-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF00000145:EE_|LV2PR12MB5917:EE_ X-MS-Office365-Filtering-Correlation-Id: e7691fb7-2b89-4d29-db86-08ddf9b6b3e8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|82310400026|376014|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?Zr0E50UtNCiwBNAKGup+td9aZ4IPshRYAmxEyGW+beMJvi/rRM7woL2j65V7?= =?us-ascii?Q?HD/PD6IBw9hVle+3g/XsMElqYl+9mYRQ6HBok2cfEvf/0H1JyR2atX4rnTLl?= =?us-ascii?Q?zS31IVtmkRX2A4a6rgsa7n9CehYPJF+SMx6Jm0vuYVzr6CA+JL7NpaZ7BWsJ?= =?us-ascii?Q?hWM7y6H8a/nOmpc5dgUFlZZEBph9ERok/6hdqFpJWCev7aAzLxHJ1hhfTKvT?= =?us-ascii?Q?+zcU6/2oxPIZUp9HrOql8+3uNF67flBehXt6M5r0GFWGHhyRFLFrXZg59/60?= =?us-ascii?Q?0mPp/iKl6pn6ebgHW/CA9MJko/jci8BsvaBszCz+y2NeshyRhROJjHyueI6L?= =?us-ascii?Q?/J7YewRpo2L8Aix0nUixLtL7uGDF/t9RrRkyJ6rAFV84/CDyx1QP1Srp5eI1?= =?us-ascii?Q?IZqjCP/df1Yv7GwMfe+JgItrBjL4wKXqGNW6Kfae744CxJeD+hFyhc/qLBnj?= =?us-ascii?Q?cCMzLdiwWOD7q9VGOcjQLLzDUm2LDb3DMv3RUA9P5DFISXKAdTtI3+1wWBIb?= =?us-ascii?Q?LdJcniidY5xFns0f1tnuj8iNF38kRcx66+yoZK7ICZ/NuPcPffezLEN6VL5B?= =?us-ascii?Q?TcR2Ovf3b0WbrWBQIR6qmdZpFPWvU4j+I/LtW4ILD5TWfDmMR1nrIovg7L4c?= =?us-ascii?Q?ltmLMvKpZX6bwXvAlbIancuNeaBnOkbk1HZ+vLhhLV9NK9C+EaBk9VXMvApc?= =?us-ascii?Q?/gbMfxonj1KhXqAXmZPyKj1rWfX3LQTPfX7TOM2ymhTQp9Yy9bWl5tu3gUlK?= =?us-ascii?Q?Ka5Xfh0C7IktnHbg+LWyTfW2jtV7K2z7tJUKewIor5YuUvKXHZ4AUdFv+6Zq?= =?us-ascii?Q?1RYd2ttiva1rnwm4ejJmSfJEgnMb6mzj1mpbu8yJK9gPvV+209gI50wjod27?= =?us-ascii?Q?nvk2L/ju9Frucc3zwbfASz4y9Q+xFtMFp62BAG0sgAU9XvHPsMPJHCy53l/w?= =?us-ascii?Q?gGfbfTgpzc6P2MqIvVaM2Vp+rBXC5b9bHMmmdtg9mnRO3UcUMqSrRaxOfvBM?= =?us-ascii?Q?vT1rJba/wrzLAjLcmnHYBhL2oplP0QP0hfoKU2s/S5asy9Q8iaCWKgNUiZ+2?= =?us-ascii?Q?3/BBHblCjj5tMgpnDz7/2YuukfX1yOBy/54E2kexgOIIlifE2u1jASgvpuTl?= =?us-ascii?Q?9OXVVSI3+E5jg+rw7N9/1QYehZqbmpU+0IjW8TU7XbtRgcXc7t1/nF6jSjwh?= =?us-ascii?Q?/Ff/SxKCGLXSqXbn3WlE0Xd98V5+JhWSNZjdL2DO+0AFJ+lxpS+NAQ5Y95si?= =?us-ascii?Q?WOp3+hrm0D9bzL3DLn43auWhD91t1f/IW9sFHii+a77cnHdBpFcNKrgQ8iDG?= =?us-ascii?Q?LBxGHDD8P5Dwg6ccK1T9FTOSV+YEc17h5NazCGWQ7V7ZsccYu0ef4CRQ01H5?= =?us-ascii?Q?HEpRdSCQdWaQg5hmq8FuRF46y6895sTJBp0rGE8rD6iyKJcKq6N1YLVjky3A?= =?us-ascii?Q?r0D9KKIKCg4LROx5PAqv/20eR8h3GGXVODCe1D6FPwoanIcJpXKQByuUOuxg?= =?us-ascii?Q?N+ZBlJ6Zaiyo7VFTQupNbjIz0k2TaPvj0m+A?= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(82310400026)(376014)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Sep 2025 09:02:05.2629 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e7691fb7-2b89-4d29-db86-08ddf9b6b3e8 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF00000145.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV2PR12MB5917 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Carolina Jubran Enhance error messages in MLX5 QoS scheduling depth validation by including the actual values that caused the validation to fail. Suggested-by: Paolo Abeni Signed-off-by: Carolina Jubran Reviewed-by: Cosmin Ratiu Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/esw/qos.c index 5f2d6c35f1ad..8574eb96f606 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c @@ -971,8 +971,9 @@ esw_qos_vport_tc_enable(struct mlx5_vport *vport, enum = sched_node_type type, max_level =3D 1 << MLX5_CAP_QOS(vport_node->esw->dev, log_esw_max_sched_depth); if (new_level > max_level) { - NL_SET_ERR_MSG_MOD(extack, - "TC arbitration on leafs is not supported beyond max scheduling de= pth"); + NL_SET_ERR_MSG_FMT_MOD(extack, + "TC arbitration on leafs is not supported beyond max schedulin= g depth %d", + max_level); return -EOPNOTSUPP; } } @@ -1444,8 +1445,9 @@ static int esw_qos_node_enable_tc_arbitration(struct = mlx5_esw_sched_node *node, new_level =3D node->level + 1; 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Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , , , , Gal Pressman , Moshe Shemesh , Carolina Jubran Subject: [PATCH net-next 4/7] net/mlx5e: Remove unused mdev param from RSS indir init Date: Mon, 22 Sep 2025 12:01:08 +0300 Message-ID: <1758531671-819655-5-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1758531671-819655-1-git-send-email-tariqt@nvidia.com> References: <1758531671-819655-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PEPF0000B076:EE_|PH7PR12MB8596:EE_ X-MS-Office365-Filtering-Correlation-Id: 9a398e95-4f7d-43aa-8c56-08ddf9b6b69f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|36860700013|376014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?86BBwAdmhd2gZWedPykyq4mcsYMNghBgV7OqjQmS1tU4X1yeDi6++DHQL+xh?= =?us-ascii?Q?i6RyvQt3KAzd42oewSpH8xgz+bTJGal7CSs3O2dqe7KlJyh6UqtSf2F5ftLy?= =?us-ascii?Q?ua6VEPY+4OEYTYvLdmEH1I/RPmwcIXoBQwTmwmq0nIpqS4dn/reN4vB6qVh4?= =?us-ascii?Q?ZrAnv3LeW5IrOB1S03uuzHURL8510TlEof+j9X2HEURSogmty3GOvTEF8e/w?= =?us-ascii?Q?DISHGxRQh8MVijiNVbSrcTZp/bXse5InzZmTuAuYr0slFMp9rRfYTssxDwxi?= =?us-ascii?Q?fASyoHO6Q73pzH0ZEQcFdEy/h2YyYFzvYFzSs2x/LlL8bIz2fUUF8XlqFvWt?= =?us-ascii?Q?cezMmaii1XpcIjS6sVxlSO0o5JvjaLBVkM1YItUfRAHHSTN00AMrDuFS0tV8?= =?us-ascii?Q?cnL6rgGF31K7o3kd466akS0veJAZQYB9S52sVrk4RSxuF1RVQFbgsbjW92Ns?= =?us-ascii?Q?5qLdnuBHeWa3HJ7V0ojviWgMgaJOrHAEFCcugW47fA3fCuCnpfGoHCqaOr6g?= =?us-ascii?Q?E3DGCiabIuS+z9YPGpgh2hIvirpR7OkRVLhfXeyHwAZdpXMx77ycxRaB/8og?= =?us-ascii?Q?9htA1UJH1+nmZF19VisfNKDHoPLV430xLyvdMgD39EkeFY/BzEr2SykRvJfm?= =?us-ascii?Q?Egmk+o9JRfBMwvCES01aYETiOgIvnXzBKYbLYvTWGEPxkk09CaCZjBxSr8z1?= =?us-ascii?Q?JuRawaKD8YkESSVbSOAs9Ig2zusbuw0cbp1zfq2lPvuQtyKWKI6+qeOP7aNO?= =?us-ascii?Q?d5phQW5ArbsS/O46SI4vYxSjykdX34q3n/J3OtTfAA9fLwhKgfqT0FxodCwQ?= =?us-ascii?Q?r1ER9c5FtzTkDW5JVk3N9xu0nDBWZOx/plaVAYYtHGoFdpXI60c8LQzaj+KT?= =?us-ascii?Q?whFov2cybDZ94cg9vTU9zQISY25fV+Ectf3EsGwxLcRiNj4ucaeeelzpGc6t?= =?us-ascii?Q?0AMXTf/9xfPYEzXvEsCJAhLyPwhOheYSmr+EylWA+YPViWEV7eJRfv0bPTK4?= =?us-ascii?Q?N7l0+fLN5Py1Te/anlwMdUsa6UPcMhSw30Moku9I71Z2PYNKCiI6L/AbY2l7?= =?us-ascii?Q?h0NsDA6nCYXvNREvQCGX934Cc39Cs6jKIVm+u+L65dbHAuBXSCh87VRMY5pz?= =?us-ascii?Q?sXLCM5Rw2gmQZRFZIsnqG8dEWO7yAdLoMofJGCnGHY8pWfEy8bK9sO5boKJX?= =?us-ascii?Q?Cm+AGXZ2JIGRMPFnAmvYHzgnTMfj5wK4V5a8Px0Uy3SUS2uwwzuHNdI/j81O?= =?us-ascii?Q?39B16++7clWNgRhryKfzXl/r5N7nTplt47eA9NRG2ClMn1Fhv33zNJI0He7k?= =?us-ascii?Q?L0AJ2M3DamWFKKJdwVD8/tB394ZVp2bcZZPgPNF97xzkOGsqAbWBE3/6qcms?= =?us-ascii?Q?8st6H52daZdD2p8N6pNhuAdozDLa3PO8AuNWoz0JE64szGupbkSaH/znri6M?= =?us-ascii?Q?MaoLk2WAViRmN9rucLizGZ6GUB+mj9dNLBBNYze3k9gMwMIRvaIFJbxeTZnc?= =?us-ascii?Q?5BDOcQGL3Y6uFd+ig1lw/TLjTjKtrnHKWZzB?= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(36860700013)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Sep 2025 09:02:09.7981 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9a398e95-4f7d-43aa-8c56-08ddf9b6b69f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B076.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB8596 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Carolina Jubran The mdev parameter is not used in mlx5e_rss_params_indir_init, so drop it from the function and update all callers accordingly. No functional changes. Signed-off-by: Carolina Jubran Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/en/rss.c | 12 +++++++----- drivers/net/ethernet/mellanox/mlx5/core/en/rss.h | 2 +- drivers/net/ethernet/mellanox/mlx5/core/en_tc.c | 6 +++--- 3 files changed, 11 insertions(+), 9 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/rss.c b/drivers/net= /ethernet/mellanox/mlx5/core/en/rss.c index c68ba0e58fa6..6422eeabc334 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/rss.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/rss.c @@ -91,7 +91,7 @@ void mlx5e_rss_params_indir_modify_actual_size(struct mlx= 5e_rss *rss, u32 num_ch rss->indir.actual_table_size =3D mlx5e_rqt_size(rss->mdev, num_channels); } =20 -int mlx5e_rss_params_indir_init(struct mlx5e_rss_params_indir *indir, stru= ct mlx5_core_dev *mdev, +int mlx5e_rss_params_indir_init(struct mlx5e_rss_params_indir *indir, u32 actual_table_size, u32 max_table_size) { indir->table =3D kvmalloc_array(max_table_size, sizeof(*indir->table), GF= P_KERNEL); @@ -139,7 +139,8 @@ static struct mlx5e_rss *mlx5e_rss_init_copy(const stru= ct mlx5e_rss *from) if (!rss) return ERR_PTR(-ENOMEM); =20 - err =3D mlx5e_rss_params_indir_init(&rss->indir, from->mdev, from->indir.= actual_table_size, + err =3D mlx5e_rss_params_indir_init(&rss->indir, + from->indir.actual_table_size, from->indir.max_table_size); if (err) goto err_free_rss; @@ -363,6 +364,7 @@ struct mlx5e_rss *mlx5e_rss_init(struct mlx5_core_dev *= mdev, bool inner_ft_suppo enum mlx5e_rss_init_type type, unsigned int nch, unsigned int max_nch) { + u32 rqt_max_size, rqt_size; struct mlx5e_rss *rss; int err; =20 @@ -370,9 +372,9 @@ struct mlx5e_rss *mlx5e_rss_init(struct mlx5_core_dev *= mdev, bool inner_ft_suppo if (!rss) return ERR_PTR(-ENOMEM); =20 - err =3D mlx5e_rss_params_indir_init(&rss->indir, mdev, - mlx5e_rqt_size(mdev, nch), - mlx5e_rqt_size(mdev, max_nch)); + rqt_size =3D mlx5e_rqt_size(mdev, nch); + rqt_max_size =3D mlx5e_rqt_size(mdev, max_nch); + err =3D mlx5e_rss_params_indir_init(&rss->indir, rqt_size, rqt_max_size); if (err) goto err_free_rss; =20 diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/rss.h b/drivers/net= /ethernet/mellanox/mlx5/core/en/rss.h index c6c1b2847cf5..616097c8770e 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/rss.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/rss.h @@ -18,7 +18,7 @@ mlx5e_rss_get_default_tt_config(enum mlx5_traffic_types t= t); =20 struct mlx5e_rss; =20 -int mlx5e_rss_params_indir_init(struct mlx5e_rss_params_indir *indir, stru= ct mlx5_core_dev *mdev, +int mlx5e_rss_params_indir_init(struct mlx5e_rss_params_indir *indir, u32 actual_table_size, u32 max_table_size); void mlx5e_rss_params_indir_cleanup(struct mlx5e_rss_params_indir *indir); void mlx5e_rss_params_indir_modify_actual_size(struct mlx5e_rss *rss, u32 = num_channels); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_tc.c b/drivers/net/= ethernet/mellanox/mlx5/core/en_tc.c index b6d6584fc6fe..00c2763e57ca 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_tc.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_tc.c @@ -758,11 +758,11 @@ static int mlx5e_hairpin_create_indirect_rqt(struct m= lx5e_hairpin *hp) struct mlx5e_priv *priv =3D hp->func_priv; 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Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , , , , Gal Pressman , Moshe Shemesh , Carolina Jubran Subject: [PATCH net-next 5/7] net/mlx5e: Introduce mlx5e_rss_init_params Date: Mon, 22 Sep 2025 12:01:09 +0300 Message-ID: <1758531671-819655-6-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1758531671-819655-1-git-send-email-tariqt@nvidia.com> References: <1758531671-819655-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF00000149:EE_|DS0PR12MB6461:EE_ X-MS-Office365-Filtering-Correlation-Id: f0c4cfe8-4f96-4631-0907-08ddf9b6b9e8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700013|1800799024|376014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?kumPIkHLt0URz44Jw0MNks04iK3xjMgATkewFtZ91Sw+k0ZXMkTn6vlKSo04?= =?us-ascii?Q?U0dNLNc+pTBT6MuhiBi4+dDLXo93Pxsu0mweIJHX7t3labixnxK3SM7XMC38?= =?us-ascii?Q?D3uwSI2P6llQ0Q40B6PTWKVyNto2DgDDQgT+RAM7s32tyuBPQwXnnKrWdpwm?= =?us-ascii?Q?0TPVuyOdldU0UU37it7IfuxUyqtfZsYdgPDl8b34oKd/1ujNjYKb6x6eYAWu?= =?us-ascii?Q?Pt+mfJPsLZH4lFU6mWUGcSiy+W/i6/YF9OWuQUMvejBwrxs34GYTVvlZutOm?= =?us-ascii?Q?Dp9mC9V/JNrBCzdqZx5fQ3pDCv52CMvBmmwAdDumyckYTzc1tGjvF37L2Vgh?= =?us-ascii?Q?hwsvFgF22IrP8Dp9Y94KldKTl2ZaFrLO2OhDMoA1ormIJdIzB8IN8asGsx06?= =?us-ascii?Q?BTt2K7lHzcpbMZA5k55zl88DPtI2qdfdafHU9SdrTWfFahex+w55JIBDMO9w?= =?us-ascii?Q?mNAnuaYtkJRGZMOkCLAOE5miZKuS3M2DgsbSwscUZLIt5CoCBae8QyblokT+?= =?us-ascii?Q?F1x0kYh1iRWdGe/4OiiaPOaEW4HIHgj6zdUEWmXCLAq0tmQ6Mk69yBYCAkzl?= =?us-ascii?Q?H6x+OkaY0zYAq2dzbNRpDLJcGGT5t7ES39vN64XAoEac6Un/0wBH/0UXXQ+U?= =?us-ascii?Q?KjiTATRuG3Awmdg34M67jyBWQ9sMeiDpFIfbRSLyIf/KaoN5Mgb3H13s+sZw?= =?us-ascii?Q?PdwJBJFMaC4dSBwFpnSGlHGC5keSwRmbg9JGpbs9WIZjmwLewwy2Uq4V9GmK?= =?us-ascii?Q?phMbznfp/V/VPUchkWvhIZPzTZYp7KWQPkdWqrgxkBAK1VPBmARzn8ZdPUL4?= =?us-ascii?Q?TbiTtlRTXT+WvGm4XcK9Oqu6yfkW/KfAPJ3Wlvs5YpU5YAxYu8Np635KGenu?= =?us-ascii?Q?RPHXxbEyA/aGx9bwEo2snTw31roySSrC04MRHP2HbNaBN62cZVLBj2YxoQcp?= =?us-ascii?Q?6DvRQRGmS3J8uC939RKvhvDZHW6IGNW88p9DGoo+yl99HFAT/+2rd3jVQVdZ?= =?us-ascii?Q?PorASl16no/wuNGLckGe664uMdJoDuP3KigLg0OaZZ2wPeWwhQwxJD9wzGNq?= =?us-ascii?Q?sDDA4hGjOReJqFLhWgWOCFgNM6sv1+P4kgRboQtnJVhWRt4MSImF5Aj6SzGo?= =?us-ascii?Q?w7ekQIDIFH8cMKKaXZHN+zsRC0UVnOkT553tsUAsvFCu3f+pQHjnCtLPHMtU?= =?us-ascii?Q?Raoxy72Y7r9KmNg8j7dNE2nJospHNyUA77JptEzqC0rSa2Cr1YqPLCMMzCc6?= =?us-ascii?Q?WxpYhnlDXVav+YmHkG6EEbxHKpcBY0NEGpVeQSgtM2oPQ/Hk2ZPeZn7Erq16?= =?us-ascii?Q?vzeVpg86Swa9SNh0ETVmqLz6VF4lW7BF2zbksdM1vaiYwH75PG4z0OuL57/E?= =?us-ascii?Q?MlQqQ7rJuNH0IOLy+nNSfjFyR8ZuKGiU5nurwmdQ9sNidiQHWPaN3OuBMZZd?= =?us-ascii?Q?NKckeBdNYIWIaldBoL6eLC3icUeDXGK2oQCc/0I0ldj3cYSN4FKHRzjL2Bko?= =?us-ascii?Q?4u8GNL1tyT+I0ZB9tit2ECguFgSxvMMeRL2M?= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(36860700013)(1800799024)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Sep 2025 09:02:15.3358 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f0c4cfe8-4f96-4631-0907-08ddf9b6b9e8 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF00000149.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB6461 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Carolina Jubran Introduce a dedicated structure to group RSS initialization parameters that are only used during RSS creation, and drop the "init" prefix from pkt_merge_param. No functional changes. Signed-off-by: Carolina Jubran Signed-off-by: Tariq Toukan --- .../net/ethernet/mellanox/mlx5/core/en/rss.c | 49 ++++++++++--------- .../net/ethernet/mellanox/mlx5/core/en/rss.h | 22 ++++++--- .../ethernet/mellanox/mlx5/core/en/rx_res.c | 29 ++++++++--- .../ethernet/mellanox/mlx5/core/en/rx_res.h | 2 +- 4 files changed, 63 insertions(+), 39 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/rss.c b/drivers/net= /ethernet/mellanox/mlx5/core/en/rss.c index 6422eeabc334..c3eeeec62129 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/rss.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/rss.c @@ -193,10 +193,10 @@ mlx5e_rss_get_tt_config(struct mlx5e_rss *rss, enum m= lx5_traffic_types tt) return rss_tt; } =20 -static int mlx5e_rss_create_tir(struct mlx5e_rss *rss, - enum mlx5_traffic_types tt, - const struct mlx5e_packet_merge_param *init_pkt_merge_param, - bool inner) +static int +mlx5e_rss_create_tir(struct mlx5e_rss *rss, enum mlx5_traffic_types tt, + const struct mlx5e_packet_merge_param *pkt_merge_param, + bool inner) { struct mlx5e_rss_params_traffic_type rss_tt; struct mlx5e_tir_builder *builder; @@ -229,7 +229,7 @@ static int mlx5e_rss_create_tir(struct mlx5e_rss *rss, rqtn =3D mlx5e_rqt_get_rqtn(&rss->rqt); mlx5e_tir_builder_build_rqt(builder, rss->mdev->mlx5e_res.hw_objs.td.tdn, rqtn, rss->inner_ft_support); - mlx5e_tir_builder_build_packet_merge(builder, init_pkt_merge_param); + mlx5e_tir_builder_build_packet_merge(builder, pkt_merge_param); rss_tt =3D mlx5e_rss_get_tt_config(rss, tt); mlx5e_tir_builder_build_rss(builder, &rss->hash, &rss_tt, inner); =20 @@ -265,15 +265,16 @@ static void mlx5e_rss_destroy_tir(struct mlx5e_rss *r= ss, enum mlx5_traffic_types *tir_p =3D NULL; } =20 -static int mlx5e_rss_create_tirs(struct mlx5e_rss *rss, - const struct mlx5e_packet_merge_param *init_pkt_merge_param, - bool inner) +static int +mlx5e_rss_create_tirs(struct mlx5e_rss *rss, + const struct mlx5e_packet_merge_param *pkt_merge_param, + bool inner) { enum mlx5_traffic_types tt, max_tt; int err; =20 for (tt =3D 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) { - err =3D mlx5e_rss_create_tir(rss, tt, init_pkt_merge_param, inner); + err =3D mlx5e_rss_create_tir(rss, tt, pkt_merge_param, inner); if (err) goto err_destroy_tirs; } @@ -359,10 +360,9 @@ static int mlx5e_rss_init_no_tirs(struct mlx5e_rss *rs= s) rss->drop_rqn, rss->indir.max_table_size); } =20 -struct mlx5e_rss *mlx5e_rss_init(struct mlx5_core_dev *mdev, bool inner_ft= _support, u32 drop_rqn, - const struct mlx5e_packet_merge_param *init_pkt_merge_param, - enum mlx5e_rss_init_type type, unsigned int nch, - unsigned int max_nch) +struct mlx5e_rss * +mlx5e_rss_init(struct mlx5_core_dev *mdev, bool inner_ft_support, u32 drop= _rqn, + const struct mlx5e_rss_init_params *init_params) { u32 rqt_max_size, rqt_size; struct mlx5e_rss *rss; @@ -372,8 +372,8 @@ struct mlx5e_rss *mlx5e_rss_init(struct mlx5_core_dev *= mdev, bool inner_ft_suppo if (!rss) return ERR_PTR(-ENOMEM); =20 - rqt_size =3D mlx5e_rqt_size(mdev, nch); - rqt_max_size =3D mlx5e_rqt_size(mdev, max_nch); + rqt_size =3D mlx5e_rqt_size(mdev, init_params->nch); + rqt_max_size =3D mlx5e_rqt_size(mdev, init_params->max_nch); err =3D mlx5e_rss_params_indir_init(&rss->indir, rqt_size, rqt_max_size); if (err) goto err_free_rss; @@ -386,15 +386,18 @@ struct mlx5e_rss *mlx5e_rss_init(struct mlx5_core_dev= *mdev, bool inner_ft_suppo if (err) goto err_free_indir; =20 - if (type =3D=3D MLX5E_RSS_INIT_NO_TIRS) + if (init_params->type =3D=3D MLX5E_RSS_INIT_NO_TIRS) goto out; =20 - err =3D mlx5e_rss_create_tirs(rss, init_pkt_merge_param, false); + err =3D mlx5e_rss_create_tirs(rss, init_params->pkt_merge_param, + false); if (err) goto err_destroy_rqt; =20 if (inner_ft_support) { - err =3D mlx5e_rss_create_tirs(rss, init_pkt_merge_param, true); + err =3D mlx5e_rss_create_tirs(rss, + init_params->pkt_merge_param, + true); if (err) goto err_destroy_tirs; } @@ -470,10 +473,10 @@ bool mlx5e_rss_valid_tir(struct mlx5e_rss *rss, enum = mlx5_traffic_types tt, bool /* Fill the "tirn" output parameter. * Create the requested TIR if it's its first usage. */ -int mlx5e_rss_obtain_tirn(struct mlx5e_rss *rss, - enum mlx5_traffic_types tt, - const struct mlx5e_packet_merge_param *init_pkt_merge_param, - bool inner, u32 *tirn) +int +mlx5e_rss_obtain_tirn(struct mlx5e_rss *rss, enum mlx5_traffic_types tt, + const struct mlx5e_packet_merge_param *pkt_merge_param, + bool inner, u32 *tirn) { struct mlx5e_tir *tir; =20 @@ -481,7 +484,7 @@ int mlx5e_rss_obtain_tirn(struct mlx5e_rss *rss, if (!tir) { /* TIR doesn't exist, create one */ int err; =20 - err =3D mlx5e_rss_create_tir(rss, tt, init_pkt_merge_param, inner); + err =3D mlx5e_rss_create_tir(rss, tt, pkt_merge_param, inner); if (err) return err; tir =3D rss_get_tir(rss, tt, inner); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/rss.h b/drivers/net= /ethernet/mellanox/mlx5/core/en/rss.h index 616097c8770e..80225709675b 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/rss.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/rss.h @@ -13,6 +13,13 @@ enum mlx5e_rss_init_type { MLX5E_RSS_INIT_TIRS }; =20 +struct mlx5e_rss_init_params { + enum mlx5e_rss_init_type type; + const struct mlx5e_packet_merge_param *pkt_merge_param; + unsigned int nch; + unsigned int max_nch; +}; + struct mlx5e_rss_params_traffic_type mlx5e_rss_get_default_tt_config(enum mlx5_traffic_types tt); =20 @@ -22,10 +29,9 @@ int mlx5e_rss_params_indir_init(struct mlx5e_rss_params_= indir *indir, u32 actual_table_size, u32 max_table_size); void mlx5e_rss_params_indir_cleanup(struct mlx5e_rss_params_indir *indir); void mlx5e_rss_params_indir_modify_actual_size(struct mlx5e_rss *rss, u32 = num_channels); -struct mlx5e_rss *mlx5e_rss_init(struct mlx5_core_dev *mdev, bool inner_ft= _support, u32 drop_rqn, - const struct mlx5e_packet_merge_param *init_pkt_merge_param, - enum mlx5e_rss_init_type type, unsigned int nch, - unsigned int max_nch); +struct mlx5e_rss * +mlx5e_rss_init(struct mlx5_core_dev *mdev, bool inner_ft_support, u32 drop= _rqn, + const struct mlx5e_rss_init_params *init_params); int mlx5e_rss_cleanup(struct mlx5e_rss *rss); =20 void mlx5e_rss_refcnt_inc(struct mlx5e_rss *rss); @@ -37,10 +43,10 @@ u32 mlx5e_rss_get_tirn(struct mlx5e_rss *rss, enum mlx5= _traffic_types tt, bool inner); bool mlx5e_rss_valid_tir(struct mlx5e_rss *rss, enum mlx5_traffic_types tt= , bool inner); u32 mlx5e_rss_get_rqtn(struct mlx5e_rss *rss); -int mlx5e_rss_obtain_tirn(struct mlx5e_rss *rss, - enum mlx5_traffic_types tt, - const struct mlx5e_packet_merge_param *init_pkt_merge_param, - bool inner, u32 *tirn); +int +mlx5e_rss_obtain_tirn(struct mlx5e_rss *rss, enum mlx5_traffic_types tt, + const struct mlx5e_packet_merge_param *pkt_merge_param, + bool inner, u32 *tirn); =20 void mlx5e_rss_enable(struct mlx5e_rss *rss, u32 *rqns, u32 *vhca_ids, uns= igned int num_rqns); void mlx5e_rss_disable(struct mlx5e_rss *rss); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/rx_res.c b/drivers/= net/ethernet/mellanox/mlx5/core/en/rx_res.c index a2acbfee2b77..74dda61e92bc 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/rx_res.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/rx_res.c @@ -54,17 +54,25 @@ static int mlx5e_rx_res_rss_init_def(struct mlx5e_rx_re= s *res, unsigned int init_nch) { bool inner_ft_support =3D res->features & MLX5E_RX_RES_FEATURE_INNER_FT; + struct mlx5e_rss_init_params init_params; struct mlx5e_rss *rss; =20 if (WARN_ON(res->rss[0])) return -EINVAL; =20 + init_params =3D (struct mlx5e_rss_init_params) { + .type =3D MLX5E_RSS_INIT_TIRS, + .pkt_merge_param =3D &res->pkt_merge_param, + .nch =3D init_nch, + .max_nch =3D res->max_nch, + }; + rss =3D mlx5e_rss_init(res->mdev, inner_ft_support, res->drop_rqn, - &res->pkt_merge_param, MLX5E_RSS_INIT_TIRS, init_nch, res->max_nch= ); + &init_params); if (IS_ERR(rss)) return PTR_ERR(rss); =20 - mlx5e_rss_set_indir_uniform(rss, init_nch); + mlx5e_rss_set_indir_uniform(rss, init_params.nch); =20 res->rss[0] =3D rss; =20 @@ -74,18 +82,25 @@ static int mlx5e_rx_res_rss_init_def(struct mlx5e_rx_re= s *res, int mlx5e_rx_res_rss_init(struct mlx5e_rx_res *res, u32 rss_idx, unsigned = int init_nch) { bool inner_ft_support =3D res->features & MLX5E_RX_RES_FEATURE_INNER_FT; + struct mlx5e_rss_init_params init_params; struct mlx5e_rss *rss; =20 if (WARN_ON_ONCE(res->rss[rss_idx])) return -ENOSPC; =20 + init_params =3D (struct mlx5e_rss_init_params) { + .type =3D MLX5E_RSS_INIT_NO_TIRS, + .pkt_merge_param =3D &res->pkt_merge_param, + .nch =3D init_nch, + .max_nch =3D res->max_nch, + }; + rss =3D mlx5e_rss_init(res->mdev, inner_ft_support, res->drop_rqn, - &res->pkt_merge_param, MLX5E_RSS_INIT_NO_TIRS, init_nch, - res->max_nch); + &init_params); if (IS_ERR(rss)) return PTR_ERR(rss); =20 - mlx5e_rss_set_indir_uniform(rss, init_nch); + mlx5e_rss_set_indir_uniform(rss, init_params.nch); if (res->rss_active) { u32 *vhca_ids =3D get_vhca_ids(res, 0); =20 @@ -438,7 +453,7 @@ static void mlx5e_rx_res_ptp_destroy(struct mlx5e_rx_re= s *res) struct mlx5e_rx_res * mlx5e_rx_res_create(struct mlx5_core_dev *mdev, enum mlx5e_rx_res_features= features, unsigned int max_nch, u32 drop_rqn, - const struct mlx5e_packet_merge_param *init_pkt_merge_param, + const struct mlx5e_packet_merge_param *pkt_merge_param, unsigned int init_nch) { bool multi_vhca =3D features & MLX5E_RX_RES_FEATURE_MULTI_VHCA; @@ -454,7 +469,7 @@ mlx5e_rx_res_create(struct mlx5_core_dev *mdev, enum ml= x5e_rx_res_features featu res->max_nch =3D max_nch; res->drop_rqn =3D drop_rqn; =20 - res->pkt_merge_param =3D *init_pkt_merge_param; + res->pkt_merge_param =3D *pkt_merge_param; init_rwsem(&res->pkt_merge_param_sem); =20 err =3D mlx5e_rx_res_rss_init_def(res, init_nch); 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Pass this struct instead of individual arguments when initializing RSS. No functional changes. Signed-off-by: Carolina Jubran Signed-off-by: Tariq Toukan --- .../net/ethernet/mellanox/mlx5/core/en/rss.c | 36 ++++++++++--------- .../net/ethernet/mellanox/mlx5/core/en/rss.h | 8 ++++- .../ethernet/mellanox/mlx5/core/en/rx_res.c | 18 +++++++--- 3 files changed, 40 insertions(+), 22 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/rss.c b/drivers/net= /ethernet/mellanox/mlx5/core/en/rss.c index c3eeeec62129..c96cbc4b0dbf 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/rss.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/rss.c @@ -75,15 +75,14 @@ struct mlx5e_rss { struct mlx5e_tir *inner_tir[MLX5E_NUM_INDIR_TIRS]; struct mlx5e_rqt rqt; struct mlx5_core_dev *mdev; /* primary */ - u32 drop_rqn; - bool inner_ft_support; + struct mlx5e_rss_params params; bool enabled; refcount_t refcnt; }; =20 bool mlx5e_rss_get_inner_ft_support(struct mlx5e_rss *rss) { - return rss->inner_ft_support; + return rss->params.inner_ft_support; } =20 void mlx5e_rss_params_indir_modify_actual_size(struct mlx5e_rss *rss, u32 = num_channels) @@ -198,6 +197,7 @@ mlx5e_rss_create_tir(struct mlx5e_rss *rss, enum mlx5_t= raffic_types tt, const struct mlx5e_packet_merge_param *pkt_merge_param, bool inner) { + bool rss_inner =3D rss->params.inner_ft_support; struct mlx5e_rss_params_traffic_type rss_tt; struct mlx5e_tir_builder *builder; struct mlx5e_tir **tir_p; @@ -205,7 +205,7 @@ mlx5e_rss_create_tir(struct mlx5e_rss *rss, enum mlx5_t= raffic_types tt, u32 rqtn; int err; =20 - if (inner && !rss->inner_ft_support) { + if (inner && !rss_inner) { mlx5e_rss_warn(rss->mdev, "Cannot create inner indirect TIR[%d], RSS inner FT is not suppo= rted.\n", tt); @@ -228,7 +228,7 @@ mlx5e_rss_create_tir(struct mlx5e_rss *rss, enum mlx5_t= raffic_types tt, =20 rqtn =3D mlx5e_rqt_get_rqtn(&rss->rqt); mlx5e_tir_builder_build_rqt(builder, rss->mdev->mlx5e_res.hw_objs.td.tdn, - rqtn, rss->inner_ft_support); + rqtn, rss_inner); mlx5e_tir_builder_build_packet_merge(builder, pkt_merge_param); rss_tt =3D mlx5e_rss_get_tt_config(rss, tt); mlx5e_tir_builder_build_rss(builder, &rss->hash, &rss_tt, inner); @@ -337,7 +337,7 @@ static int mlx5e_rss_update_tirs(struct mlx5e_rss *rss) tt, err); } =20 - if (!rss->inner_ft_support) + if (!rss->params.inner_ft_support) continue; =20 err =3D mlx5e_rss_update_tir(rss, tt, true); @@ -357,11 +357,13 @@ static int mlx5e_rss_init_no_tirs(struct mlx5e_rss *r= ss) refcount_set(&rss->refcnt, 1); =20 return mlx5e_rqt_init_direct(&rss->rqt, rss->mdev, true, - rss->drop_rqn, rss->indir.max_table_size); + rss->params.drop_rqn, + rss->indir.max_table_size); } =20 struct mlx5e_rss * -mlx5e_rss_init(struct mlx5_core_dev *mdev, bool inner_ft_support, u32 drop= _rqn, +mlx5e_rss_init(struct mlx5_core_dev *mdev, + const struct mlx5e_rss_params *params, const struct mlx5e_rss_init_params *init_params) { u32 rqt_max_size, rqt_size; @@ -379,8 +381,7 @@ mlx5e_rss_init(struct mlx5_core_dev *mdev, bool inner_f= t_support, u32 drop_rqn, goto err_free_rss; =20 rss->mdev =3D mdev; - rss->inner_ft_support =3D inner_ft_support; - rss->drop_rqn =3D drop_rqn; + rss->params =3D *params; =20 err =3D mlx5e_rss_init_no_tirs(rss); if (err) @@ -394,7 +395,7 @@ mlx5e_rss_init(struct mlx5_core_dev *mdev, bool inner_f= t_support, u32 drop_rqn, if (err) goto err_destroy_rqt; =20 - if (inner_ft_support) { + if (params->inner_ft_support) { err =3D mlx5e_rss_create_tirs(rss, init_params->pkt_merge_param, true); @@ -423,7 +424,7 @@ int mlx5e_rss_cleanup(struct mlx5e_rss *rss) =20 mlx5e_rss_destroy_tirs(rss, false); =20 - if (rss->inner_ft_support) + if (rss->params.inner_ft_support) mlx5e_rss_destroy_tirs(rss, true); =20 mlx5e_rqt_destroy(&rss->rqt); @@ -453,7 +454,7 @@ u32 mlx5e_rss_get_tirn(struct mlx5e_rss *rss, enum mlx5= _traffic_types tt, { struct mlx5e_tir *tir; =20 - WARN_ON(inner && !rss->inner_ft_support); + WARN_ON(inner && !rss->params.inner_ft_support); tir =3D rss_get_tir(rss, tt, inner); WARN_ON(!tir); =20 @@ -517,10 +518,11 @@ void mlx5e_rss_disable(struct mlx5e_rss *rss) int err; =20 rss->enabled =3D false; - err =3D mlx5e_rqt_redirect_direct(&rss->rqt, rss->drop_rqn, NULL); + err =3D mlx5e_rqt_redirect_direct(&rss->rqt, rss->params.drop_rqn, NULL); if (err) mlx5e_rss_warn(rss->mdev, "Failed to redirect RQT %#x to drop RQ %#x: er= r =3D %d\n", - mlx5e_rqt_get_rqtn(&rss->rqt), rss->drop_rqn, err); + mlx5e_rqt_get_rqtn(&rss->rqt), + rss->params.drop_rqn, err); } =20 int mlx5e_rss_packet_merge_set_param(struct mlx5e_rss *rss, @@ -553,7 +555,7 @@ int mlx5e_rss_packet_merge_set_param(struct mlx5e_rss *= rss, } =20 inner_tir: - if (!rss->inner_ft_support) + if (!rss->params.inner_ft_support) continue; =20 tir =3D rss_get_tir(rss, tt, true); @@ -686,7 +688,7 @@ int mlx5e_rss_set_hash_fields(struct mlx5e_rss *rss, en= um mlx5_traffic_types tt, return err; } =20 - if (!(rss->inner_ft_support)) + if (!(rss->params.inner_ft_support)) return 0; =20 err =3D mlx5e_rss_update_tir(rss, tt, true); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/rss.h b/drivers/net= /ethernet/mellanox/mlx5/core/en/rss.h index 80225709675b..5fb03cd0a411 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/rss.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/rss.h @@ -20,6 +20,11 @@ struct mlx5e_rss_init_params { unsigned int max_nch; }; =20 +struct mlx5e_rss_params { + bool inner_ft_support; + u32 drop_rqn; +}; + struct mlx5e_rss_params_traffic_type mlx5e_rss_get_default_tt_config(enum mlx5_traffic_types tt); =20 @@ -30,7 +35,8 @@ int mlx5e_rss_params_indir_init(struct mlx5e_rss_params_i= ndir *indir, void mlx5e_rss_params_indir_cleanup(struct mlx5e_rss_params_indir *indir); void mlx5e_rss_params_indir_modify_actual_size(struct mlx5e_rss *rss, u32 = num_channels); struct mlx5e_rss * -mlx5e_rss_init(struct mlx5_core_dev *mdev, bool inner_ft_support, u32 drop= _rqn, +mlx5e_rss_init(struct mlx5_core_dev *mdev, + const struct mlx5e_rss_params *params, const struct mlx5e_rss_init_params *init_params); int mlx5e_rss_cleanup(struct mlx5e_rss *rss); =20 diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/rx_res.c b/drivers/= net/ethernet/mellanox/mlx5/core/en/rx_res.c index 74dda61e92bc..ac26a32845d0 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/rx_res.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/rx_res.c @@ -55,6 +55,7 @@ static int mlx5e_rx_res_rss_init_def(struct mlx5e_rx_res = *res, { bool inner_ft_support =3D res->features & MLX5E_RX_RES_FEATURE_INNER_FT; struct mlx5e_rss_init_params init_params; + struct mlx5e_rss_params rss_params; struct mlx5e_rss *rss; =20 if (WARN_ON(res->rss[0])) @@ -67,8 +68,12 @@ static int mlx5e_rx_res_rss_init_def(struct mlx5e_rx_res= *res, .max_nch =3D res->max_nch, }; =20 - rss =3D mlx5e_rss_init(res->mdev, inner_ft_support, res->drop_rqn, - &init_params); + rss_params =3D (struct mlx5e_rss_params) { + .inner_ft_support =3D inner_ft_support, + .drop_rqn =3D res->drop_rqn, + }; + + rss =3D mlx5e_rss_init(res->mdev, &rss_params, &init_params); if (IS_ERR(rss)) return PTR_ERR(rss); =20 @@ -83,6 +88,7 @@ int mlx5e_rx_res_rss_init(struct mlx5e_rx_res *res, u32 r= ss_idx, unsigned int in { bool inner_ft_support =3D res->features & MLX5E_RX_RES_FEATURE_INNER_FT; struct mlx5e_rss_init_params init_params; + struct mlx5e_rss_params rss_params; struct mlx5e_rss *rss; =20 if (WARN_ON_ONCE(res->rss[rss_idx])) @@ -95,8 +101,12 @@ int mlx5e_rx_res_rss_init(struct mlx5e_rx_res *res, u32= rss_idx, unsigned int in .max_nch =3D res->max_nch, }; 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Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , , , , Gal Pressman , Moshe Shemesh Subject: [PATCH net-next 7/7] net/mlx5e: Use extack in set rxfh callback Date: Mon, 22 Sep 2025 12:01:11 +0300 Message-ID: <1758531671-819655-8-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1758531671-819655-1-git-send-email-tariqt@nvidia.com> References: <1758531671-819655-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PEPF0000B071:EE_|DM4PR12MB6207:EE_ X-MS-Office365-Filtering-Correlation-Id: 0792bd8b-7a54-40df-d598-08ddf9b6bf5f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|376014|36860700013|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?RMZVpRAsQg/7r3X9KH7citZNlJ3sa+ZH9uFStp0GbZYeBhf8Kz1/OxjNVxe/?= =?us-ascii?Q?EiJMvkSv6CWKrBi65eJaPsMJo+84n7npkWof0Wt5ffNdk6b6Ha2fvHNfsmbz?= =?us-ascii?Q?n1DroU286NbbKzkym5ykgSlK0HErIgY+lTiPQaLcclHw0kIrcEF2hO4RkATx?= =?us-ascii?Q?avSVr6UgQhlE9slSVrf3w+mgciQw4SoVmDn1cngWGIkFbrMQMbVea+3+5WPp?= =?us-ascii?Q?IFyTgPEmHr92fX1yFEDhzny3pB73n0BTWPMf7GeS16J/p5kdpam+JF8d0yUu?= =?us-ascii?Q?ywioqi4Mk8/Pdbg++DoITeOUwHhNffYiYhkuqhuKnJIvgQWkWPwrYFvs2GjE?= =?us-ascii?Q?PaF56ZzYoOGmSUCS8t3fI0wtW8JALJfu8atsFneV+F05bDErgCULADgNdMaO?= =?us-ascii?Q?fiiPTND+x5iTXxby4Tm6oR4Sw7YdRRXXEPkddhnPTQAbUc/SjTJsLqa/Sn1E?= =?us-ascii?Q?LFv1ixK44n/uIzwkIyjhirF1nW8o0jzHQXTcb78hbhtiKAoRAbZnZP3U/G3k?= =?us-ascii?Q?fg466Z9tUVyt4ms0ZS+UsNDna0RAbYm2Xo0czTH1TnSzu0OYKKh1kblt0+S1?= =?us-ascii?Q?+B7lKMYyEM3T7YJMpNz2UyS+t8839MAKtVLukWHwqW67ybYgOeAcjkazPV6P?= =?us-ascii?Q?1CaRPsYaOuG1xovGx5CQsXOP4seOf7zawmYlya1FZcYVY9z37KJENlLF375O?= =?us-ascii?Q?ekPr3ncgug9dxB9tYqBNp5W0caxkkPgYqZelHn64mQdDt3L4UXmth8ZVb7DY?= =?us-ascii?Q?zPm96UEKaX/n8bbg7ideYh/eJj/zNhnxpnHL0QEq8MlDkZpGlHsXE8YrR8fG?= =?us-ascii?Q?LB+xPYD+PjgjbMNkC6R9CGGEoKkb1RszuljXW1WctSEDZUCenP5Sv1tDEhfb?= =?us-ascii?Q?TeeWJE5Gqy4R17frlFlIN1/XYl7SeP4dfeYjHT+oq05ihjmV7OC1qxv4Hz7u?= =?us-ascii?Q?GznrjTz8Rb+lLjmRjj+epmBT2uUeUns3f2TnLIVj2Y6hVvcC1J/tLV14FdtV?= =?us-ascii?Q?Uy3t+2xKHMvEnJ2Sd8NCx8W4CDlArFzIeHCD+WLIkXi5ElGD7f+LsegoBUjy?= =?us-ascii?Q?3TO2VYdCUn5oqDr8kcJV2bVGAURBkkL3i9c7rzbus6H5J1z3X+bF2hXgoyRZ?= =?us-ascii?Q?JIPlH2/NORV19fY6NPnGXqpZEvq7tB7DLkMGHpGoeLfkoQT1dSt5xFHPqK8K?= =?us-ascii?Q?8tLJokUnoL5X+5vg+HFJ1iOc45iY/CPUnZIjz0WRTf6YCXobj6zFFTX2YxKM?= =?us-ascii?Q?T41uWaiBiQ51v/mzcDpztVOnt2pcJW6KE4BXqz1C66GAHDukjaJvtEwJagEf?= =?us-ascii?Q?WneDWHkhoBRSHzglXqFr45zrQgCwqKNLXYz87X1mO2siHJpt7nl5N+N5XWbv?= =?us-ascii?Q?ELHpb3xree5H3ibtBP8wET5V8Pr1JPBXdUzSVwcC0J4LxiXTLgcbh0KEBFi7?= =?us-ascii?Q?mB7V4OqocbcJTSv4WEvVQiKacUS+brbxbjxNnEMYmz381c/DnwUWiJ2LVJLY?= =?us-ascii?Q?EHHq2XPPbsXrjG0g1Cp6L/5cj5L5XmjDuYe9?= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(376014)(36860700013)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Sep 2025 09:02:24.4746 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0792bd8b-7a54-40df-d598-08ddf9b6bf5f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B071.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6207 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Gal Pressman The ->set_rxfh() callback now passes a valid extack instead of NULL through netlink [1]. In case of an error, reflect it through extack instead of a dmesg print. [1] commit c0ae03588bbb ("ethtool: rss: initial RSS_SET (indirection table hand= ling)") Signed-off-by: Gal Pressman Reviewed-by: Dragos Tatulea Signed-off-by: Tariq Toukan --- .../net/ethernet/mellanox/mlx5/core/en_ethtool.c | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c b/drivers= /net/ethernet/mellanox/mlx5/core/en_ethtool.c index d507366d773e..eb25b19b4a4a 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c @@ -1494,7 +1494,8 @@ static int mlx5e_get_rxfh(struct net_device *netdev, = struct ethtool_rxfh_param * } =20 static int mlx5e_rxfh_hfunc_check(struct mlx5e_priv *priv, - const struct ethtool_rxfh_param *rxfh) + const struct ethtool_rxfh_param *rxfh, + struct netlink_ext_ack *extack) { unsigned int count; =20 @@ -1504,8 +1505,10 @@ static int mlx5e_rxfh_hfunc_check(struct mlx5e_priv = *priv, unsigned int xor8_max_channels =3D mlx5e_rqt_max_num_channels_allowed_fo= r_xor8(); =20 if (count > xor8_max_channels) { - netdev_err(priv->netdev, "%s: Cannot set RSS hash function to XOR, curr= ent number of channels (%d) exceeds the maximum allowed for XOR8 RSS hfunc = (%d)\n", - __func__, count, xor8_max_channels); + NL_SET_ERR_MSG_FMT_MOD( + extack, + "Cannot set RSS hash function to XOR, current number of channels (%d) = exceeds the maximum allowed for XOR8 RSS hfunc (%d)\n", + count, xor8_max_channels); return -EINVAL; } } @@ -1524,7 +1527,7 @@ static int mlx5e_set_rxfh(struct net_device *dev, =20 mutex_lock(&priv->state_lock); =20 - err =3D mlx5e_rxfh_hfunc_check(priv, rxfh); + err =3D mlx5e_rxfh_hfunc_check(priv, rxfh, extack); if (err) goto unlock; =20 @@ -1550,7 +1553,7 @@ static int mlx5e_create_rxfh_context(struct net_devic= e *dev, =20 mutex_lock(&priv->state_lock); =20 - err =3D mlx5e_rxfh_hfunc_check(priv, rxfh); + err =3D mlx5e_rxfh_hfunc_check(priv, rxfh, extack); if (err) goto unlock; =20 @@ -1590,7 +1593,7 @@ static int mlx5e_modify_rxfh_context(struct net_devic= e *dev, =20 mutex_lock(&priv->state_lock); =20 - err =3D mlx5e_rxfh_hfunc_check(priv, rxfh); + err =3D mlx5e_rxfh_hfunc_check(priv, rxfh, extack); if (err) goto unlock; =20 --=20 2.31.1