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Sun, 21 Sep 2025 23:06:49 -0700 From: Tariq Toukan To: Saeed Mahameed , Leon Romanovsky CC: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" , Tariq Toukan , "Mark Bloch" , , , , Gal Pressman Subject: [PATCH mlx5-next 1/2] net/mlx5: Add IFC bit for TIR/SQ order capability Date: Mon, 22 Sep 2025 09:06:30 +0300 Message-ID: <1758521191-814350-2-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1758521191-814350-1-git-send-email-tariqt@nvidia.com> References: <1758521191-814350-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MN1PEPF0000F0DE:EE_|DS4PR12MB9659:EE_ X-MS-Office365-Filtering-Correlation-Id: 2a1e616d-cc6d-419e-1bac-08ddf99e44cf X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|36860700013|82310400026|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?Guz8gqJOSbSb6Tniagf2I+Mottnzq6JYENfLeBhxgNPVsyyvh8I3uSneh4jV?= =?us-ascii?Q?GnhyTZVJUTrlK+MfqdghIJr2SFIM1vygxHYhKknBFKwFQzQvxQJjQCdQ8y+2?= =?us-ascii?Q?s9h1bKXTsJ/7XHoeMgbGweTJRnQ7/sV/IDToewfMJQROdKSGNzRDxKX65m6g?= =?us-ascii?Q?h8iaJ91XSx5KkYYJE+gAeGKUWZkwdf9an0E/LF5mQpzpIgpuEC4LKdumLbAB?= =?us-ascii?Q?5Xv/Gal8ZlycmykPprwzczG4o1YQH0ivwjuNY8XeibpcqSFThr3ksjMORalb?= =?us-ascii?Q?NfWSR7ZjXymyxzj13jblJvrX/N5zP0/yfwBOPbUwMK23rzXz4Qh9D7OC1qlA?= =?us-ascii?Q?ZjSWBzeBBZz+XrT74YqGxVx0c3CmWhI9lZJdbPGU5n6jiZIBeFi2H/HqbZOD?= =?us-ascii?Q?UsA/6dlDxJxqrUc3amiFxCRKtqLiQ+SU4VUOLHYVCrMHQwtOLgufhggHVW0l?= =?us-ascii?Q?YlBA5CcIfGSRzMmDGj0vXyyZa1p/bHEZOyb8mTAs8xw47RC/xziVVLSN+YLS?= =?us-ascii?Q?o11jwvvJDn8oUx1BYPqlXyjpRl2W/4QRxaUeOuIlOb7LTMQpPqt41vJgFHo9?= =?us-ascii?Q?nWvZI+TztJ+Tm1+esgrtqaHjkV5mOdTQNVhFYomS24nMCYerlUYn3cqS6+d3?= =?us-ascii?Q?FNoJefxc5vcgI+XG4C6J0IU5PY4+EMZnrVTG3+76Q6tNs2Icewxmu/emVXU+?= =?us-ascii?Q?LKy+vMtjp7fPTVQSI9NxLIQ1YDpoE/0ETdwQGNI16BtmBdnrMYBft4qlCHMC?= =?us-ascii?Q?FX35ovUMO170miCw0vvhMSPqYztE0NYYxugEiATmj4Tj/kbAuKcNI9U5EjUM?= =?us-ascii?Q?65Zgbmlj3xmJenaTzlqQZfmtLqkWryS1/BULeEaIQ1eegQHpP91FQEz81dUI?= =?us-ascii?Q?7k0u0FRd9LhMF9vJ7qOrUap+PI28LVhFPL2eStGOZq0GpDHUX/AfxqPOSDrb?= =?us-ascii?Q?6YLWrq7zELG0IyPrvlWHtqp6SbsdTs1e9sEMZ1iqvbYi6uxyyWHdAC6PRhOE?= =?us-ascii?Q?kZ8ftCtT78As8aef0QR3EaFRpTyKX+nM1E7gexYdaWOLAzEr6otQlyQZHnZh?= =?us-ascii?Q?7C5diDL82TCpSCKshhiqVaHgAEhkHSe0lPwO4dldVaEgrNufVRVzLOsDFX9O?= =?us-ascii?Q?7axM8WVMHzL/5MRjhhnr7W6BAX1fAmaUI6l+YhMvjeM/5YTw29m2lw3mQvah?= =?us-ascii?Q?EiRUh3dl1wZE5TVKW7fO7ovyT44E6/u7tE/6t/YlRG4/H24g1cBM8hvMLl8e?= =?us-ascii?Q?5s/OYVevjTKCDD+jHbXKSs9UsNTuWy+gyX3un3SiYB2FbWMIb7JtZFJwteMn?= =?us-ascii?Q?GGN4UBzhNXX2l7AE8XiZeAvvCZMHrlXDY4UTPShz0HCwXyADdoVsPK62Jg7G?= =?us-ascii?Q?4mZJO6Wxq4yQY0GZWWn/W/ZSDQe0aXzm60074PrfLBKs4WLd+kZT6ug27o3B?= =?us-ascii?Q?rEDUkMFRjd3tI1iL+G8jBUXAT5hmElRQll1xpLr90sJCebA+9zc+LEV1RqVA?= =?us-ascii?Q?QiTVwKMj+3oZ3/AcTGSENQ1KZVZ46pBQWIAY?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(36860700013)(82310400026)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Sep 2025 06:07:10.9287 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2a1e616d-cc6d-419e-1bac-08ddf99e44cf X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MN1PEPF0000F0DE.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS4PR12MB9659 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Before this cap, firmware requested a certain creation order between TIR objects and SQs of the same transport domain to properly support the self loopback prevention feature. If order is not preserved, explicit modify_tir operations are necessary after the opening of the SQs. When set, this cap bit indicates that this firmware requirement / limitation no longer holds. Signed-off-by: Tariq Toukan Reviewed-by: Carolina Jubran Reviewed-by: Dragos Tatulea --- include/linux/mlx5/mlx5_ifc.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h index 0cf187e13def..c0f5fee7a4a5 100644 --- a/include/linux/mlx5/mlx5_ifc.h +++ b/include/linux/mlx5/mlx5_ifc.h @@ -1895,7 +1895,8 @@ struct mlx5_ifc_cmd_hca_cap_bits { =20 u8 reserved_at_2a0[0x7]; u8 mkey_pcie_tph[0x1]; - u8 reserved_at_2a8[0x2]; + u8 reserved_at_2a8[0x1]; + u8 tis_tir_td_order[0x1]; =20 u8 psp[0x1]; u8 shampo[0x1]; --=20 2.31.1